1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MSDU_START_H_ 20 #define _RX_MSDU_START_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_MSDU_START 10 25 26 #define NUM_OF_QWORDS_RX_MSDU_START 5 27 28 29 struct rx_msdu_start { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rxpcu_mpdu_filter_in_category : 2, 32 sw_frame_group_id : 7, 33 reserved_0 : 7, 34 phy_ppdu_id : 16; 35 uint32_t msdu_length : 14, 36 stbc : 1, 37 ipsec_esp : 1, 38 l3_offset : 7, 39 ipsec_ah : 1, 40 l4_offset : 8; 41 uint32_t msdu_number : 8, 42 decap_format : 2, 43 ipv4_proto : 1, 44 ipv6_proto : 1, 45 tcp_proto : 1, 46 udp_proto : 1, 47 ip_frag : 1, 48 tcp_only_ack : 1, 49 da_is_bcast_mcast : 1, 50 toeplitz_hash_sel : 2, 51 ip_fixed_header_valid : 1, 52 ip_extn_header_valid : 1, 53 tcp_udp_header_valid : 1, 54 mesh_control_present : 1, 55 ldpc : 1, 56 ip4_protocol_ip6_next_header : 8; 57 uint32_t toeplitz_hash_2_or_4 : 32; 58 uint32_t flow_id_toeplitz : 32; 59 uint32_t user_rssi : 8, 60 pkt_type : 4, 61 sgi : 2, 62 rate_mcs : 4, 63 receive_bandwidth : 3, 64 reception_type : 3, 65 mimo_ss_bitmap : 8; 66 uint32_t ppdu_start_timestamp_31_0 : 32; 67 uint32_t ppdu_start_timestamp_63_32 : 32; 68 uint32_t sw_phy_meta_data : 32; 69 uint32_t vlan_ctag_ci : 16, 70 vlan_stag_ci : 16; 71 #else 72 uint32_t phy_ppdu_id : 16, 73 reserved_0 : 7, 74 sw_frame_group_id : 7, 75 rxpcu_mpdu_filter_in_category : 2; 76 uint32_t l4_offset : 8, 77 ipsec_ah : 1, 78 l3_offset : 7, 79 ipsec_esp : 1, 80 stbc : 1, 81 msdu_length : 14; 82 uint32_t ip4_protocol_ip6_next_header : 8, 83 ldpc : 1, 84 mesh_control_present : 1, 85 tcp_udp_header_valid : 1, 86 ip_extn_header_valid : 1, 87 ip_fixed_header_valid : 1, 88 toeplitz_hash_sel : 2, 89 da_is_bcast_mcast : 1, 90 tcp_only_ack : 1, 91 ip_frag : 1, 92 udp_proto : 1, 93 tcp_proto : 1, 94 ipv6_proto : 1, 95 ipv4_proto : 1, 96 decap_format : 2, 97 msdu_number : 8; 98 uint32_t toeplitz_hash_2_or_4 : 32; 99 uint32_t flow_id_toeplitz : 32; 100 uint32_t mimo_ss_bitmap : 8, 101 reception_type : 3, 102 receive_bandwidth : 3, 103 rate_mcs : 4, 104 sgi : 2, 105 pkt_type : 4, 106 user_rssi : 8; 107 uint32_t ppdu_start_timestamp_31_0 : 32; 108 uint32_t ppdu_start_timestamp_63_32 : 32; 109 uint32_t sw_phy_meta_data : 32; 110 uint32_t vlan_stag_ci : 16, 111 vlan_ctag_ci : 16; 112 #endif 113 }; 114 115 116 117 118 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 119 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 120 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 121 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 122 123 124 125 126 #define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 127 #define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 128 #define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 129 #define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 130 131 132 133 134 #define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 135 #define RX_MSDU_START_RESERVED_0_LSB 9 136 #define RX_MSDU_START_RESERVED_0_MSB 15 137 #define RX_MSDU_START_RESERVED_0_MASK 0x000000000000fe00 138 139 140 141 142 #define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 143 #define RX_MSDU_START_PHY_PPDU_ID_LSB 16 144 #define RX_MSDU_START_PHY_PPDU_ID_MSB 31 145 #define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 146 147 148 149 150 #define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 151 #define RX_MSDU_START_MSDU_LENGTH_LSB 32 152 #define RX_MSDU_START_MSDU_LENGTH_MSB 45 153 #define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 154 155 156 157 158 #define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 159 #define RX_MSDU_START_STBC_LSB 46 160 #define RX_MSDU_START_STBC_MSB 46 161 #define RX_MSDU_START_STBC_MASK 0x0000400000000000 162 163 164 165 166 #define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 167 #define RX_MSDU_START_IPSEC_ESP_LSB 47 168 #define RX_MSDU_START_IPSEC_ESP_MSB 47 169 #define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 170 171 172 173 174 #define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 175 #define RX_MSDU_START_L3_OFFSET_LSB 48 176 #define RX_MSDU_START_L3_OFFSET_MSB 54 177 #define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 178 179 180 181 182 #define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 183 #define RX_MSDU_START_IPSEC_AH_LSB 55 184 #define RX_MSDU_START_IPSEC_AH_MSB 55 185 #define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 186 187 188 189 190 #define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 191 #define RX_MSDU_START_L4_OFFSET_LSB 56 192 #define RX_MSDU_START_L4_OFFSET_MSB 63 193 #define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 194 195 196 197 198 #define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 199 #define RX_MSDU_START_MSDU_NUMBER_LSB 0 200 #define RX_MSDU_START_MSDU_NUMBER_MSB 7 201 #define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff 202 203 204 205 206 #define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 207 #define RX_MSDU_START_DECAP_FORMAT_LSB 8 208 #define RX_MSDU_START_DECAP_FORMAT_MSB 9 209 #define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 210 211 212 213 214 #define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 215 #define RX_MSDU_START_IPV4_PROTO_LSB 10 216 #define RX_MSDU_START_IPV4_PROTO_MSB 10 217 #define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 218 219 220 221 222 #define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 223 #define RX_MSDU_START_IPV6_PROTO_LSB 11 224 #define RX_MSDU_START_IPV6_PROTO_MSB 11 225 #define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 226 227 228 229 230 #define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 231 #define RX_MSDU_START_TCP_PROTO_LSB 12 232 #define RX_MSDU_START_TCP_PROTO_MSB 12 233 #define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 234 235 236 237 238 #define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 239 #define RX_MSDU_START_UDP_PROTO_LSB 13 240 #define RX_MSDU_START_UDP_PROTO_MSB 13 241 #define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 242 243 244 245 246 #define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 247 #define RX_MSDU_START_IP_FRAG_LSB 14 248 #define RX_MSDU_START_IP_FRAG_MSB 14 249 #define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 250 251 252 253 254 #define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 255 #define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 256 #define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 257 #define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 258 259 260 261 262 #define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 263 #define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 264 #define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 265 #define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 266 267 268 269 270 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 271 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 272 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 273 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 274 275 276 277 278 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 279 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 280 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 281 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 282 283 284 285 286 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 287 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 288 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 289 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 290 291 292 293 294 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 295 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 296 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 297 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 298 299 300 301 302 #define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 303 #define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 304 #define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 305 #define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 306 307 308 309 310 #define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 311 #define RX_MSDU_START_LDPC_LSB 23 312 #define RX_MSDU_START_LDPC_MSB 23 313 #define RX_MSDU_START_LDPC_MASK 0x0000000000800000 314 315 316 317 318 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 319 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 320 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 321 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 322 323 324 325 326 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 327 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 328 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 329 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 330 331 332 333 334 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 335 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 336 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 337 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff 338 339 340 341 342 #define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 343 #define RX_MSDU_START_USER_RSSI_LSB 32 344 #define RX_MSDU_START_USER_RSSI_MSB 39 345 #define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 346 347 348 349 350 #define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 351 #define RX_MSDU_START_PKT_TYPE_LSB 40 352 #define RX_MSDU_START_PKT_TYPE_MSB 43 353 #define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 354 355 356 357 358 #define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 359 #define RX_MSDU_START_SGI_LSB 44 360 #define RX_MSDU_START_SGI_MSB 45 361 #define RX_MSDU_START_SGI_MASK 0x0000300000000000 362 363 364 365 366 #define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000010 367 #define RX_MSDU_START_RATE_MCS_LSB 46 368 #define RX_MSDU_START_RATE_MCS_MSB 49 369 #define RX_MSDU_START_RATE_MCS_MASK 0x0003c00000000000 370 371 372 373 374 #define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 375 #define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 376 #define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 377 #define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 378 379 380 381 382 #define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 383 #define RX_MSDU_START_RECEPTION_TYPE_LSB 53 384 #define RX_MSDU_START_RECEPTION_TYPE_MSB 55 385 #define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 386 387 388 389 390 #define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 391 #define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 392 #define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 393 #define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 394 395 396 397 398 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 399 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 400 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 401 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 402 403 404 405 406 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 407 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 408 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 409 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 410 411 412 413 414 #define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 415 #define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 416 #define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 417 #define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff 418 419 420 421 422 #define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 423 #define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 424 #define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 425 #define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 426 427 428 429 430 #define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 431 #define RX_MSDU_START_VLAN_STAG_CI_LSB 48 432 #define RX_MSDU_START_VLAN_STAG_CI_MSB 63 433 #define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 434 435 436 437 #endif 438