1 
2 /*
3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4  * SPDX-License-Identifier: ISC
5  */
6 
7 
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16 
17 
18 
19 #ifndef _RU_ALLOCATION_160_INFO_H_
20 #define _RU_ALLOCATION_160_INFO_H_
21 #if !defined(__ASSEMBLER__)
22 #endif
23 
24 #define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
25 
26 
27 struct ru_allocation_160_info {
28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
29              uint32_t ru_allocation_band0_0                                   :  9,
30                       ru_allocation_band0_1                                   :  9,
31                       reserved_0a                                             :  6,
32                       ru_allocations_01_subband80_mask                        :  4,
33                       ru_allocations_23_subband80_mask                        :  4;
34              uint32_t ru_allocation_band0_2                                   :  9,
35                       ru_allocation_band0_3                                   :  9,
36                       reserved_1a                                             : 14;
37              uint32_t ru_allocation_band1_0                                   :  9,
38                       ru_allocation_band1_1                                   :  9,
39                       reserved_2a                                             : 14;
40              uint32_t ru_allocation_band1_2                                   :  9,
41                       ru_allocation_band1_3                                   :  9,
42                       reserved_3a                                             : 14;
43 #else
44              uint32_t ru_allocations_23_subband80_mask                        :  4,
45                       ru_allocations_01_subband80_mask                        :  4,
46                       reserved_0a                                             :  6,
47                       ru_allocation_band0_1                                   :  9,
48                       ru_allocation_band0_0                                   :  9;
49              uint32_t reserved_1a                                             : 14,
50                       ru_allocation_band0_3                                   :  9,
51                       ru_allocation_band0_2                                   :  9;
52              uint32_t reserved_2a                                             : 14,
53                       ru_allocation_band1_1                                   :  9,
54                       ru_allocation_band1_0                                   :  9;
55              uint32_t reserved_3a                                             : 14,
56                       ru_allocation_band1_3                                   :  9,
57                       ru_allocation_band1_2                                   :  9;
58 #endif
59 };
60 
61 
62 
63 
64 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET                         0x00000000
65 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB                            0
66 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB                            8
67 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK                           0x000001ff
68 
69 
70 
71 
72 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET                         0x00000000
73 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB                            9
74 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB                            17
75 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK                           0x0003fe00
76 
77 
78 
79 
80 #define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET                                   0x00000000
81 #define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB                                      18
82 #define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB                                      23
83 #define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK                                     0x00fc0000
84 
85 
86 
87 
88 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET              0x00000000
89 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB                 24
90 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB                 27
91 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK                0x0f000000
92 
93 
94 
95 
96 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET              0x00000000
97 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB                 28
98 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB                 31
99 #define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK                0xf0000000
100 
101 
102 
103 
104 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET                         0x00000004
105 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB                            0
106 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB                            8
107 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK                           0x000001ff
108 
109 
110 
111 
112 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET                         0x00000004
113 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB                            9
114 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB                            17
115 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK                           0x0003fe00
116 
117 
118 
119 
120 #define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET                                   0x00000004
121 #define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB                                      18
122 #define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB                                      31
123 #define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK                                     0xfffc0000
124 
125 
126 
127 
128 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET                         0x00000008
129 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB                            0
130 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB                            8
131 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK                           0x000001ff
132 
133 
134 
135 
136 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET                         0x00000008
137 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB                            9
138 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB                            17
139 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK                           0x0003fe00
140 
141 
142 
143 
144 #define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET                                   0x00000008
145 #define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB                                      18
146 #define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB                                      31
147 #define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK                                     0xfffc0000
148 
149 
150 
151 
152 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET                         0x0000000c
153 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB                            0
154 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB                            8
155 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK                           0x000001ff
156 
157 
158 
159 
160 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET                         0x0000000c
161 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB                            9
162 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB                            17
163 #define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK                           0x0003fe00
164 
165 
166 
167 
168 #define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET                                   0x0000000c
169 #define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB                                      18
170 #define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB                                      31
171 #define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK                                     0xfffc0000
172 
173 
174 
175 #endif
176