1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_ENTRANCE_RING_H_ 20 #define _REO_ENTRANCE_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rx_mpdu_details.h" 25 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 26 27 28 struct reo_entrance_ring { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct rx_mpdu_details reo_level_mpdu_frame_info; 31 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 32 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 33 rounded_mpdu_byte_count : 14, 34 reo_destination_indication : 5, 35 frameless_bar : 1, 36 reserved_5a : 4; 37 uint32_t rxdma_push_reason : 2, 38 rxdma_error_code : 5, 39 mpdu_fragment_number : 4, 40 sw_exception : 1, 41 sw_exception_mpdu_delink : 1, 42 sw_exception_destination_ring_valid : 1, 43 sw_exception_destination_ring : 5, 44 mpdu_sequence_number : 12, 45 reserved_6a : 1; 46 uint32_t phy_ppdu_id : 16, 47 src_link_id : 3, 48 reserved_7a : 1, 49 ring_id : 8, 50 looping_count : 4; 51 #else 52 struct rx_mpdu_details reo_level_mpdu_frame_info; 53 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 54 uint32_t reserved_5a : 4, 55 frameless_bar : 1, 56 reo_destination_indication : 5, 57 rounded_mpdu_byte_count : 14, 58 rx_reo_queue_desc_addr_39_32 : 8; 59 uint32_t reserved_6a : 1, 60 mpdu_sequence_number : 12, 61 sw_exception_destination_ring : 5, 62 sw_exception_destination_ring_valid : 1, 63 sw_exception_mpdu_delink : 1, 64 sw_exception : 1, 65 mpdu_fragment_number : 4, 66 rxdma_error_code : 5, 67 rxdma_push_reason : 2; 68 uint32_t looping_count : 4, 69 ring_id : 8, 70 reserved_7a : 1, 71 src_link_id : 3, 72 phy_ppdu_id : 16; 73 #endif 74 }; 75 76 77 78 79 80 81 82 83 84 85 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 86 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 87 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 88 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 89 90 91 92 93 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 94 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 95 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 96 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 97 98 99 100 101 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 102 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 103 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 104 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 105 106 107 108 109 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 110 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 111 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 112 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 113 114 115 116 117 118 119 120 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 121 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 122 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 123 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 124 125 126 127 128 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 129 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 130 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 131 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 132 133 134 135 136 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 137 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 138 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 139 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 140 141 142 143 144 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 145 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 146 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 147 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 148 149 150 151 152 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 153 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 154 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 155 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 156 157 158 159 160 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 161 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 162 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 163 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 164 165 166 167 168 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 169 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 170 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 171 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 172 173 174 175 176 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 177 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 178 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 179 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 180 181 182 183 184 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 185 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 186 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 187 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 188 189 190 191 192 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 193 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 194 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 195 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 196 197 198 199 200 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 201 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 202 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 203 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 204 205 206 207 208 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 209 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 210 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 211 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 212 213 214 215 216 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 217 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 218 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 219 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 220 221 222 223 224 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 225 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 226 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 227 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 228 229 230 231 232 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 233 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 234 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 235 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 236 237 238 239 240 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 241 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 242 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 243 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 244 245 246 247 248 #define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 249 #define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 250 #define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 251 #define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 252 253 254 255 256 #define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 257 #define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 258 #define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 259 #define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 260 261 262 263 264 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 265 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 266 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 267 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 268 269 270 271 272 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 273 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 274 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 275 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c 276 277 278 279 280 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 281 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 282 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 283 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 284 285 286 287 288 #define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 289 #define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 290 #define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 291 #define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 292 293 294 295 296 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 297 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 298 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 299 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 300 301 302 303 304 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 305 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 306 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 307 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 308 309 310 311 312 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 313 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 314 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 315 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 316 317 318 319 320 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 321 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 322 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 323 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 324 325 326 327 328 #define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 329 #define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 330 #define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 331 #define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 332 333 334 335 336 #define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c 337 #define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 338 #define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 339 #define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff 340 341 342 343 344 #define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c 345 #define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 346 #define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 347 #define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 348 349 350 351 352 #define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c 353 #define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 354 #define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 355 #define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 356 357 358 359 360 #define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c 361 #define REO_ENTRANCE_RING_RING_ID_LSB 20 362 #define REO_ENTRANCE_RING_RING_ID_MSB 27 363 #define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 364 365 366 367 368 #define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c 369 #define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 370 #define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 371 #define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 372 373 374 375 #endif 376