1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _PDG_RESPONSE_H_ 20 #define _PDG_RESPONSE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "pdg_response_rate_setting.h" 25 #define NUM_OF_DWORDS_PDG_RESPONSE 12 26 27 #define NUM_OF_QWORDS_PDG_RESPONSE 6 28 29 30 struct pdg_response { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct pdg_response_rate_setting hw_response_rate_info; 33 uint32_t hw_response_tx_duration : 16, 34 rx_duration_field : 16; 35 uint32_t punctured_response_transmission : 1, 36 cca_subband_channel_bonding_mask : 16, 37 scrambler_seed_override : 2, 38 response_density_valid : 1, 39 response_density : 5, 40 more_data : 1, 41 duration_indication : 1, 42 relayed_frame : 1, 43 address_indicator : 1, 44 bandwidth : 3; 45 uint32_t ack_id : 16, 46 block_ack_bitmap : 16; 47 uint32_t response_frame_type : 4, 48 ack_id_ext : 10, 49 ftm_en : 1, 50 group_id : 6, 51 sta_partial_aid : 11; 52 uint32_t ndp_ba_start_seq_ctrl : 12, 53 active_channel : 3, 54 txop_duration_all_ones : 1, 55 frame_length : 16; 56 #else 57 struct pdg_response_rate_setting hw_response_rate_info; 58 uint32_t rx_duration_field : 16, 59 hw_response_tx_duration : 16; 60 uint32_t bandwidth : 3, 61 address_indicator : 1, 62 relayed_frame : 1, 63 duration_indication : 1, 64 more_data : 1, 65 response_density : 5, 66 response_density_valid : 1, 67 scrambler_seed_override : 2, 68 cca_subband_channel_bonding_mask : 16, 69 punctured_response_transmission : 1; 70 uint32_t block_ack_bitmap : 16, 71 ack_id : 16; 72 uint32_t sta_partial_aid : 11, 73 group_id : 6, 74 ftm_en : 1, 75 ack_id_ext : 10, 76 response_frame_type : 4; 77 uint32_t frame_length : 16, 78 txop_duration_all_ones : 1, 79 active_channel : 3, 80 ndp_ba_start_seq_ctrl : 12; 81 #endif 82 }; 83 84 85 86 87 88 89 90 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 91 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 92 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 93 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 94 95 96 97 98 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 99 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 100 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 101 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe 102 103 104 105 106 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 107 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 108 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 109 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 110 111 112 113 114 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 115 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 116 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 117 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 118 119 120 121 122 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 123 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 124 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 125 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 126 127 128 129 130 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 131 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 132 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 133 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 134 135 136 137 138 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 139 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 140 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 141 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 142 143 144 145 146 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 147 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 148 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 149 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 150 151 152 153 154 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 155 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 156 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 157 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 158 159 160 161 162 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 163 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 164 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 165 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 166 167 168 169 170 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 171 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 172 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 173 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 174 175 176 177 178 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 179 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 180 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 181 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 182 183 184 185 186 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 187 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 188 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 189 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 190 191 192 193 194 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 195 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 196 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 197 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f 198 199 200 201 202 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 203 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 204 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 205 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 206 207 208 209 210 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 211 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 212 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 213 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 214 215 216 217 218 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 219 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 220 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 221 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 222 223 224 225 226 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 227 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 228 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 229 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 230 231 232 233 234 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 235 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 236 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 237 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 238 239 240 241 242 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 243 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32 244 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 245 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000 246 247 248 249 250 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 251 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 252 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 253 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 254 255 256 257 258 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 259 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 260 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45 261 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000 262 263 264 265 266 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008 267 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46 268 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47 269 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000 270 271 272 273 274 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 275 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 276 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 277 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 278 279 280 281 282 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 283 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 284 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 285 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 286 287 288 289 290 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 291 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 292 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 293 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 294 295 296 297 298 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 299 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 300 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 301 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e 302 303 304 305 306 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 307 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 308 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 309 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 310 311 312 313 314 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 315 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 316 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 317 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 318 319 320 321 322 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 323 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 324 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 325 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 326 327 328 329 330 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 331 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 332 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 333 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 334 335 336 337 338 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 339 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 340 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 341 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 342 343 344 345 346 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 347 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 348 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 349 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 350 351 352 353 354 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 355 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 356 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 357 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 358 359 360 361 362 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 363 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 364 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 365 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 366 367 368 369 370 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 371 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 372 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 373 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 374 375 376 377 378 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 379 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 380 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 381 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 382 383 384 385 386 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 387 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 388 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 389 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 390 391 392 393 394 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 395 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 396 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 397 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 398 399 400 401 402 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 403 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 404 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 405 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 406 407 408 409 410 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 411 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 412 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 413 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 414 415 416 417 418 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 419 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 420 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 421 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 422 423 424 425 426 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 427 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 428 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 429 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 430 431 432 433 434 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 435 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 436 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 437 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 438 439 440 441 442 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 443 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 444 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 445 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 446 447 448 449 450 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 451 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 452 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 453 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 454 455 456 457 458 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 459 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 460 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 461 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 462 463 464 465 466 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 467 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 468 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 469 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 470 471 472 473 474 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 475 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 476 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 477 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 478 479 480 481 482 483 484 485 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 486 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 487 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 488 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff 489 490 491 492 493 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 494 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 495 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 496 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 497 498 499 500 501 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 502 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 503 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 504 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 505 506 507 508 509 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 510 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 511 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 512 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 513 514 515 516 517 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 518 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 519 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 520 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 521 522 523 524 525 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 526 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 527 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 528 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 529 530 531 532 533 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 534 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 535 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 536 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 537 538 539 540 541 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 542 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 543 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 544 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 545 546 547 548 549 #define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 550 #define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 551 #define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 552 #define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 553 554 555 556 557 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 558 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 559 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 560 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 561 562 563 564 565 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 566 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 567 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 568 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe 569 570 571 572 573 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 574 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 575 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 576 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 577 578 579 580 581 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 582 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 583 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 584 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 585 586 587 588 589 #define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 590 #define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 591 #define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 592 #define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 593 594 595 596 597 #define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 598 #define PDG_RESPONSE_MORE_DATA_LSB 25 599 #define PDG_RESPONSE_MORE_DATA_MSB 25 600 #define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 601 602 603 604 605 #define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 606 #define PDG_RESPONSE_DURATION_INDICATION_LSB 26 607 #define PDG_RESPONSE_DURATION_INDICATION_MSB 26 608 #define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 609 610 611 612 613 #define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020 614 #define PDG_RESPONSE_RELAYED_FRAME_LSB 27 615 #define PDG_RESPONSE_RELAYED_FRAME_MSB 27 616 #define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000 617 618 619 620 621 #define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020 622 #define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 623 #define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 624 #define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000 625 626 627 628 629 #define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 630 #define PDG_RESPONSE_BANDWIDTH_LSB 29 631 #define PDG_RESPONSE_BANDWIDTH_MSB 31 632 #define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 633 634 635 636 637 #define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 638 #define PDG_RESPONSE_ACK_ID_LSB 32 639 #define PDG_RESPONSE_ACK_ID_MSB 47 640 #define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 641 642 643 644 645 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 646 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 647 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 648 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 649 650 651 652 653 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 654 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 655 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 656 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f 657 658 659 660 661 #define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 662 #define PDG_RESPONSE_ACK_ID_EXT_LSB 4 663 #define PDG_RESPONSE_ACK_ID_EXT_MSB 13 664 #define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 665 666 667 668 669 #define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 670 #define PDG_RESPONSE_FTM_EN_LSB 14 671 #define PDG_RESPONSE_FTM_EN_MSB 14 672 #define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 673 674 675 676 677 #define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 678 #define PDG_RESPONSE_GROUP_ID_LSB 15 679 #define PDG_RESPONSE_GROUP_ID_MSB 20 680 #define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 681 682 683 684 685 #define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 686 #define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 687 #define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 688 #define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 689 690 691 692 693 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 694 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 695 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 696 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 697 698 699 700 701 #define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 702 #define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 703 #define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 704 #define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 705 706 707 708 709 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 710 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 711 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 712 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 713 714 715 716 717 #define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 718 #define PDG_RESPONSE_FRAME_LENGTH_LSB 48 719 #define PDG_RESPONSE_FRAME_LENGTH_MSB 63 720 #define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 721 722 723 724 #endif 725