1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _MON_BUFFER_ADDR_H_ 20 #define _MON_BUFFER_ADDR_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 25 26 #define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 27 28 29 struct mon_buffer_addr { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t buffer_virt_addr_31_0 : 32; 32 uint32_t buffer_virt_addr_63_32 : 32; 33 uint32_t dma_length : 12, 34 reserved_2a : 4, 35 msdu_continuation : 1, 36 truncated : 1, 37 reserved_2b : 14; 38 uint32_t tlv64_padding : 32; 39 #else 40 uint32_t buffer_virt_addr_31_0 : 32; 41 uint32_t buffer_virt_addr_63_32 : 32; 42 uint32_t reserved_2b : 14, 43 truncated : 1, 44 msdu_continuation : 1, 45 reserved_2a : 4, 46 dma_length : 12; 47 uint32_t tlv64_padding : 32; 48 #endif 49 }; 50 51 52 53 54 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 55 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 56 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 57 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff 58 59 60 61 62 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 63 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 64 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 65 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 66 67 68 69 70 #define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 71 #define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 72 #define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 73 #define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff 74 75 76 77 78 #define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 79 #define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 80 #define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 81 #define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 82 83 84 85 86 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 87 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 88 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 89 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 90 91 92 93 94 #define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 95 #define MON_BUFFER_ADDR_TRUNCATED_LSB 17 96 #define MON_BUFFER_ADDR_TRUNCATED_MSB 17 97 #define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 98 99 100 101 102 #define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 103 #define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 104 #define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 105 #define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 106 107 108 109 110 #define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 111 #define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 112 #define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 113 #define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 114 115 116 117 #endif 118