1 
2 /*
3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4  * SPDX-License-Identifier: ISC
5  */
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17 
18 
19 #ifndef _HE_SIG_B2_MU_INFO_H_
20 #define _HE_SIG_B2_MU_INFO_H_
21 #if !defined(__ASSEMBLER__)
22 #endif
23 
24 #define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
25 
26 
27 struct he_sig_b2_mu_info {
28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
29              uint32_t sta_id                                                  : 11,
30                       sta_spatial_config                                      :  4,
31                       sta_mcs                                                 :  4,
32                       reserved_set_to_1                                       :  1,
33                       sta_coding                                              :  1,
34                       reserved_0a                                             :  7,
35                       nsts                                                    :  3,
36                       rx_integrity_check_passed                               :  1;
37              uint32_t user_order                                              :  8,
38                       cc_mask                                                 :  8,
39                       reserved_1a                                             : 16;
40 #else
41              uint32_t rx_integrity_check_passed                               :  1,
42                       nsts                                                    :  3,
43                       reserved_0a                                             :  7,
44                       sta_coding                                              :  1,
45                       reserved_set_to_1                                       :  1,
46                       sta_mcs                                                 :  4,
47                       sta_spatial_config                                      :  4,
48                       sta_id                                                  : 11;
49              uint32_t reserved_1a                                             : 16,
50                       cc_mask                                                 :  8,
51                       user_order                                              :  8;
52 #endif
53 };
54 
55 
56 
57 
58 #define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
59 #define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
60 #define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
61 #define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
62 
63 
64 
65 
66 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
67 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
68 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
69 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
70 
71 
72 
73 
74 #define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
75 #define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
76 #define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
77 #define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
78 
79 
80 
81 
82 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
83 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
84 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
85 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
86 
87 
88 
89 
90 #define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
91 #define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
92 #define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
93 #define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
94 
95 
96 
97 
98 #define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
99 #define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
100 #define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
101 #define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
102 
103 
104 
105 
106 #define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
107 #define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
108 #define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
109 #define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
110 
111 
112 
113 
114 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
115 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
116 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
117 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
118 
119 
120 
121 
122 #define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
123 #define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
124 #define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
125 #define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
126 
127 
128 
129 
130 #define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
131 #define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
132 #define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
133 #define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
134 
135 
136 
137 
138 #define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
139 #define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
140 #define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
141 #define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
142 
143 
144 
145 #endif
146