1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _HE_SIG_A_MU_DL_INFO_H_ 20 #define _HE_SIG_A_MU_DL_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 25 26 27 struct he_sig_a_mu_dl_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t dl_ul_flag : 1, 30 mcs_of_sig_b : 3, 31 dcm_of_sig_b : 1, 32 bss_color_id : 6, 33 spatial_reuse : 4, 34 transmit_bw : 3, 35 num_sig_b_symbols : 4, 36 comp_mode_sig_b : 1, 37 cp_ltf_size : 2, 38 doppler_indication : 1, 39 reserved_0a : 6; 40 uint32_t txop_duration : 7, 41 reserved_1a : 1, 42 num_ltf_symbols : 3, 43 ldpc_extra_symbol : 1, 44 stbc : 1, 45 packet_extension_a_factor : 2, 46 packet_extension_pe_disambiguity : 1, 47 crc : 4, 48 tail : 6, 49 reserved_1b : 5, 50 rx_integrity_check_passed : 1; 51 #else 52 uint32_t reserved_0a : 6, 53 doppler_indication : 1, 54 cp_ltf_size : 2, 55 comp_mode_sig_b : 1, 56 num_sig_b_symbols : 4, 57 transmit_bw : 3, 58 spatial_reuse : 4, 59 bss_color_id : 6, 60 dcm_of_sig_b : 1, 61 mcs_of_sig_b : 3, 62 dl_ul_flag : 1; 63 uint32_t rx_integrity_check_passed : 1, 64 reserved_1b : 5, 65 tail : 6, 66 crc : 4, 67 packet_extension_pe_disambiguity : 1, 68 packet_extension_a_factor : 2, 69 stbc : 1, 70 ldpc_extra_symbol : 1, 71 num_ltf_symbols : 3, 72 reserved_1a : 1, 73 txop_duration : 7; 74 #endif 75 }; 76 77 78 79 80 #define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 81 #define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 82 #define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 83 #define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 84 85 86 87 88 #define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 89 #define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 90 #define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 91 #define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e 92 93 94 95 96 #define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 97 #define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 98 #define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 99 #define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 100 101 102 103 104 #define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 105 #define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 106 #define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 107 #define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 108 109 110 111 112 #define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 113 #define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 114 #define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 115 #define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 116 117 118 119 120 #define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 121 #define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 122 #define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 123 #define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 124 125 126 127 128 #define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 129 #define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 130 #define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 131 #define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 132 133 134 135 136 #define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 137 #define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 138 #define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 139 #define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 140 141 142 143 144 #define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 145 #define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 146 #define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 147 #define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 148 149 150 151 152 #define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 153 #define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 154 #define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 155 #define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 156 157 158 159 160 #define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 161 #define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 162 #define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 163 #define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 164 165 166 167 168 #define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 169 #define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 170 #define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 171 #define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f 172 173 174 175 176 #define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 177 #define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 178 #define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 179 #define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 180 181 182 183 184 #define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 185 #define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 186 #define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 187 #define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 188 189 190 191 192 #define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 193 #define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 194 #define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 195 #define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 196 197 198 199 200 #define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 201 #define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 202 #define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 203 #define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 204 205 206 207 208 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 209 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 210 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 211 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 212 213 214 215 216 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 217 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 218 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 219 #define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 220 221 222 223 224 #define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 225 #define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 226 #define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 227 #define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 228 229 230 231 232 #define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 233 #define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 234 #define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 235 #define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 236 237 238 239 240 #define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 241 #define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 242 #define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 243 #define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 244 245 246 247 248 #define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 249 #define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 250 #define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 251 #define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 252 253 254 255 #endif 256