1  
2  /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for any
5   * purpose with or without fee is hereby granted, provided that the above
6   * copyright notice and this permission notice appear in all copies.
7   *
8   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9   * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10   * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11   * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12   * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13   * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15   */
16  
17  
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24  
25  
26  #ifndef _WBM_RELEASE_RING_RX_H_
27  #define _WBM_RELEASE_RING_RX_H_
28  #if !defined(__ASSEMBLER__)
29  #endif
30  
31  #include "rx_msdu_desc_info.h"
32  #include "rx_mpdu_desc_info.h"
33  #include "buffer_addr_info.h"
34  #define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8
35  
36  
37  struct wbm_release_ring_rx {
38  #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39               struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
40               uint32_t release_source_module                                   :  3, // [2:0]
41                        bm_action                                               :  3, // [5:3]
42                        buffer_or_desc_type                                     :  3, // [8:6]
43                        first_msdu_index                                        :  4, // [12:9]
44                        reserved_2a                                             :  2, // [14:13]
45                        cache_id                                                :  1, // [15:15]
46                        cookie_conversion_status                                :  1, // [16:16]
47                        rxdma_push_reason                                       :  2, // [18:17]
48                        rxdma_error_code                                        :  5, // [23:19]
49                        reo_push_reason                                         :  2, // [25:24]
50                        reo_error_code                                          :  5, // [30:26]
51                        wbm_internal_error                                      :  1; // [31:31]
52               struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
53               struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
54               uint32_t reserved_6a                                             : 32; // [31:0]
55               uint32_t reserved_7a                                             : 20, // [19:0]
56                        ring_id                                                 :  8, // [27:20]
57                        looping_count                                           :  4; // [31:28]
58  #else
59               struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
60               uint32_t wbm_internal_error                                      :  1, // [31:31]
61                        reo_error_code                                          :  5, // [30:26]
62                        reo_push_reason                                         :  2, // [25:24]
63                        rxdma_error_code                                        :  5, // [23:19]
64                        rxdma_push_reason                                       :  2, // [18:17]
65                        cookie_conversion_status                                :  1, // [16:16]
66                        cache_id                                                :  1, // [15:15]
67                        reserved_2a                                             :  2, // [14:13]
68                        first_msdu_index                                        :  4, // [12:9]
69                        buffer_or_desc_type                                     :  3, // [8:6]
70                        bm_action                                               :  3, // [5:3]
71                        release_source_module                                   :  3; // [2:0]
72               struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
73               struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
74               uint32_t reserved_6a                                             : 32; // [31:0]
75               uint32_t looping_count                                           :  4, // [31:28]
76                        ring_id                                                 :  8, // [27:20]
77                        reserved_7a                                             : 20; // [19:0]
78  #endif
79  };
80  
81  
82  /* Description		RELEASED_BUFF_OR_DESC_ADDR_INFO
83  
84  			Consumer: WBM/SW/FW
85  			Producer: SW/TQM/RXDMA/REO/SWITCH
86  
87  			Details of the physical address of the buffer or link descriptor
88  			 that is being released. Note that within this descriptor,
89  			WBM will look at the 'owner' of the released buffer/descriptor
90  			 and forward it to SW/FW is WBM is not the owner.
91  */
92  
93  
94  /* Description		BUFFER_ADDR_31_0
95  
96  			Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
97  			 descriptor OR Link Descriptor
98  
99  			In case of 'NULL' pointer, this field is set to 0
100  			<legal all>
101  */
102  
103  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
104  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
105  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
106  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
107  
108  
109  /* Description		BUFFER_ADDR_39_32
110  
111  			Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
112  			 descriptor OR Link Descriptor
113  
114  			In case of 'NULL' pointer, this field is set to 0
115  			<legal all>
116  */
117  
118  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
119  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
120  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
121  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
122  
123  
124  /* Description		RETURN_BUFFER_MANAGER
125  
126  			Consumer: WBM
127  			Producer: SW/FW
128  
129  			In case of 'NULL' pointer, this field is set to 0
130  
131  			Indicates to which buffer manager the buffer OR MSDU_EXTENSION
132  			 descriptor OR link descriptor that is being pointed to
133  			shall be returned after the frame has been processed. It
134  			 is used by WBM for routing purposes.
135  
136  			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
137  			 to the WMB buffer idle list
138  			<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
139  			 to the WBM idle link descriptor idle list, where the chip
140  			 0 WBM is chosen in case of a multi-chip config
141  			<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
142  			 to the chip 1 WBM idle link descriptor idle list
143  			<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
144  			 to the chip 2 WBM idle link descriptor idle list
145  			<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
146  			returned to chip 3 WBM idle link descriptor idle list
147  			<enum 4 FW_BM> This buffer shall be returned to the FW
148  			<enum 5 SW0_BM> This buffer shall be returned to the SW,
149  			ring 0
150  			<enum 6 SW1_BM> This buffer shall be returned to the SW,
151  			ring 1
152  			<enum 7 SW2_BM> This buffer shall be returned to the SW,
153  			ring 2
154  			<enum 8 SW3_BM> This buffer shall be returned to the SW,
155  			ring 3
156  			<enum 9 SW4_BM> This buffer shall be returned to the SW,
157  			ring 4
158  			<enum 10 SW5_BM> This buffer shall be returned to the SW,
159  			ring 5
160  			<enum 11 SW6_BM> This buffer shall be returned to the SW,
161  			ring 6
162  
163  			<legal 0-12>
164  */
165  
166  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
167  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
168  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
169  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
170  
171  
172  /* Description		SW_BUFFER_COOKIE
173  
174  			Cookie field exclusively used by SW.
175  
176  			In case of 'NULL' pointer, this field is set to 0
177  
178  			HW ignores the contents, accept that it passes the programmed
179  			 value on to other descriptors together with the physical
180  			 address
181  
182  			Field can be used by SW to for example associate the buffers
183  			 physical address with the virtual address
184  			The bit definitions as used by SW are within SW HLD specification
185  
186  
187  			NOTE1:
188  			The three most significant bits can have a special meaning
189  			 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
190  			and field transmit_bw_restriction is set
191  
192  			In case of NON punctured transmission:
193  			Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
194  			Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
195  			Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
196  			Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
197  			Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
198  			Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
199  			Sw_buffer_cookie[19:18] = 2'b11: reserved
200  
201  			In case of punctured transmission:
202  			Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
203  			Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
204  			Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
205  			Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
206  			Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
207  			Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
208  			Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
209  			Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
210  			Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
211  			Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
212  			Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
213  			Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
214  			Sw_buffer_cookie[19:18] = 2'b11: reserved
215  
216  			Note: a punctured transmission is indicated by the presence
217  			 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
218  
219  			<legal all>
220  */
221  
222  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
223  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
224  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
225  #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
226  
227  
228  /* Description		RELEASE_SOURCE_MODULE
229  
230  			Indicates which module initiated the release of this buffer
231  			 or descriptor
232  
233  			<enum 1 release_source_RXDMA> RXDMA released this buffer
234  			 or descriptor
235  			<enum 2 release_source_REO> REO released this buffer or
236  			descriptor
237  			<enum 5 release_source_FW_RX> FW released this buffer or
238  			 descriptor
239  			<enum 4 release_source_SW_RX> SW released this buffer or
240  			 descriptor
241  			<enum 0 release_source_TQM> DO NOT USE
242  			<enum 3 release_source_FW_TX> DO NOT USE
243  			<enum 6 release_source_SW_TX> DO NOT USE
244  			<legal 0-6>
245  */
246  
247  #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
248  #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB                               0
249  #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB                               2
250  #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
251  
252  
253  /* Description		BM_ACTION
254  
255  			Consumer: WBM/SW/FW
256  			Producer: SW/TQM/RXDMA/REO/SWITCH
257  
258  			Field only valid when the field return_buffer_manager in
259  			 the Released_buff_or_desc_addr_info indicates:
260  			WBM_IDLE_BUF_LIST or
261  			WBM_IDLE_DESC_LIST
262  
263  			An MSDU extension descriptor shall never be marked as WBM
264  			 being the 'owner', and thus WBM will forward it to FW/SW
265  
266  
267  			<enum 0 Put_in_idle_list> Put the buffer or descriptor back
268  			 in the idle list. In case of MSDU or MDPU link descriptor,
269  			BM does not need to check to release any individual MSDU
270  			 buffers
271  
272  			<enum 1 release_msdu_list > This BM action can only be used
273  			 in combination with buffer_or_desc_type being msdu_link_descriptor.
274  			Field first_msdu_index points out which MSDU pointer in
275  			the MSDU link descriptor is the first of an MPDU that is
276  			 released.
277  			BM shall release all the MSDU buffers linked to this first
278  			 MSDU buffer pointer. All related MSDU buffer pointer entries
279  			 shall be set to value 0, which represents the 'NULL" pointer.
280  			When all MSDU buffer pointers in the MSDU link descriptor
281  			 are 'NULL', the MSDU link descriptor itself shall also
282  			be released.
283  
284  			<enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED....
285  
286  			Put the buffer or descriptor back in the idle list. Only
287  			 valid in combination with buffer_or_desc_type indicating
288  			 MDPU_link_descriptor.
289  			BM shall release the MPDU link descriptor as well as all
290  			 MSDUs that are linked to the MPDUs in this descriptor.
291  
292  
293  			TODO: Any restrictions?
294  			<legal 0-2>
295  */
296  
297  #define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET                                        0x00000008
298  #define WBM_RELEASE_RING_RX_BM_ACTION_LSB                                           3
299  #define WBM_RELEASE_RING_RX_BM_ACTION_MSB                                           5
300  #define WBM_RELEASE_RING_RX_BM_ACTION_MASK                                          0x00000038
301  
302  
303  /* Description		BUFFER_OR_DESC_TYPE
304  
305  			Consumer: WBM/SW/FW
306  			Producer: SW/TQM/RXDMA/REO/SWITCH
307  
308  			Field only valid when WBM is marked as the return_buffer_manager
309  			 in the Released_Buffer_address_info
310  
311  			Indicates that type of buffer or descriptor is being released
312  
313  
314  			<enum 0 MSDU_rel_buffer> The address points to an MSDU buffer
315  
316  			<enum 1 msdu_link_descriptor> The address points to an TX
317  			 MSDU link descriptor
318  			<enum 2 mpdu_link_descriptor> The address points to an MPDU
319  			 link descriptor
320  			<enum 3 msdu_ext_descriptor > The address points to an MSDU
321  			 extension descriptor.
322  			In case BM finds this one in a release ring, it passes it
323  			 on to FW...
324  			<enum 4 queue_ext_descriptor> The address points to an TQM
325  			 queue extension descriptor. WBM should treat this is the
326  			 same way as a link descriptor. That is, put the 128 byte
327  			 buffer back in the link buffer idle list.
328  
329  			TODO: Any restrictions?
330  			<legal 0-4>
331  */
332  
333  #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
334  #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB                                 6
335  #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB                                 8
336  #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK                                0x000001c0
337  
338  
339  /* Description		FIRST_MSDU_INDEX
340  
341  			Consumer: WBM/SW/FW
342  			Producer: SW/TQM/RXDMA/REO/SWITCH
343  
344  			Field only valid for the bm_action release_msdu_list.
345  
346  			The index of the first MSDU in an MSDU link descriptor all
347  			 belonging to the same MPDU.
348  
349  			TODO: Any restrictions?
350  			<legal 0-6>
351  */
352  
353  #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET                                 0x00000008
354  #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB                                    9
355  #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB                                    12
356  #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK                                   0x00001e00
357  
358  
359  /* Description		RESERVED_2A
360  
361  			<legal 0>
362  */
363  
364  #define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET                                      0x00000008
365  #define WBM_RELEASE_RING_RX_RESERVED_2A_LSB                                         13
366  #define WBM_RELEASE_RING_RX_RESERVED_2A_MSB                                         14
367  #define WBM_RELEASE_RING_RX_RESERVED_2A_MASK                                        0x00006000
368  
369  
370  /* Description		CACHE_ID
371  
372  			Indicates the WBM cache the MSDU was released from
373  			<legal all>
374  */
375  
376  #define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET                                         0x00000008
377  #define WBM_RELEASE_RING_RX_CACHE_ID_LSB                                            15
378  #define WBM_RELEASE_RING_RX_CACHE_ID_MSB                                            15
379  #define WBM_RELEASE_RING_RX_CACHE_ID_MASK                                           0x00008000
380  
381  
382  /* Description		COOKIE_CONVERSION_STATUS
383  
384  			0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr'
385  
386  			1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr'
387  			<legal 0>
388  */
389  
390  #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                         0x00000008
391  #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB                            16
392  #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB                            16
393  #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK                           0x00010000
394  
395  
396  /* Description		RXDMA_PUSH_REASON
397  
398  			Field only valid when Release_source_module is set to release_source_RXDMA
399  
400  
401  			Indicates why rxdma pushed the frame to this ring
402  
403  			<enum 0 rxdma_error_detected> RXDMA detected an error an
404  			 pushed this frame to this queue
405  			<enum 1 rxdma_routing_instruction> RXDMA pushed the frame
406  			 to this queue per received routing instructions. No error
407  			 within RXDMA was detected
408  			<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
409  			 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag"
410  			set, but instead WBM might just see a NULL pointer in the
411  			 MSDU link descriptor. This is to be considered a normal
412  			 condition for this scenario.
413  
414  			<legal 0 - 2>
415  */
416  
417  #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET                                0x00000008
418  #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB                                   17
419  #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB                                   18
420  #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK                                  0x00060000
421  
422  
423  /* Description		RXDMA_ERROR_CODE
424  
425  			Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'.
426  
427  
428  			<enum 0 rxdma_overflow_err>MPDU frame is not complete due
429  			 to a FIFO overflow error in RXPCU.
430  			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
431  			 due to receiving incomplete MPDU from the PHY
432  			<enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed
433  
434  			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error
435  			 or CRYPTO received an encrypted frame, but did not get
436  			a valid corresponding key id in the peer entry.
437  			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error
438  
439  			<enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted
440  			 frame error when encrypted was expected
441  			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length
442  			 error
443  			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max number
444  			 of MSDUs allowed in an MPDU got exceeded
445  			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error
446  
447  			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
448  			parsing error
449  			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
450  			during SA search
451  			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
452  			during DA search
453  			<enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout
454  			 during flow search
455  			<enum 13 rxdma_flush_request>RXDMA received a flush request
456  
457  			<enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
458  			 present as well as a fragmented MPDU. A-MSDU defragmentation
459  			 is not supported in Lithium SW so this is treated as an
460  			 error.
461  			<enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast
462  			 echo
463  			<enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an
464  			 A-MSDU with either 'from DS = 0' with an SA mismatching
465  			 TA or 'to DS = 0' with a DA mismatching RA.
466  			<enum 17 rxdma_unauthorized_wds_err>RX PCU reported that
467  			 Rx peer entry did not indicate 'authorized_to_send_WDS'
468  			and also indicated 'from DS = to DS = 1.'
469  			<enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported
470  			 a broadcast or multicast RA as well as either A-MSDU present
471  			 or 'from DS = to DS = 1.'
472  */
473  
474  #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET                                 0x00000008
475  #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB                                    19
476  #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB                                    23
477  #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK                                   0x00f80000
478  
479  
480  /* Description		REO_PUSH_REASON
481  
482  			Field only valid when Release_source_module is set to release_source_REO
483  
484  
485  			Indicates why REO pushed the frame to this release ring
486  
487  			<enum 0 reo_error_detected> Reo detected an error an pushed
488  			 this frame to this queue
489  			<enum 1 reo_routing_instruction> Reo pushed the frame to
490  			 this queue per received routing instructions. No error
491  			within REO was detected
492  
493  			<legal 0 - 1>
494  */
495  
496  #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET                                  0x00000008
497  #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB                                     24
498  #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB                                     25
499  #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK                                    0x03000000
500  
501  
502  /* Description		REO_ERROR_CODE
503  
504  			Field only valid when 'Reo_push_reason' set to 'reo_error_detected'.
505  
506  
507  			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided
508  			 in the REO_ENTRANCE ring is set to 0
509  			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid
510  			 bit is NOT set
511  			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
512  			 session having been setup.
513  			<enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN,
514  			Retry bit set: duplicate frame
515  			<enum 4 ba_duplicate> BA session, duplicate frame
516  			<enum 5 regular_frame_2k_jump> A normal (management/data
517  			 frame) received with 2K jump in SN
518  			<enum 6 bar_frame_2k_jump> A bar received with 2K jump in
519  			 SSN
520  			<enum 7 regular_frame_OOR> A normal (management/data frame)
521  			received with SN falling within the OOR window
522  			<enum 8 bar_frame_OOR> A bar received with SSN falling within
523  			 the OOR window
524  			<enum 9 bar_frame_no_ba_session> A bar received without
525  			a BA session
526  			<enum 10 bar_frame_sn_equals_ssn> A bar received with SSN
527  			 equal to SN
528  			<enum 11 pn_check_failed> PN Check Failed packet.
529  			<enum 12 2k_error_handling_flag_set> Frame is forwarded
530  			as a result of the 'Seq_2k_error_detected_flag' been set
531  			 in the REO Queue descriptor
532  			<enum 13 pn_error_handling_flag_set> Frame is forwarded
533  			as a result of the 'pn_error_detected_flag' been set in
534  			the REO Queue descriptor
535  			<enum 14 queue_descriptor_blocked_set> Frame is forwarded
536  			 as a result of the queue descriptor(address) being blocked
537  			 as SW/FW seems to be currently in the process of making
538  			 updates to this descriptor...
539  
540  			<legal 0-14>
541  */
542  
543  #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET                                   0x00000008
544  #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB                                      26
545  #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB                                      30
546  #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK                                     0x7c000000
547  
548  
549  /* Description		WBM_INTERNAL_ERROR
550  
551  			Can only be set by WBM.
552  
553  			Is set when WBM got a buffer pointer but the action was
554  			to push it to the idle link descriptor ring or do link related
555  			 activity
556  			OR
557  			Is set when WBM got a link buffer pointer but the action
558  			 was to push it to the buffer  descriptor ring
559  
560  			<legal all>
561  */
562  
563  #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET                               0x00000008
564  #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB                                  31
565  #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB                                  31
566  #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK                                 0x80000000
567  
568  
569  /* Description		RX_MPDU_DESC_INFO_DETAILS
570  
571  			Consumer: REO/SW/FW
572  			Producer: RXDMA
573  
574  			General information related to the MPDU whose link descriptors
575  			 are being released from Rx DMA or REO
576  
577  			When enabled in REO, REO will overwrite this structure to
578  			 have only the 'Msdu_count' field and 56 bits of the previous
579  			 PN from 'RX_REO_QUEUE' (Hamilton FR62456)
580  */
581  
582  
583  /* Description		MSDU_COUNT
584  
585  			Consumer: REO/SW/FW
586  			Producer: RXDMA
587  
588  			The number of MSDUs within the MPDU
589  			<legal all>
590  */
591  
592  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET             0x0000000c
593  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                0
594  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                7
595  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK               0x000000ff
596  
597  
598  /* Description		FRAGMENT_FLAG
599  
600  			Consumer: REO/SW/FW
601  			Producer: RXDMA
602  
603  			When set, this MPDU is a fragment and REO should forward
604  			 this fragment MPDU to the REO destination ring without
605  			any reorder checks, pn checks or bitmap update. This implies
606  			 that REO is forwarding the pointer to the MSDU link descriptor.
607  			The destination ring is coming from a programmable register
608  			 setting in REO
609  
610  			<legal all>
611  */
612  
613  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET          0x0000000c
614  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB             8
615  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB             8
616  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK            0x00000100
617  
618  
619  /* Description		MPDU_RETRY_BIT
620  
621  			Consumer: REO/SW/FW
622  			Producer: RXDMA
623  
624  			The retry bit setting from the MPDU header of the received
625  			 frame
626  			<legal all>
627  */
628  
629  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET         0x0000000c
630  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB            9
631  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB            9
632  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK           0x00000200
633  
634  
635  /* Description		AMPDU_FLAG
636  
637  			Consumer: REO/SW/FW
638  			Producer: RXDMA
639  
640  			When set, the MPDU was received as part of an A-MPDU.
641  			<legal all>
642  */
643  
644  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET             0x0000000c
645  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                10
646  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                10
647  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK               0x00000400
648  
649  
650  /* Description		BAR_FRAME
651  
652  			Consumer: REO/SW/FW
653  			Producer: RXDMA
654  
655  			When set, the received frame is a BAR frame. After processing,
656  			this frame shall be pushed to SW or deleted.
657  			<legal all>
658  */
659  
660  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET              0x0000000c
661  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                 11
662  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                 11
663  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                0x00000800
664  
665  
666  /* Description		PN_FIELDS_CONTAIN_VALID_INFO
667  
668  			Consumer: REO/SW/FW
669  			Producer: RXDMA
670  
671  			Copied here by RXDMA from RX_MPDU_END
672  			When not set, REO will Not perform a PN sequence number
673  			check
674  */
675  
676  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
677  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
678  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
679  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
680  
681  
682  /* Description		RAW_MPDU
683  
684  			Field only valid when first_msdu_in_mpdu_flag is set.
685  
686  			When set, the contents in the MSDU buffer contains a 'RAW'
687  			MPDU. This 'RAW' MPDU might be spread out over multiple
688  			MSDU buffers.
689  			<legal all>
690  */
691  
692  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET               0x0000000c
693  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                  13
694  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                  13
695  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                 0x00002000
696  
697  
698  /* Description		MORE_FRAGMENT_FLAG
699  
700  			The More Fragment bit setting from the MPDU header of the
701  			 received frame
702  
703  			<legal all>
704  */
705  
706  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET     0x0000000c
707  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB        14
708  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB        14
709  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK       0x00004000
710  
711  
712  /* Description		SRC_INFO
713  
714  			Source (virtual) device/interface info. associated with
715  			this peer
716  
717  			This field gets passed on by REO to PPE in the EDMA descriptor
718  			 ('REO_TO_PPE_RING').
719  
720  			Hamilton v1 used this for 'vdev_id' instead.
721  			<legal all>
722  */
723  
724  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET               0x0000000c
725  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                  15
726  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                  26
727  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                 0x07ff8000
728  
729  
730  /* Description		MPDU_QOS_CONTROL_VALID
731  
732  			When set, the MPDU has a QoS control field.
733  
734  			In case of ndp or phy_err, this field will never be set.
735  
736  			<legal all>
737  */
738  
739  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
740  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB    27
741  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB    27
742  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK   0x08000000
743  
744  
745  /* Description		TID
746  
747  			Field only valid when mpdu_qos_control_valid is set
748  
749  			The TID field in the QoS control field
750  			<legal all>
751  */
752  
753  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                    0x0000000c
754  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                       28
755  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                       31
756  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                      0xf0000000
757  
758  
759  /* Description		PEER_META_DATA
760  
761  			Meta data that SW has programmed in the Peer table entry
762  			 of the transmitting STA.
763  			<legal all>
764  */
765  
766  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET         0x00000010
767  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB            0
768  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB            31
769  #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK           0xffffffff
770  
771  
772  /* Description		RX_MSDU_DESC_INFO_DETAILS
773  
774  			Consumer: TQM/SW
775  			Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA)
776  
777  			In case of RXDMA or REO releasing Rx MSDU link descriptors,'
778  			WBM fills this field with Rx_msdu_desc_info_details when
779  			 releasing the MSDUs to SW (Maple/Spruce FR59859).
780  */
781  
782  
783  /* Description		FIRST_MSDU_IN_MPDU_FLAG
784  
785  			Parsed from RX_MSDU_END TLV . In the case MSDU spans over
786  			 multiple buffers, this field will be valid in the Last
787  			buffer used by the MSDU
788  
789  			<enum 0 Not_first_msdu> This is not the first MSDU in the
790  			 MPDU.
791  			<enum 1 first_msdu> This MSDU is the first one in the MPDU.
792  
793  
794  			<legal all>
795  */
796  
797  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
798  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
799  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
800  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
801  
802  
803  /* Description		LAST_MSDU_IN_MPDU_FLAG
804  
805  			Consumer: WBM/REO/SW/FW
806  			Producer: RXDMA
807  
808  			Parsed from RX_MSDU_END TLV . In the case MSDU spans over
809  			 multiple buffers, this field will be valid in the Last
810  			buffer used by the MSDU
811  
812  			<enum 0 Not_last_msdu> There are more MSDUs linked to this
813  			 MSDU that belongs to this MPDU
814  			<enum 1 Last_msdu> this MSDU is the last one in the MPDU.
815  			This setting is only allowed in combination with 'Msdu_continuation'
816  			set to 0. This implies that when an msdu is spread out over
817  			 multiple buffers and thus msdu_continuation is set, only
818  			 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag'
819  			be set.
820  
821  			When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag
822  			 are set, the MPDU that this MSDU belongs to only contains
823  			 a single MSDU.
824  
825  
826  			<legal all>
827  */
828  
829  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
830  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
831  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
832  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
833  
834  
835  /* Description		MSDU_CONTINUATION
836  
837  			When set, this MSDU buffer was not able to hold the entire
838  			 MSDU. The next buffer will therefor contain additional
839  			information related to this MSDU.
840  
841  			<legal all>
842  */
843  
844  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000014
845  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
846  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
847  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
848  
849  
850  /* Description		MSDU_LENGTH
851  
852  			Parsed from RX_MSDU_START TLV . In the case MSDU spans over
853  			 multiple buffers, this field will be valid in the First
854  			 buffer used by MSDU.
855  
856  			Full MSDU length in bytes after decapsulation.
857  
858  			This field is still valid for MPDU frames without A-MSDU.
859  			 It still represents MSDU length after decapsulation
860  
861  			Or in case of RAW MPDUs, it indicates the length of the
862  			entire MPDU (without FCS field)
863  			<legal all>
864  */
865  
866  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000014
867  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
868  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
869  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
870  
871  
872  /* Description		MSDU_DROP
873  
874  			Parsed from RX_MSDU_END TLV . In the case MSDU spans over
875  			 multiple buffers, this field will be valid in the Last
876  			buffer used by the MSDU
877  
878  			When set, REO shall drop this MSDU and not forward it to
879  			 any other ring...
880  			<legal all>
881  */
882  
883  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000014
884  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
885  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
886  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
887  
888  
889  /* Description		SA_IS_VALID
890  
891  			Parsed from RX_MSDU_END TLV . In the case MSDU spans over
892  			 multiple buffers, this field will be valid in the Last
893  			buffer used by the MSDU
894  
895  			Indicates that OLE found a valid SA entry for this MSDU
896  			<legal all>
897  */
898  
899  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000014
900  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
901  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
902  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
903  
904  
905  /* Description		DA_IS_VALID
906  
907  			Parsed from RX_MSDU_END TLV . In the case MSDU spans over
908  			 multiple buffers, this field will be valid in the Last
909  			buffer used by the MSDU
910  
911  			Indicates that OLE found a valid DA entry for this MSDU
912  			<legal all>
913  */
914  
915  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000014
916  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
917  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
918  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
919  
920  
921  /* Description		DA_IS_MCBC
922  
923  			Field Only valid if "da_is_valid" is set
924  
925  			Indicates the DA address was a Multicast of Broadcast address
926  			 for this MSDU
927  			<legal all>
928  */
929  
930  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000014
931  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
932  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
933  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
934  
935  
936  /* Description		L3_HEADER_PADDING_MSB
937  
938  			Passed on from 'RX_MSDU_END' TLV (only the MSB is reported
939  			 as the LSB is always zero)
940  			Number of bytes padded to make sure that the L3 header will
941  			 always start of a Dword boundary
942  			<legal all>
943  */
944  
945  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000014
946  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
947  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
948  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
949  
950  
951  /* Description		TCP_UDP_CHKSUM_FAIL
952  
953  			Passed on from 'RX_ATTENTION' TLV
954  			Indicates that the computed checksum did not match the checksum
955  			 in the TCP/UDP header.
956  			<legal all>
957  */
958  
959  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000014
960  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
961  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
962  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
963  
964  
965  /* Description		IP_CHKSUM_FAIL
966  
967  			Passed on from 'RX_ATTENTION' TLV
968  			Indicates that the computed checksum did not match the checksum
969  			 in the IP header.
970  			<legal all>
971  */
972  
973  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000014
974  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
975  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
976  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
977  
978  
979  /* Description		FR_DS
980  
981  			Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START'
982  			TLV
983  			Set if the 'from DS' bit is set in the frame control.
984  			<legal all>
985  */
986  
987  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000014
988  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
989  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
990  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
991  
992  
993  /* Description		TO_DS
994  
995  			Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START'
996  			TLV
997  			Set if the 'to DS' bit is set in the frame control.
998  			<legal all>
999  */
1000  
1001  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000014
1002  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
1003  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
1004  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
1005  
1006  
1007  /* Description		INTRA_BSS
1008  
1009  			This packet needs intra-BSS routing by SW as the 'vdev_id'
1010  			for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START')
1011  			that this MSDU was got in.
1012  
1013  			<legal all>
1014  */
1015  
1016  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000014
1017  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
1018  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
1019  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
1020  
1021  
1022  /* Description		DEST_CHIP_ID
1023  
1024  			If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
1025  			to support intra-BSS routing with multi-chip multi-link
1026  			operation.
1027  
1028  			This indicates into which chip's TCL the packet should be
1029  			 queued.
1030  
1031  			<legal all>
1032  */
1033  
1034  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000014
1035  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
1036  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
1037  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
1038  
1039  
1040  /* Description		DECAP_FORMAT
1041  
1042  			Indicates the format after decapsulation:
1043  
1044  			<enum 0 RAW> No encapsulation
1045  			<enum 1 Native_WiFi>
1046  			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses SNAP/LLC)
1047  
1048  			<enum 3 802_3> Indicate Ethernet
1049  
1050  			<legal all>
1051  */
1052  
1053  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000014
1054  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
1055  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
1056  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
1057  
1058  
1059  /* Description		DEST_CHIP_PMAC_ID
1060  
1061  			If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
1062  			to support intra-BSS routing with multi-chip multi-link
1063  			operation.
1064  
1065  			This indicates into which link/'vdev' the packet should
1066  			be queued in TCL.
1067  
1068  			<legal all>
1069  */
1070  
1071  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET      0x00000014
1072  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB         31
1073  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB         31
1074  #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK        0x80000000
1075  
1076  
1077  /* Description		RESERVED_6A
1078  
1079  			<legal 0>
1080  */
1081  
1082  #define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET                                      0x00000018
1083  #define WBM_RELEASE_RING_RX_RESERVED_6A_LSB                                         0
1084  #define WBM_RELEASE_RING_RX_RESERVED_6A_MSB                                         31
1085  #define WBM_RELEASE_RING_RX_RESERVED_6A_MASK                                        0xffffffff
1086  
1087  
1088  /* Description		RESERVED_7A
1089  
1090  			<legal 0>
1091  */
1092  
1093  #define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET                                      0x0000001c
1094  #define WBM_RELEASE_RING_RX_RESERVED_7A_LSB                                         0
1095  #define WBM_RELEASE_RING_RX_RESERVED_7A_MSB                                         19
1096  #define WBM_RELEASE_RING_RX_RESERVED_7A_MASK                                        0x000fffff
1097  
1098  
1099  /* Description		RING_ID
1100  
1101  			Consumer: TQM/REO/RXDMA/SW
1102  			Producer: SRNG (of RXDMA)
1103  
1104  			For debugging.
1105  			This field is filled in by the SRNG module.
1106  			It help to identify the ring that is being looked <legal
1107  			 all>
1108  */
1109  
1110  #define WBM_RELEASE_RING_RX_RING_ID_OFFSET                                          0x0000001c
1111  #define WBM_RELEASE_RING_RX_RING_ID_LSB                                             20
1112  #define WBM_RELEASE_RING_RX_RING_ID_MSB                                             27
1113  #define WBM_RELEASE_RING_RX_RING_ID_MASK                                            0x0ff00000
1114  
1115  
1116  /* Description		LOOPING_COUNT
1117  
1118  			Consumer: WBM/SW/FW
1119  			Producer: SW/TQM/RXDMA/REO/SWITCH
1120  
1121  			If WBM_internal_error is set, this descriptor is sent to
1122  			 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count
1123  			 is used to indicate an error code.
1124  
1125  			The values reported are documented further in the WBM MLD
1126  			 doc.
1127  
1128  			If WBM_internal_error is not set, the following holds.
1129  
1130  			A count value that indicates the number of times the producer
1131  			 of entries into the Buffer Manager Ring has looped around
1132  			 the ring.
1133  			At initialization time, this value is set to 0. On the first
1134  			 loop, this value is set to 1. After the max value is reached
1135  			 allowed by the number of bits for this field, the count
1136  			 value continues with 0 again.
1137  
1138  			In case SW is the consumer of the ring entries, it can use
1139  			 this field to figure out up to where the producer of entries
1140  			 has created new entries. This eliminates the need to check
1141  			 where the "head pointer' of the ring is located once the
1142  			 SW starts processing an interrupt indicating that new entries
1143  			 have been put into this ring...
1144  
1145  			Also note that SW if it wants only needs to look at the
1146  			LSB bit of this count value.
1147  			<legal all>
1148  */
1149  
1150  #define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET                                    0x0000001c
1151  #define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB                                       28
1152  #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB                                       31
1153  #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK                                      0xf0000000
1154  
1155  
1156  
1157  #endif   // WBM_RELEASE_RING_RX
1158