1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM_RELEASE_RING_H_ 27 #define _WBM_RELEASE_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "buffer_addr_info.h" 32 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 33 34 35 struct wbm_release_ring { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct buffer_addr_info released_buff_or_desc_addr_info; 38 uint32_t release_source_module : 3, // [2:0] 39 reserved_2a : 3, // [5:3] 40 buffer_or_desc_type : 3, // [8:6] 41 reserved_2b : 22, // [30:9] 42 wbm_internal_error : 1; // [31:31] 43 uint32_t reserved_3a : 32; // [31:0] 44 uint32_t reserved_4a : 32; // [31:0] 45 uint32_t reserved_5a : 32; // [31:0] 46 uint32_t reserved_6a : 32; // [31:0] 47 uint32_t reserved_7a : 28, // [27:0] 48 looping_count : 4; // [31:28] 49 #else 50 struct buffer_addr_info released_buff_or_desc_addr_info; 51 uint32_t wbm_internal_error : 1, // [31:31] 52 reserved_2b : 22, // [30:9] 53 buffer_or_desc_type : 3, // [8:6] 54 reserved_2a : 3, // [5:3] 55 release_source_module : 3; // [2:0] 56 uint32_t reserved_3a : 32; // [31:0] 57 uint32_t reserved_4a : 32; // [31:0] 58 uint32_t reserved_5a : 32; // [31:0] 59 uint32_t reserved_6a : 32; // [31:0] 60 uint32_t looping_count : 4, // [31:28] 61 reserved_7a : 28; // [27:0] 62 #endif 63 }; 64 65 66 /* Description RELEASED_BUFF_OR_DESC_ADDR_INFO 67 68 DO NOT USE. This may be a 'BUFFER_ADDR_INFO' structure or 69 a 64-bit virtual address. 70 */ 71 72 73 /* Description BUFFER_ADDR_31_0 74 75 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 76 descriptor OR Link Descriptor 77 78 In case of 'NULL' pointer, this field is set to 0 79 <legal all> 80 */ 81 82 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 83 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 84 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 85 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 86 87 88 /* Description BUFFER_ADDR_39_32 89 90 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 91 descriptor OR Link Descriptor 92 93 In case of 'NULL' pointer, this field is set to 0 94 <legal all> 95 */ 96 97 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 98 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 99 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 100 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 101 102 103 /* Description RETURN_BUFFER_MANAGER 104 105 Consumer: WBM 106 Producer: SW/FW 107 108 In case of 'NULL' pointer, this field is set to 0 109 110 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 111 descriptor OR link descriptor that is being pointed to 112 shall be returned after the frame has been processed. It 113 is used by WBM for routing purposes. 114 115 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 116 to the WMB buffer idle list 117 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 118 to the WBM idle link descriptor idle list, where the chip 119 0 WBM is chosen in case of a multi-chip config 120 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 121 to the chip 1 WBM idle link descriptor idle list 122 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 123 to the chip 2 WBM idle link descriptor idle list 124 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 125 returned to chip 3 WBM idle link descriptor idle list 126 <enum 4 FW_BM> This buffer shall be returned to the FW 127 <enum 5 SW0_BM> This buffer shall be returned to the SW, 128 ring 0 129 <enum 6 SW1_BM> This buffer shall be returned to the SW, 130 ring 1 131 <enum 7 SW2_BM> This buffer shall be returned to the SW, 132 ring 2 133 <enum 8 SW3_BM> This buffer shall be returned to the SW, 134 ring 3 135 <enum 9 SW4_BM> This buffer shall be returned to the SW, 136 ring 4 137 <enum 10 SW5_BM> This buffer shall be returned to the SW, 138 ring 5 139 <enum 11 SW6_BM> This buffer shall be returned to the SW, 140 ring 6 141 142 <legal 0-12> 143 */ 144 145 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 146 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 147 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 148 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 149 150 151 /* Description SW_BUFFER_COOKIE 152 153 Cookie field exclusively used by SW. 154 155 In case of 'NULL' pointer, this field is set to 0 156 157 HW ignores the contents, accept that it passes the programmed 158 value on to other descriptors together with the physical 159 address 160 161 Field can be used by SW to for example associate the buffers 162 physical address with the virtual address 163 The bit definitions as used by SW are within SW HLD specification 164 165 166 NOTE1: 167 The three most significant bits can have a special meaning 168 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 169 and field transmit_bw_restriction is set 170 171 In case of NON punctured transmission: 172 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 173 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 174 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 175 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 176 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 177 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 178 Sw_buffer_cookie[19:18] = 2'b11: reserved 179 180 In case of punctured transmission: 181 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 182 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 183 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 184 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 185 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 186 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 187 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 188 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 189 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 190 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 191 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 192 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 193 Sw_buffer_cookie[19:18] = 2'b11: reserved 194 195 Note: a punctured transmission is indicated by the presence 196 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 197 198 <legal all> 199 */ 200 201 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 202 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 203 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 204 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 205 206 207 /* Description RELEASE_SOURCE_MODULE 208 209 Indicates which module initiated the release of this buffer 210 or descriptor 211 212 <enum 1 release_source_RXDMA> RXDMA released this buffer 213 or descriptor 214 <enum 2 release_source_REO> REO released this buffer or 215 descriptor 216 <enum 5 release_source_FW_RX> FW released this buffer or 217 descriptor 218 <enum 4 release_source_SW_RX> SW released this buffer or 219 descriptor 220 <enum 0 release_source_TQM> DO NOT USE 221 <enum 3 release_source_FW_TX> DO NOT USE 222 <enum 6 release_source_SW_TX> DO NOT USE 223 <legal 0-6> 224 */ 225 226 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 227 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 228 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 229 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 230 231 232 /* Description RESERVED_2A 233 234 This could be different fields depending on the structure. 235 236 <legal all> 237 */ 238 239 #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 240 #define WBM_RELEASE_RING_RESERVED_2A_LSB 3 241 #define WBM_RELEASE_RING_RESERVED_2A_MSB 5 242 #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 243 244 245 /* Description BUFFER_OR_DESC_TYPE 246 247 Consumer: WBM/SW/FW 248 Producer: SW/TQM/RXDMA/REO/SWITCH 249 250 Field only valid when WBM is marked as the return_buffer_manager 251 in the Released_Buffer_address_info 252 253 Indicates that type of buffer or descriptor is being released 254 255 256 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 257 258 <enum 1 msdu_link_descriptor> The address points to an TX 259 MSDU link descriptor 260 <enum 2 mpdu_link_descriptor> The address points to an MPDU 261 link descriptor 262 <enum 3 msdu_ext_descriptor > The address points to an MSDU 263 extension descriptor. 264 In case BM finds this one in a release ring, it passes it 265 on to FW... 266 <enum 4 queue_ext_descriptor> The address points to an TQM 267 queue extension descriptor. WBM should treat this is the 268 same way as a link descriptor. That is, put the 128 byte 269 buffer back in the link buffer idle list. 270 271 TODO: Any restrictions? 272 <legal 0-4> 273 */ 274 275 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 276 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 277 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 278 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 279 280 281 /* Description RESERVED_2B 282 283 This could be different fields depending on the structure. 284 285 <legal all> 286 */ 287 288 #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 289 #define WBM_RELEASE_RING_RESERVED_2B_LSB 9 290 #define WBM_RELEASE_RING_RESERVED_2B_MSB 30 291 #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 292 293 294 /* Description WBM_INTERNAL_ERROR 295 296 Can only be set by WBM. 297 298 Is set when WBM got a buffer pointer but the action was 299 to push it to the idle link descriptor ring or do link related 300 activity 301 OR 302 Is set when WBM got a link buffer pointer but the action 303 was to push it to the buffer descriptor ring 304 305 <legal all> 306 */ 307 308 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 309 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 310 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 311 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 312 313 314 /* Description RESERVED_3A 315 316 This could be different fields depending on the structure. 317 318 <legal all> 319 */ 320 321 #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c 322 #define WBM_RELEASE_RING_RESERVED_3A_LSB 0 323 #define WBM_RELEASE_RING_RESERVED_3A_MSB 31 324 #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff 325 326 327 /* Description RESERVED_4A 328 329 This could be different fields depending on the structure. 330 331 <legal all> 332 */ 333 334 #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 335 #define WBM_RELEASE_RING_RESERVED_4A_LSB 0 336 #define WBM_RELEASE_RING_RESERVED_4A_MSB 31 337 #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff 338 339 340 /* Description RESERVED_5A 341 342 This could be different fields depending on the structure. 343 344 <legal all> 345 */ 346 347 #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 348 #define WBM_RELEASE_RING_RESERVED_5A_LSB 0 349 #define WBM_RELEASE_RING_RESERVED_5A_MSB 31 350 #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff 351 352 353 /* Description RESERVED_6A 354 355 This could be different fields depending on the structure. 356 357 <legal all> 358 */ 359 360 #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 361 #define WBM_RELEASE_RING_RESERVED_6A_LSB 0 362 #define WBM_RELEASE_RING_RESERVED_6A_MSB 31 363 #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff 364 365 366 /* Description RESERVED_7A 367 368 This could be different fields depending on the structure. 369 370 <legal all> 371 */ 372 373 #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c 374 #define WBM_RELEASE_RING_RESERVED_7A_LSB 0 375 #define WBM_RELEASE_RING_RESERVED_7A_MSB 27 376 #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff 377 378 379 /* Description LOOPING_COUNT 380 381 Consumer: WBM/SW/FW 382 Producer: SW/TQM/RXDMA/REO/SWITCH 383 384 If WBM_internal_error is set, this descriptor is sent to 385 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 386 is used to indicate an error code. 387 388 The values reported are documented further in the WBM MLD 389 doc. 390 391 If WBM_internal_error is not set, the following holds. 392 393 A count value that indicates the number of times the producer 394 of entries into the Buffer Manager Ring has looped around 395 the ring. 396 At initialization time, this value is set to 0. On the first 397 loop, this value is set to 1. After the max value is reached 398 allowed by the number of bits for this field, the count 399 value continues with 0 again. 400 401 In case SW is the consumer of the ring entries, it can use 402 this field to figure out up to where the producer of entries 403 has created new entries. This eliminates the need to check 404 where the "head pointer' of the ring is located once the 405 SW starts processing an interrupt indicating that new entries 406 have been put into this ring... 407 408 Also note that SW if it wants only needs to look at the 409 LSB bit of this count value. 410 <legal all> 411 */ 412 413 #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c 414 #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 415 #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 416 #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 417 418 419 420 #endif // WBM_RELEASE_RING 421