1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_MSDU_START_H_ 27 #define _TX_MSDU_START_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_MSDU_START 8 32 33 #define NUM_OF_QWORDS_TX_MSDU_START 4 34 35 36 struct tx_msdu_start { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t msdu_len : 14, // [13:0] 39 first_msdu : 1, // [14:14] 40 last_msdu : 1, // [15:15] 41 encap_type : 2, // [17:16] 42 epd_en : 1, // [18:18] 43 da_sa_present : 2, // [20:19] 44 ipv4_checksum_en : 1, // [21:21] 45 udp_over_ipv4_checksum_en : 1, // [22:22] 46 udp_over_ipv6_checksum_en : 1, // [23:23] 47 tcp_over_ipv4_checksum_en : 1, // [24:24] 48 tcp_over_ipv6_checksum_en : 1, // [25:25] 49 dummy_msdu_delimitation : 1, // [26:26] 50 reserved_0a : 5; // [31:27] 51 uint32_t tso_enable : 1, // [0:0] 52 reserved_1a : 6, // [6:1] 53 tcp_flag : 9, // [15:7] 54 tcp_flag_mask : 9, // [24:16] 55 mesh_enable : 1, // [25:25] 56 reserved_1b : 6; // [31:26] 57 uint32_t l2_length : 16, // [15:0] 58 ip_length : 16; // [31:16] 59 uint32_t tcp_seq_number : 32; // [31:0] 60 uint32_t ip_identification : 16, // [15:0] 61 checksum_offset : 13, // [28:16] 62 partial_checksum_en : 1, // [29:29] 63 reserved_4 : 2; // [31:30] 64 uint32_t payload_start_offset : 14, // [13:0] 65 reserved_5a : 2, // [15:14] 66 payload_end_offset : 14, // [29:16] 67 reserved_5b : 2; // [31:30] 68 uint32_t udp_length : 16, // [15:0] 69 reserved_6 : 16; // [31:16] 70 uint32_t tlv64_padding : 32; // [31:0] 71 #else 72 uint32_t reserved_0a : 5, // [31:27] 73 dummy_msdu_delimitation : 1, // [26:26] 74 tcp_over_ipv6_checksum_en : 1, // [25:25] 75 tcp_over_ipv4_checksum_en : 1, // [24:24] 76 udp_over_ipv6_checksum_en : 1, // [23:23] 77 udp_over_ipv4_checksum_en : 1, // [22:22] 78 ipv4_checksum_en : 1, // [21:21] 79 da_sa_present : 2, // [20:19] 80 epd_en : 1, // [18:18] 81 encap_type : 2, // [17:16] 82 last_msdu : 1, // [15:15] 83 first_msdu : 1, // [14:14] 84 msdu_len : 14; // [13:0] 85 uint32_t reserved_1b : 6, // [31:26] 86 mesh_enable : 1, // [25:25] 87 tcp_flag_mask : 9, // [24:16] 88 tcp_flag : 9, // [15:7] 89 reserved_1a : 6, // [6:1] 90 tso_enable : 1; // [0:0] 91 uint32_t ip_length : 16, // [31:16] 92 l2_length : 16; // [15:0] 93 uint32_t tcp_seq_number : 32; // [31:0] 94 uint32_t reserved_4 : 2, // [31:30] 95 partial_checksum_en : 1, // [29:29] 96 checksum_offset : 13, // [28:16] 97 ip_identification : 16; // [15:0] 98 uint32_t reserved_5b : 2, // [31:30] 99 payload_end_offset : 14, // [29:16] 100 reserved_5a : 2, // [15:14] 101 payload_start_offset : 14; // [13:0] 102 uint32_t reserved_6 : 16, // [31:16] 103 udp_length : 16; // [15:0] 104 uint32_t tlv64_padding : 32; // [31:0] 105 #endif 106 }; 107 108 109 /* Description MSDU_LEN 110 111 MSDU length before encapsulation. It is the same value as 112 the length in the MSDU packet TLV 113 */ 114 115 #define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 116 #define TX_MSDU_START_MSDU_LEN_LSB 0 117 #define TX_MSDU_START_MSDU_LEN_MSB 13 118 #define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff 119 120 121 /* Description FIRST_MSDU 122 123 If set the current MSDU is the first MSDU in MPDU. Used 124 by the OLE during encapsulation. 125 */ 126 127 #define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 128 #define TX_MSDU_START_FIRST_MSDU_LSB 14 129 #define TX_MSDU_START_FIRST_MSDU_MSB 14 130 #define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 131 132 133 /* Description LAST_MSDU 134 135 If set the current MSDU is the last MSDU in MPDU. Used 136 by the OLE during encapsulation. 137 */ 138 139 #define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 140 #define TX_MSDU_START_LAST_MSDU_LSB 15 141 #define TX_MSDU_START_LAST_MSDU_MSB 15 142 #define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 143 144 145 /* Description ENCAP_TYPE 146 147 Indicates the encapsulation that HW will perform: 148 <enum 0 RAW> No encapsulation 149 <enum 1 Native_WiFi> 150 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 151 152 <enum 3 802_3> DO NOT USE. Indicate Ethernet 153 Used by the OLE during encapsulation. 154 <legal all> 155 */ 156 157 #define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 158 #define TX_MSDU_START_ENCAP_TYPE_LSB 16 159 #define TX_MSDU_START_ENCAP_TYPE_MSB 17 160 #define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 161 162 163 /* Description EPD_EN 164 165 Consumer: TXOLE 166 Producer: SW/TCL 167 168 If set to one use EPD instead of LPD 169 <legal all> 170 */ 171 172 #define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 173 #define TX_MSDU_START_EPD_EN_LSB 18 174 #define TX_MSDU_START_EPD_EN_MSB 18 175 #define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 176 177 178 /* Description DA_SA_PRESENT 179 180 Used for 11ah 181 182 Indicates the encapsulation that HW will perform: 183 <enum 0 DA_SA_IS_ABSENT> DA and SA absent 184 <enum 1 DA_IS_PRESENT> DA Present, SA Absent 185 <enum 2 SA_IS_PRESENT> 186 <enum 3 DA_SA_IS_PRESENT> Both DA and SA are present 187 Used by the OLE during encapsulation. 188 189 TXDMA gets this configuration from a sw configuration register. 190 191 192 <legal all> 193 */ 194 195 #define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 196 #define TX_MSDU_START_DA_SA_PRESENT_LSB 19 197 #define TX_MSDU_START_DA_SA_PRESENT_MSB 20 198 #define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 199 200 201 /* Description IPV4_CHECKSUM_EN 202 203 Enable IPv4 checksum replacement 204 */ 205 206 #define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 207 #define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 208 #define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 209 #define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 210 211 212 /* Description UDP_OVER_IPV4_CHECKSUM_EN 213 214 Enable UDP over IPv4 checksum replacement. UDP checksum 215 over IPv4 is optional for TCP/IP stacks. 216 */ 217 218 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 219 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 220 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 221 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 222 223 224 /* Description UDP_OVER_IPV6_CHECKSUM_EN 225 226 Enable UDP over IPv6 checksum replacement. UDP checksum 227 over IPv6 is mandatory for TCP/IP stacks. 228 */ 229 230 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 231 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 232 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 233 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 234 235 236 /* Description TCP_OVER_IPV4_CHECKSUM_EN 237 238 Enable TCP checksum over IPv4 replacement 239 */ 240 241 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 242 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 243 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 244 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 245 246 247 /* Description TCP_OVER_IPV6_CHECKSUM_EN 248 249 Enable TCP checksum over IPv6 eplacement 250 */ 251 252 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 253 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 254 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 255 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 256 257 258 /* Description DUMMY_MSDU_DELIMITATION 259 260 This bit is mainly for debug. 261 262 TXDMA sets this bit when sending a dummy 'TX_MSDU_END' + 'TX_MSDU_START' 263 sequence for a user to delimit user arbitration where it 264 could switch to packet data from other users before continuing 265 this MSDU. 266 267 This is done mainly for long raw Wi-Fi packets where TXDMA 268 needs to switch users in the midst of the packet but other 269 blocks assume TXDMA switch only at MSDU boundaries. 270 <legal all> 271 */ 272 273 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 274 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 275 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 276 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 277 278 279 /* Description RESERVED_0A 280 281 FW will set to 0, MAC will ignore. <legal 0> 282 */ 283 284 #define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 285 #define TX_MSDU_START_RESERVED_0A_LSB 27 286 #define TX_MSDU_START_RESERVED_0A_MSB 31 287 #define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 288 289 290 /* Description TSO_ENABLE 291 292 Enable transmit segmentation offload. 293 294 In case MSDU_EXTENSION is used, TXDMA gets the setting for 295 this bit from that descriptor. 296 In case MSDU_EXTENSION is NOT use, TXDMA gets the setting 297 for this bit from an internal SW programmable register. 298 299 <legal all> 300 */ 301 302 #define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 303 #define TX_MSDU_START_TSO_ENABLE_LSB 32 304 #define TX_MSDU_START_TSO_ENABLE_MSB 32 305 #define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 306 307 308 /* Description RESERVED_1A 309 310 FW will set to 0, MAC will ignore. <legal 0> 311 */ 312 313 #define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 314 #define TX_MSDU_START_RESERVED_1A_LSB 33 315 #define TX_MSDU_START_RESERVED_1A_MSB 38 316 #define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 317 318 319 /* Description TCP_FLAG 320 321 TCP flags 322 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 323 */ 324 325 #define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 326 #define TX_MSDU_START_TCP_FLAG_LSB 39 327 #define TX_MSDU_START_TCP_FLAG_MSB 47 328 #define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 329 330 331 /* Description TCP_FLAG_MASK 332 333 TCP flag mask. Tcp_flag is inserted into the header based 334 on the mask, if TSO is enabled 335 */ 336 337 #define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 338 #define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 339 #define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 340 #define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 341 342 343 /* Description MESH_ENABLE 344 345 If set to 1: 346 347 * For raw WiFi frames, this indicates transmission to a 348 mesh STA but is ignored by HW 349 350 * For native WiFi frames, this is used to indicate to TX 351 OLE that a 'Mesh Control' field is present between the 352 header and the LLC 353 */ 354 355 #define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 356 #define TX_MSDU_START_MESH_ENABLE_LSB 57 357 #define TX_MSDU_START_MESH_ENABLE_MSB 57 358 #define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 359 360 361 /* Description RESERVED_1B 362 363 FW will set to 0, MAC will ignore. <legal 0> 364 */ 365 366 #define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 367 #define TX_MSDU_START_RESERVED_1B_LSB 58 368 #define TX_MSDU_START_RESERVED_1B_MSB 63 369 #define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 370 371 372 /* Description L2_LENGTH 373 374 L2 length for the msdu, if TSO is enabled <legal all> 375 */ 376 377 #define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 378 #define TX_MSDU_START_L2_LENGTH_LSB 0 379 #define TX_MSDU_START_L2_LENGTH_MSB 15 380 #define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff 381 382 383 /* Description IP_LENGTH 384 385 IP length for the msdu, if TSO is enabled <legal all> 386 */ 387 388 #define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 389 #define TX_MSDU_START_IP_LENGTH_LSB 16 390 #define TX_MSDU_START_IP_LENGTH_MSB 31 391 #define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 392 393 394 /* Description TCP_SEQ_NUMBER 395 396 Tcp_seq_number for the msdu, if TSO is enabled <legal all> 397 398 */ 399 400 #define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 401 #define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 402 #define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 403 #define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 404 405 406 /* Description IP_IDENTIFICATION 407 408 IP_identification for the msdu, if TSO is enabled <legal 409 all> 410 */ 411 412 #define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 413 #define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 414 #define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 415 #define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff 416 417 418 /* Description CHECKSUM_OFFSET 419 420 The calculated checksum from start offset to end offset 421 will be added to the checksum at the offset given by this 422 field<legal all> 423 */ 424 425 #define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 426 #define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 427 #define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 428 #define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 429 430 431 /* Description PARTIAL_CHECKSUM_EN 432 433 Enable Partial Checksum, MAV feature 434 */ 435 436 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 437 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 438 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 439 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 440 441 442 /* Description RESERVED_4 443 444 <legal 0> 445 */ 446 447 #define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 448 #define TX_MSDU_START_RESERVED_4_LSB 30 449 #define TX_MSDU_START_RESERVED_4_MSB 31 450 #define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 451 452 453 /* Description PAYLOAD_START_OFFSET 454 455 L4 checksum calculations will start fromt this offset 456 <legal all> 457 */ 458 459 #define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 460 #define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 461 #define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 462 #define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 463 464 465 /* Description RESERVED_5A 466 467 <legal 0> 468 */ 469 470 #define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 471 #define TX_MSDU_START_RESERVED_5A_LSB 46 472 #define TX_MSDU_START_RESERVED_5A_MSB 47 473 #define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 474 475 476 /* Description PAYLOAD_END_OFFSET 477 478 L4 checksum calculations will end at this offset. 479 <legal all> 480 */ 481 482 #define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 483 #define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 484 #define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 485 #define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 486 487 488 /* Description RESERVED_5B 489 490 <legal 0> 491 */ 492 493 #define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 494 #define TX_MSDU_START_RESERVED_5B_LSB 62 495 #define TX_MSDU_START_RESERVED_5B_MSB 63 496 #define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 497 498 499 /* Description UDP_LENGTH 500 501 This field indicates UDP length/UDP lite checksum coverage 502 field to be used by L4 checksum engine in case TSO is enabled 503 for UDP/UDP lite respectively 504 <legal all> 505 */ 506 507 #define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 508 #define TX_MSDU_START_UDP_LENGTH_LSB 0 509 #define TX_MSDU_START_UDP_LENGTH_MSB 15 510 #define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff 511 512 513 /* Description RESERVED_6 514 515 <legal 0> 516 */ 517 518 #define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 519 #define TX_MSDU_START_RESERVED_6_LSB 16 520 #define TX_MSDU_START_RESERVED_6_MSB 31 521 #define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 522 523 524 /* Description TLV64_PADDING 525 526 Automatic DWORD padding inserted while converting TLV32 527 to TLV64 for 64 bit ARCH 528 <legal 0> 529 */ 530 531 #define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 532 #define TX_MSDU_START_TLV64_PADDING_LSB 32 533 #define TX_MSDU_START_TLV64_PADDING_MSB 63 534 #define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 535 536 537 538 #endif // TX_MSDU_START 539