1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _TX_MSDU_EXTENSION_H_
27 #define _TX_MSDU_EXTENSION_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
32 
33 
34 struct tx_msdu_extension {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t tso_enable                                              :  1, // [0:0]
37                       reserved_0a                                             :  6, // [6:1]
38                       tcp_flag                                                :  9, // [15:7]
39                       tcp_flag_mask                                           :  9, // [24:16]
40                       reserved_0b                                             :  7; // [31:25]
41              uint32_t l2_length                                               : 16, // [15:0]
42                       ip_length                                               : 16; // [31:16]
43              uint32_t tcp_seq_number                                          : 32; // [31:0]
44              uint32_t ip_identification                                       : 16, // [15:0]
45                       udp_length                                              : 16; // [31:16]
46              uint32_t checksum_offset                                         : 14, // [13:0]
47                       partial_checksum_en                                     :  1, // [14:14]
48                       reserved_4a                                             :  1, // [15:15]
49                       payload_start_offset                                    : 14, // [29:16]
50                       reserved_4b                                             :  2; // [31:30]
51              uint32_t payload_end_offset                                      : 14, // [13:0]
52                       reserved_5a                                             :  2, // [15:14]
53                       wds                                                     :  1, // [16:16]
54                       reserved_5b                                             : 15; // [31:17]
55              uint32_t buf0_ptr_31_0                                           : 32; // [31:0]
56              uint32_t buf0_ptr_39_32                                          :  8, // [7:0]
57                       extn_override                                           :  1, // [8:8]
58                       encap_type                                              :  2, // [10:9]
59                       encrypt_type                                            :  4, // [14:11]
60                       tqm_no_drop                                             :  1, // [15:15]
61                       buf0_len                                                : 16; // [31:16]
62              uint32_t buf1_ptr_31_0                                           : 32; // [31:0]
63              uint32_t buf1_ptr_39_32                                          :  8, // [7:0]
64                       epd                                                     :  1, // [8:8]
65                       mesh_enable                                             :  2, // [10:9]
66                       reserved_9a                                             :  5, // [15:11]
67                       buf1_len                                                : 16; // [31:16]
68              uint32_t buf2_ptr_31_0                                           : 32; // [31:0]
69              uint32_t buf2_ptr_39_32                                          :  8, // [7:0]
70                       dscp_tid_table_num                                      :  6, // [13:8]
71                       reserved_11a                                            :  2, // [15:14]
72                       buf2_len                                                : 16; // [31:16]
73              uint32_t buf3_ptr_31_0                                           : 32; // [31:0]
74              uint32_t buf3_ptr_39_32                                          :  8, // [7:0]
75                       reserved_13a                                            :  8, // [15:8]
76                       buf3_len                                                : 16; // [31:16]
77              uint32_t buf4_ptr_31_0                                           : 32; // [31:0]
78              uint32_t buf4_ptr_39_32                                          :  8, // [7:0]
79                       reserved_15a                                            :  8, // [15:8]
80                       buf4_len                                                : 16; // [31:16]
81              uint32_t buf5_ptr_31_0                                           : 32; // [31:0]
82              uint32_t buf5_ptr_39_32                                          :  8, // [7:0]
83                       reserved_17a                                            :  8, // [15:8]
84                       buf5_len                                                : 16; // [31:16]
85 #else
86              uint32_t reserved_0b                                             :  7, // [31:25]
87                       tcp_flag_mask                                           :  9, // [24:16]
88                       tcp_flag                                                :  9, // [15:7]
89                       reserved_0a                                             :  6, // [6:1]
90                       tso_enable                                              :  1; // [0:0]
91              uint32_t ip_length                                               : 16, // [31:16]
92                       l2_length                                               : 16; // [15:0]
93              uint32_t tcp_seq_number                                          : 32; // [31:0]
94              uint32_t udp_length                                              : 16, // [31:16]
95                       ip_identification                                       : 16; // [15:0]
96              uint32_t reserved_4b                                             :  2, // [31:30]
97                       payload_start_offset                                    : 14, // [29:16]
98                       reserved_4a                                             :  1, // [15:15]
99                       partial_checksum_en                                     :  1, // [14:14]
100                       checksum_offset                                         : 14; // [13:0]
101              uint32_t reserved_5b                                             : 15, // [31:17]
102                       wds                                                     :  1, // [16:16]
103                       reserved_5a                                             :  2, // [15:14]
104                       payload_end_offset                                      : 14; // [13:0]
105              uint32_t buf0_ptr_31_0                                           : 32; // [31:0]
106              uint32_t buf0_len                                                : 16, // [31:16]
107                       tqm_no_drop                                             :  1, // [15:15]
108                       encrypt_type                                            :  4, // [14:11]
109                       encap_type                                              :  2, // [10:9]
110                       extn_override                                           :  1, // [8:8]
111                       buf0_ptr_39_32                                          :  8; // [7:0]
112              uint32_t buf1_ptr_31_0                                           : 32; // [31:0]
113              uint32_t buf1_len                                                : 16, // [31:16]
114                       reserved_9a                                             :  5, // [15:11]
115                       mesh_enable                                             :  2, // [10:9]
116                       epd                                                     :  1, // [8:8]
117                       buf1_ptr_39_32                                          :  8; // [7:0]
118              uint32_t buf2_ptr_31_0                                           : 32; // [31:0]
119              uint32_t buf2_len                                                : 16, // [31:16]
120                       reserved_11a                                            :  2, // [15:14]
121                       dscp_tid_table_num                                      :  6, // [13:8]
122                       buf2_ptr_39_32                                          :  8; // [7:0]
123              uint32_t buf3_ptr_31_0                                           : 32; // [31:0]
124              uint32_t buf3_len                                                : 16, // [31:16]
125                       reserved_13a                                            :  8, // [15:8]
126                       buf3_ptr_39_32                                          :  8; // [7:0]
127              uint32_t buf4_ptr_31_0                                           : 32; // [31:0]
128              uint32_t buf4_len                                                : 16, // [31:16]
129                       reserved_15a                                            :  8, // [15:8]
130                       buf4_ptr_39_32                                          :  8; // [7:0]
131              uint32_t buf5_ptr_31_0                                           : 32; // [31:0]
132              uint32_t buf5_len                                                : 16, // [31:16]
133                       reserved_17a                                            :  8, // [15:8]
134                       buf5_ptr_39_32                                          :  8; // [7:0]
135 #endif
136 };
137 
138 
139 /* Description		TSO_ENABLE
140 
141 			Enable transmit segmentation offload <legal all>
142 */
143 
144 #define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET                                         0x00000000
145 #define TX_MSDU_EXTENSION_TSO_ENABLE_LSB                                            0
146 #define TX_MSDU_EXTENSION_TSO_ENABLE_MSB                                            0
147 #define TX_MSDU_EXTENSION_TSO_ENABLE_MASK                                           0x00000001
148 
149 
150 /* Description		RESERVED_0A
151 
152 			FW will set to 0, MAC will ignore.  <legal 0>
153 */
154 
155 #define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET                                        0x00000000
156 #define TX_MSDU_EXTENSION_RESERVED_0A_LSB                                           1
157 #define TX_MSDU_EXTENSION_RESERVED_0A_MSB                                           6
158 #define TX_MSDU_EXTENSION_RESERVED_0A_MASK                                          0x0000007e
159 
160 
161 /* Description		TCP_FLAG
162 
163 			TCP flags
164 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
165 */
166 
167 #define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET                                           0x00000000
168 #define TX_MSDU_EXTENSION_TCP_FLAG_LSB                                              7
169 #define TX_MSDU_EXTENSION_TCP_FLAG_MSB                                              15
170 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK                                             0x0000ff80
171 
172 
173 /* Description		TCP_FLAG_MASK
174 
175 			TCP flag mask. Tcp_flag is inserted into the header based
176 			 on the mask, if TSO is enabled
177 */
178 
179 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET                                      0x00000000
180 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB                                         16
181 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB                                         24
182 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK                                        0x01ff0000
183 
184 
185 /* Description		RESERVED_0B
186 
187 			FW will set to 0, MAC will ignore.  <legal 0>
188 */
189 
190 #define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET                                        0x00000000
191 #define TX_MSDU_EXTENSION_RESERVED_0B_LSB                                           25
192 #define TX_MSDU_EXTENSION_RESERVED_0B_MSB                                           31
193 #define TX_MSDU_EXTENSION_RESERVED_0B_MASK                                          0xfe000000
194 
195 
196 /* Description		L2_LENGTH
197 
198 			L2 length for the msdu, if TSO is enabled <legal all>
199 */
200 
201 #define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET                                          0x00000004
202 #define TX_MSDU_EXTENSION_L2_LENGTH_LSB                                             0
203 #define TX_MSDU_EXTENSION_L2_LENGTH_MSB                                             15
204 #define TX_MSDU_EXTENSION_L2_LENGTH_MASK                                            0x0000ffff
205 
206 
207 /* Description		IP_LENGTH
208 
209 			IP length for the msdu, if TSO is enabled <legal all>
210 */
211 
212 #define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET                                          0x00000004
213 #define TX_MSDU_EXTENSION_IP_LENGTH_LSB                                             16
214 #define TX_MSDU_EXTENSION_IP_LENGTH_MSB                                             31
215 #define TX_MSDU_EXTENSION_IP_LENGTH_MASK                                            0xffff0000
216 
217 
218 /* Description		TCP_SEQ_NUMBER
219 
220 			Tcp_seq_number for the msdu, if TSO is enabled <legal all>
221 
222 */
223 
224 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET                                     0x00000008
225 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB                                        0
226 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB                                        31
227 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK                                       0xffffffff
228 
229 
230 /* Description		IP_IDENTIFICATION
231 
232 			IP_identification for the msdu, if TSO is enabled <legal
233 			 all>
234 */
235 
236 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET                                  0x0000000c
237 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB                                     0
238 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB                                     15
239 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK                                    0x0000ffff
240 
241 
242 /* Description		UDP_LENGTH
243 
244 			TXDMA is copies this field into MSDU START TLV
245 */
246 
247 #define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET                                         0x0000000c
248 #define TX_MSDU_EXTENSION_UDP_LENGTH_LSB                                            16
249 #define TX_MSDU_EXTENSION_UDP_LENGTH_MSB                                            31
250 #define TX_MSDU_EXTENSION_UDP_LENGTH_MASK                                           0xffff0000
251 
252 
253 /* Description		CHECKSUM_OFFSET
254 
255 			The calculated checksum from start offset to end offset
256 			will be added to the checksum at the offset given by this
257 			 field<legal all>
258 */
259 
260 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET                                    0x00000010
261 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB                                       0
262 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB                                       13
263 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK                                      0x00003fff
264 
265 
266 /* Description		PARTIAL_CHECKSUM_EN
267 
268 			Partial Checksum Enable Bit.
269 			<legal 0-1>
270 */
271 
272 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET                                0x00000010
273 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB                                   14
274 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB                                   14
275 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK                                  0x00004000
276 
277 
278 /* Description		RESERVED_4A
279 
280 			<Legal 0>
281 */
282 
283 #define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET                                        0x00000010
284 #define TX_MSDU_EXTENSION_RESERVED_4A_LSB                                           15
285 #define TX_MSDU_EXTENSION_RESERVED_4A_MSB                                           15
286 #define TX_MSDU_EXTENSION_RESERVED_4A_MASK                                          0x00008000
287 
288 
289 /* Description		PAYLOAD_START_OFFSET
290 
291 			L4 checksum calculations will start fromt this offset
292 			<Legal all>
293 */
294 
295 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET                               0x00000010
296 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB                                  16
297 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB                                  29
298 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK                                 0x3fff0000
299 
300 
301 /* Description		RESERVED_4B
302 
303 			<Legal 0>
304 */
305 
306 #define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET                                        0x00000010
307 #define TX_MSDU_EXTENSION_RESERVED_4B_LSB                                           30
308 #define TX_MSDU_EXTENSION_RESERVED_4B_MSB                                           31
309 #define TX_MSDU_EXTENSION_RESERVED_4B_MASK                                          0xc0000000
310 
311 
312 /* Description		PAYLOAD_END_OFFSET
313 
314 			L4 checksum calculations will end at this offset.
315 			<Legal all>
316 */
317 
318 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET                                 0x00000014
319 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB                                    0
320 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB                                    13
321 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK                                   0x00003fff
322 
323 
324 /* Description		RESERVED_5A
325 
326 			<Legal 0>
327 */
328 
329 #define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET                                        0x00000014
330 #define TX_MSDU_EXTENSION_RESERVED_5A_LSB                                           14
331 #define TX_MSDU_EXTENSION_RESERVED_5A_MSB                                           15
332 #define TX_MSDU_EXTENSION_RESERVED_5A_MASK                                          0x0000c000
333 
334 
335 /* Description		WDS
336 
337 			If set the current packet is 4-address frame.  Required
338 			because an aggregate can include some frames with 3 address
339 			 format and other frames with 4 address format.  Used by
340 			 the OLE during encapsulation.
341 			Note: there is also global wds tx control in the TX_PEER_ENTRY
342 
343 			<legal all>
344 */
345 
346 #define TX_MSDU_EXTENSION_WDS_OFFSET                                                0x00000014
347 #define TX_MSDU_EXTENSION_WDS_LSB                                                   16
348 #define TX_MSDU_EXTENSION_WDS_MSB                                                   16
349 #define TX_MSDU_EXTENSION_WDS_MASK                                                  0x00010000
350 
351 
352 /* Description		RESERVED_5B
353 
354 			<Legal 0>
355 */
356 
357 #define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET                                        0x00000014
358 #define TX_MSDU_EXTENSION_RESERVED_5B_LSB                                           17
359 #define TX_MSDU_EXTENSION_RESERVED_5B_MSB                                           31
360 #define TX_MSDU_EXTENSION_RESERVED_5B_MASK                                          0xfffe0000
361 
362 
363 /* Description		BUF0_PTR_31_0
364 
365 			Lower 32 bits of the first buffer pointer
366 
367 			NOTE: SW/FW manages the 'cookie' info related to this buffer
368 			 together with the 'cookie' info for this MSDU_EXTENSION
369 			 descriptor
370 			<legal all>
371 */
372 
373 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET                                      0x00000018
374 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB                                         0
375 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB                                         31
376 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK                                        0xffffffff
377 
378 
379 /* Description		BUF0_PTR_39_32
380 
381 			Upper 8 bits of the first buffer pointer <legal all>
382 */
383 
384 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET                                     0x0000001c
385 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB                                        0
386 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB                                        7
387 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK                                       0x000000ff
388 
389 
390 /* Description		EXTN_OVERRIDE
391 
392 			Field only used by TCL
393 
394 			When set, the fields encap_type, Encrypt_type, TQM_NO_DROP,
395 			EPD and mesh_enable are valid and override any TCL per-bank
396 			 registers specifying these values (except TQM_NO_DROP).
397 
398 
399 			When clear, the values for encap_type, Encrypt_type, EPD,
400 			mesh_enable and DSCP_TID_TABLE_NUM are taken from per-bank
401 			 registers in TCL and TQM_NO_DROP is not being requested
402 			 by SW.
403 
404 			<legal all>
405 */
406 
407 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET                                      0x0000001c
408 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB                                         8
409 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB                                         8
410 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK                                        0x00000100
411 
412 
413 /* Description		ENCAP_TYPE
414 
415 			Field only used by TCL, only valid if Extn_override is set.
416 
417 
418 			Indicates the encapsulation that HW will perform:
419 			<enum 0 RAW> No encapsulation
420 			<enum 1 Native_WiFi>
421 			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses SNAP/LLC)
422 
423 			<enum 3 802_3> DO NOT USE. Indicate Ethernet
424 
425 			Used by the OLE during encapsulation.
426 			<legal all>
427 */
428 
429 #define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET                                         0x0000001c
430 #define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB                                            9
431 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB                                            10
432 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK                                           0x00000600
433 
434 
435 /* Description		ENCRYPT_TYPE
436 
437 			Field only used by TCL, only valid if Extn_override is set
438 			 and encap_type = RAW
439 
440 			Indicates type of decrypt cipher used (as defined in the
441 			 peer entry)
442 			<enum 0 wep_40> WEP 40-bit
443 			<enum 1 wep_104> WEP 104-bit
444 			<enum 2 tkip_no_mic> TKIP without MIC
445 			<enum 3 wep_128> WEP 128-bit
446 			<enum 4 tkip_with_mic> TKIP with MIC
447 			<enum 5 wapi> WAPI
448 			<enum 6 aes_ccmp_128> AES CCMP 128
449 			<enum 7 no_cipher> No crypto
450 			<enum 8 aes_ccmp_256> AES CCMP 256
451 			<enum 9 aes_gcmp_128> AES CCMP 128
452 			<enum 10 aes_gcmp_256> AES CCMP 256
453 			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
454 
455 			<enum 12 wep_varied_width> DO not use... Only for higher
456 			 layer modules..
457 			<legal 0-12>
458 */
459 
460 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET                                       0x0000001c
461 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB                                          11
462 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB                                          14
463 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK                                         0x00007800
464 
465 
466 /* Description		TQM_NO_DROP
467 
468 			Field only used by TCL, only valid if Extn_override is set.
469 
470 
471 			This bit is used to stop TQM from dropping MSDUs while adding
472 			 them to MSDU flows1'b1: Do not drop MSDU when any of the
473 			 threshold value is met while adding MSDU in a flow1'b1:
474 			Drop MSDU when any of the threshold value is met while adding
475 			 MSDU in a flow
476 			Note: TCL can also have CCE/LCE rules to set 'TQM_NO_DROP'
477 			which will be OR'd to this value.
478 			<legal all>
479 */
480 
481 #define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET                                        0x0000001c
482 #define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB                                           15
483 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB                                           15
484 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK                                          0x00008000
485 
486 
487 /* Description		BUF0_LEN
488 
489 			Length of the first buffer <legal all>
490 */
491 
492 #define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET                                           0x0000001c
493 #define TX_MSDU_EXTENSION_BUF0_LEN_LSB                                              16
494 #define TX_MSDU_EXTENSION_BUF0_LEN_MSB                                              31
495 #define TX_MSDU_EXTENSION_BUF0_LEN_MASK                                             0xffff0000
496 
497 
498 /* Description		BUF1_PTR_31_0
499 
500 			Lower 32 bits of the second buffer pointer
501 
502 			NOTE: SW/FW manages the 'cookie' info related to this buffer
503 			 together with the 'cookie' info for this MSDU_EXTENSION
504 			 descriptor
505 			<legal all>
506 */
507 
508 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET                                      0x00000020
509 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB                                         0
510 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB                                         31
511 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK                                        0xffffffff
512 
513 
514 /* Description		BUF1_PTR_39_32
515 
516 			Upper 8 bits of the second buffer pointer <legal all>
517 */
518 
519 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET                                     0x00000024
520 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB                                        0
521 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB                                        7
522 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK                                       0x000000ff
523 
524 
525 /* Description		EPD
526 
527 			Field only used by TCL, only valid if Extn_override is set.
528 
529 
530 			When this bit is set then input packet is an EPD type
531 			<legal all>
532 */
533 
534 #define TX_MSDU_EXTENSION_EPD_OFFSET                                                0x00000024
535 #define TX_MSDU_EXTENSION_EPD_LSB                                                   8
536 #define TX_MSDU_EXTENSION_EPD_MSB                                                   8
537 #define TX_MSDU_EXTENSION_EPD_MASK                                                  0x00000100
538 
539 
540 /* Description		MESH_ENABLE
541 
542 			Field only used by TCL, only valid if Extn_override is set.
543 
544 
545 			If set to a non-zero value:
546 			* For raw WiFi frames, this indicates transmission to a
547 			mesh STA, enabling the interpretation of the 'Mesh Control
548 			 Present' bit (bit 8) of QoS Control (otherwise this bit
549 			 is ignored). The interpretation of the A-MSDU 'Length'
550 			field is decided by the e-numerations below.
551 			* For native WiFi frames, this indicates that a 'Mesh Control'
552 			field is present between the header and the LLC. The three
553 			 non-zero values are interchangeable.
554 
555 			<enum 0 MESH_DISABLE>
556 			<enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes
557 			 the length of Mesh Control.
558 			<enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes
559 			 the length of Mesh Control.
560 			<enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and
561 			 excludes the length of Mesh Control. This is 802.11s-compliant.
562 
563 			<legal 0-3>
564 */
565 
566 #define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET                                        0x00000024
567 #define TX_MSDU_EXTENSION_MESH_ENABLE_LSB                                           9
568 #define TX_MSDU_EXTENSION_MESH_ENABLE_MSB                                           10
569 #define TX_MSDU_EXTENSION_MESH_ENABLE_MASK                                          0x00000600
570 
571 
572 /* Description		RESERVED_9A
573 
574 			<Legal 0>
575 */
576 
577 #define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET                                        0x00000024
578 #define TX_MSDU_EXTENSION_RESERVED_9A_LSB                                           11
579 #define TX_MSDU_EXTENSION_RESERVED_9A_MSB                                           15
580 #define TX_MSDU_EXTENSION_RESERVED_9A_MASK                                          0x0000f800
581 
582 
583 /* Description		BUF1_LEN
584 
585 			Length of the second buffer <legal all>
586 */
587 
588 #define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET                                           0x00000024
589 #define TX_MSDU_EXTENSION_BUF1_LEN_LSB                                              16
590 #define TX_MSDU_EXTENSION_BUF1_LEN_MSB                                              31
591 #define TX_MSDU_EXTENSION_BUF1_LEN_MASK                                             0xffff0000
592 
593 
594 /* Description		BUF2_PTR_31_0
595 
596 			Lower 32 bits of the third buffer pointer
597 			NOTE: SW/FW manages the 'cookie' info related to this buffer
598 			 together with the 'cookie' info for this MSDU_EXTENSION
599 			 descriptor
600 			<legal all>
601 */
602 
603 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET                                      0x00000028
604 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB                                         0
605 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB                                         31
606 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK                                        0xffffffff
607 
608 
609 /* Description		BUF2_PTR_39_32
610 
611 			Upper 8 bits of the third buffer pointer <legal all>
612 */
613 
614 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET                                     0x0000002c
615 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB                                        0
616 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB                                        7
617 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK                                       0x000000ff
618 
619 
620 /* Description		DSCP_TID_TABLE_NUM
621 
622 			Field only used by TCL, only valid if Extn_override is set.
623 
624 
625 			This specifies the DSCP to TID mapping table to be used
626 			for the MSDU
627 			<legal all>
628 */
629 
630 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET                                 0x0000002c
631 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB                                    8
632 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB                                    13
633 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK                                   0x00003f00
634 
635 
636 /* Description		RESERVED_11A
637 
638 			<Legal 0>
639 */
640 
641 #define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET                                       0x0000002c
642 #define TX_MSDU_EXTENSION_RESERVED_11A_LSB                                          14
643 #define TX_MSDU_EXTENSION_RESERVED_11A_MSB                                          15
644 #define TX_MSDU_EXTENSION_RESERVED_11A_MASK                                         0x0000c000
645 
646 
647 /* Description		BUF2_LEN
648 
649 			Length of the third buffer <legal all>
650 */
651 
652 #define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET                                           0x0000002c
653 #define TX_MSDU_EXTENSION_BUF2_LEN_LSB                                              16
654 #define TX_MSDU_EXTENSION_BUF2_LEN_MSB                                              31
655 #define TX_MSDU_EXTENSION_BUF2_LEN_MASK                                             0xffff0000
656 
657 
658 /* Description		BUF3_PTR_31_0
659 
660 			Lower 32 bits of the fourth buffer pointer
661 
662 			NOTE: SW/FW manages the 'cookie' info related to this buffer
663 			 together with the 'cookie' info for this MSDU_EXTENSION
664 			 descriptor
665 			 <legal all>
666 */
667 
668 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET                                      0x00000030
669 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB                                         0
670 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB                                         31
671 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK                                        0xffffffff
672 
673 
674 /* Description		BUF3_PTR_39_32
675 
676 			Upper 8 bits of the fourth buffer pointer <legal all>
677 */
678 
679 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET                                     0x00000034
680 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB                                        0
681 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB                                        7
682 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK                                       0x000000ff
683 
684 
685 /* Description		RESERVED_13A
686 
687 			<Legal 0>
688 */
689 
690 #define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET                                       0x00000034
691 #define TX_MSDU_EXTENSION_RESERVED_13A_LSB                                          8
692 #define TX_MSDU_EXTENSION_RESERVED_13A_MSB                                          15
693 #define TX_MSDU_EXTENSION_RESERVED_13A_MASK                                         0x0000ff00
694 
695 
696 /* Description		BUF3_LEN
697 
698 			Length of the fourth buffer <legal all>
699 */
700 
701 #define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET                                           0x00000034
702 #define TX_MSDU_EXTENSION_BUF3_LEN_LSB                                              16
703 #define TX_MSDU_EXTENSION_BUF3_LEN_MSB                                              31
704 #define TX_MSDU_EXTENSION_BUF3_LEN_MASK                                             0xffff0000
705 
706 
707 /* Description		BUF4_PTR_31_0
708 
709 			Lower 32 bits of the fifth buffer pointer
710 
711 			NOTE: SW/FW manages the 'cookie' info related to this buffer
712 			 together with the 'cookie' info for this MSDU_EXTENSION
713 			 descriptor
714 			<legal all>
715 */
716 
717 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET                                      0x00000038
718 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB                                         0
719 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB                                         31
720 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK                                        0xffffffff
721 
722 
723 /* Description		BUF4_PTR_39_32
724 
725 			Upper 8 bits of the fifth buffer pointer <legal all>
726 */
727 
728 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET                                     0x0000003c
729 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB                                        0
730 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB                                        7
731 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK                                       0x000000ff
732 
733 
734 /* Description		RESERVED_15A
735 
736 			<Legal 0>
737 */
738 
739 #define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET                                       0x0000003c
740 #define TX_MSDU_EXTENSION_RESERVED_15A_LSB                                          8
741 #define TX_MSDU_EXTENSION_RESERVED_15A_MSB                                          15
742 #define TX_MSDU_EXTENSION_RESERVED_15A_MASK                                         0x0000ff00
743 
744 
745 /* Description		BUF4_LEN
746 
747 			Length of the fifth buffer <legal all>
748 */
749 
750 #define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET                                           0x0000003c
751 #define TX_MSDU_EXTENSION_BUF4_LEN_LSB                                              16
752 #define TX_MSDU_EXTENSION_BUF4_LEN_MSB                                              31
753 #define TX_MSDU_EXTENSION_BUF4_LEN_MASK                                             0xffff0000
754 
755 
756 /* Description		BUF5_PTR_31_0
757 
758 			Lower 32 bits of the sixth buffer pointer
759 
760 			NOTE: SW/FW manages the 'cookie' info related to this buffer
761 			 together with the 'cookie' info for this MSDU_EXTENSION
762 			 descriptor
763 			 <legal all>
764 */
765 
766 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET                                      0x00000040
767 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB                                         0
768 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB                                         31
769 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK                                        0xffffffff
770 
771 
772 /* Description		BUF5_PTR_39_32
773 
774 			Upper 8 bits of the sixth buffer pointer <legal all>
775 */
776 
777 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET                                     0x00000044
778 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB                                        0
779 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB                                        7
780 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK                                       0x000000ff
781 
782 
783 /* Description		RESERVED_17A
784 
785 			<Legal 0>
786 */
787 
788 #define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET                                       0x00000044
789 #define TX_MSDU_EXTENSION_RESERVED_17A_LSB                                          8
790 #define TX_MSDU_EXTENSION_RESERVED_17A_MSB                                          15
791 #define TX_MSDU_EXTENSION_RESERVED_17A_MASK                                         0x0000ff00
792 
793 
794 /* Description		BUF5_LEN
795 
796 			Length of the sixth buffer <legal all>
797 */
798 
799 #define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET                                           0x00000044
800 #define TX_MSDU_EXTENSION_BUF5_LEN_LSB                                              16
801 #define TX_MSDU_EXTENSION_BUF5_LEN_MSB                                              31
802 #define TX_MSDU_EXTENSION_BUF5_LEN_MASK                                             0xffff0000
803 
804 
805 
806 #endif   // TX_MSDU_EXTENSION
807