1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TCL_GSE_CMD_H_ 27 #define _TCL_GSE_CMD_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TCL_GSE_CMD 8 32 33 34 struct tcl_gse_cmd { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t control_buffer_addr_31_0 : 32; // [31:0] 37 uint32_t control_buffer_addr_39_32 : 8, // [7:0] 38 gse_ctrl : 4, // [11:8] 39 gse_sel : 1, // [12:12] 40 status_destination_ring_id : 1, // [13:13] 41 swap : 1, // [14:14] 42 index_search_en : 1, // [15:15] 43 cache_set_num : 4, // [19:16] 44 reserved_1a : 12; // [31:20] 45 uint32_t tcl_cmd_type : 1, // [0:0] 46 reserved_2a : 31; // [31:1] 47 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 48 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 49 uint32_t reserved_5a : 32; // [31:0] 50 uint32_t reserved_6a : 32; // [31:0] 51 uint32_t reserved_7a : 20, // [19:0] 52 ring_id : 8, // [27:20] 53 looping_count : 4; // [31:28] 54 #else 55 uint32_t control_buffer_addr_31_0 : 32; // [31:0] 56 uint32_t reserved_1a : 12, // [31:20] 57 cache_set_num : 4, // [19:16] 58 index_search_en : 1, // [15:15] 59 swap : 1, // [14:14] 60 status_destination_ring_id : 1, // [13:13] 61 gse_sel : 1, // [12:12] 62 gse_ctrl : 4, // [11:8] 63 control_buffer_addr_39_32 : 8; // [7:0] 64 uint32_t reserved_2a : 31, // [31:1] 65 tcl_cmd_type : 1; // [0:0] 66 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 67 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 68 uint32_t reserved_5a : 32; // [31:0] 69 uint32_t reserved_6a : 32; // [31:0] 70 uint32_t looping_count : 4, // [31:28] 71 ring_id : 8, // [27:20] 72 reserved_7a : 20; // [19:0] 73 #endif 74 }; 75 76 77 /* Description CONTROL_BUFFER_ADDR_31_0 78 79 Address (lower 32 bits) of a control buffer containing additional 80 info needed for this command execution. 81 <legal all> 82 */ 83 84 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 85 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 86 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 87 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 88 89 90 /* Description CONTROL_BUFFER_ADDR_39_32 91 92 Address (upper 8 bits) of a control buffer containing additional 93 info needed for this command execution. 94 <legal all> 95 */ 96 97 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 98 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 99 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 100 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 101 102 103 /* Description GSE_CTRL 104 105 GSE control operations. This includes cache operations and 106 table entry statistics read/clear operation. 107 <enum 0 rd_stat> Report or Read statistics 108 <enum 1 srch_dis> Search disable. Report only Hash 109 <enum 2 Wr_bk_single> Write Back single entry 110 <enum 3 wr_bk_all> Write Back entire cache entry 111 <enum 4 inval_single> Invalidate single cache entry 112 <enum 5 inval_all> Invalidate entire cache 113 <enum 6 wr_bk_inval_single> Write back and Invalidate single 114 entry in cache 115 <enum 7 wr_bk_inval_all> write back and invalidate entire 116 cache 117 <enum 8 clr_stat_single> Clear statistics for single entry 118 119 <legal 0-8> 120 Rest of the values reserved. 121 For all single entry control operations (write back, Invalidate 122 or both)Statistics will be reported 123 */ 124 125 #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 126 #define TCL_GSE_CMD_GSE_CTRL_LSB 8 127 #define TCL_GSE_CMD_GSE_CTRL_MSB 11 128 #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 129 130 131 /* Description GSE_SEL 132 133 Bit to select the ASE or FSE to do the operation mention 134 by GSE_ctrl bit 135 0: FSE select 136 1: ASE select 137 */ 138 139 #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 140 #define TCL_GSE_CMD_GSE_SEL_LSB 12 141 #define TCL_GSE_CMD_GSE_SEL_MSB 12 142 #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 143 144 145 /* Description STATUS_DESTINATION_RING_ID 146 147 The TCL status ring to which the GSE status needs to be 148 send. 149 150 <enum 0 tcl_status_0_ring> 151 <enum 1 tcl_status_1_ring> 152 153 <legal all> 154 */ 155 156 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 157 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 158 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 159 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 160 161 162 /* Description SWAP 163 164 Bit to enable byte swapping of contents of buffer 165 <enum 0 Byte_swap_disable > 166 <enum 1 byte_swap_enable > 167 <legal all> 168 */ 169 170 #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 171 #define TCL_GSE_CMD_SWAP_LSB 14 172 #define TCL_GSE_CMD_SWAP_MSB 14 173 #define TCL_GSE_CMD_SWAP_MASK 0x00004000 174 175 176 /* Description INDEX_SEARCH_EN 177 178 When this bit is set to 1 control_buffer_addr[19:0] will 179 be considered as index of the AST or Flow table and GSE 180 commands will be executed accordingly on the entry pointed 181 by the index. 182 This feature is disabled by setting this bit to 0. 183 <enum 0 index_based_cmd_disable> 184 <enum 1 index_based_cmd_enable> 185 186 <legal all> 187 */ 188 189 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 190 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 191 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 192 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 193 194 195 /* Description CACHE_SET_NUM 196 197 Cache set number that should be used to cache the index 198 based search results, for address and flow search. This 199 value should be equal to value of cache_set_num for the 200 index that is issued in TCL_DATA_CMD during search index 201 based ASE or FSE. This field is valid for index based GSE 202 commands 203 <legal all> 204 */ 205 206 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 207 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 208 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 209 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 210 211 212 /* Description RESERVED_1A 213 214 <legal 0> 215 */ 216 217 #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 218 #define TCL_GSE_CMD_RESERVED_1A_LSB 20 219 #define TCL_GSE_CMD_RESERVED_1A_MSB 31 220 #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 221 222 223 /* Description TCL_CMD_TYPE 224 225 This field is used to select the type of TCL Command decriptor 226 that is queued by SW/FW. For 'TCL_GSE_CMD' this has to 227 be 1. 228 <legal 1> 229 */ 230 231 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 232 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 233 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 234 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 235 236 237 /* Description RESERVED_2A 238 239 <legal 0> 240 */ 241 242 #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 243 #define TCL_GSE_CMD_RESERVED_2A_LSB 1 244 #define TCL_GSE_CMD_RESERVED_2A_MSB 31 245 #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe 246 247 248 /* Description CMD_META_DATA_31_0 249 250 Meta data to be returned in the status descriptor 251 <legal all> 252 */ 253 254 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c 255 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 256 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 257 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff 258 259 260 /* Description CMD_META_DATA_63_32 261 262 Meta data to be returned in the status descriptor 263 <legal all> 264 */ 265 266 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 267 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 268 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 269 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff 270 271 272 /* Description RESERVED_5A 273 274 <legal 0> 275 */ 276 277 #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 278 #define TCL_GSE_CMD_RESERVED_5A_LSB 0 279 #define TCL_GSE_CMD_RESERVED_5A_MSB 31 280 #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff 281 282 283 /* Description RESERVED_6A 284 285 <legal 0> 286 */ 287 288 #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 289 #define TCL_GSE_CMD_RESERVED_6A_LSB 0 290 #define TCL_GSE_CMD_RESERVED_6A_MSB 31 291 #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff 292 293 294 /* Description RESERVED_7A 295 296 <legal 0> 297 */ 298 299 #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c 300 #define TCL_GSE_CMD_RESERVED_7A_LSB 0 301 #define TCL_GSE_CMD_RESERVED_7A_MSB 19 302 #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff 303 304 305 /* Description RING_ID 306 307 Helps with debugging when dumping ring contents. 308 <legal all> 309 */ 310 311 #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c 312 #define TCL_GSE_CMD_RING_ID_LSB 20 313 #define TCL_GSE_CMD_RING_ID_MSB 27 314 #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 315 316 317 /* Description LOOPING_COUNT 318 319 A count value that indicates the number of times the producer 320 of entries into the Ring has looped around the ring. 321 At initialization time, this value is set to 0. On the first 322 loop, this value is set to 1. After the max value is reached 323 allowed by the number of bits for this field, the count 324 value continues with 0 again. 325 326 In case SW is the consumer of the ring entries, it can use 327 this field to figure out up to where the producer of entries 328 has created new entries. This eliminates the need to check 329 where the "head pointer' of the ring is located once the 330 SW starts processing an interrupt indicating that new entries 331 have been put into this ring... 332 333 Also note that SW if it wants only needs to look at the 334 LSB bit of this count value. 335 <legal all> 336 */ 337 338 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c 339 #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 340 #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 341 #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 342 343 344 345 #endif // TCL_GSE_CMD 346