1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_
27 #define _TCL_ENTRANCE_FROM_PPE_RING_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8
32 
33 
34 struct tcl_entrance_from_ppe_ring {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t buffer_addr_lo                                          : 32; // [31:0]
37              uint32_t buffer_addr_hi                                          :  8, // [7:0]
38                       drop_prec                                               :  2, // [9:8]
39                       fake_mac_header                                         :  1, // [10:10]
40                       known_ind                                               :  1, // [11:11]
41                       cpu_code_valid                                          :  1, // [12:12]
42                       tunnel_term_ind                                         :  1, // [13:13]
43                       tunnel_type                                             :  1, // [14:14]
44                       wifi_qos_flag                                           :  1, // [15:15]
45                       service_code                                            :  9, // [24:16]
46                       reserved_1b                                             :  1, // [25:25]
47                       int_pri                                                 :  4, // [29:26]
48                       more                                                    :  1, // [30:30]
49                       reserved_1a                                             :  1; // [31:31]
50              uint32_t opaque_lo                                               : 32; // [31:0]
51              uint32_t opaque_hi                                               : 32; // [31:0]
52              uint32_t src_info                                                : 16, // [15:0]
53                       dst_info                                                : 16; // [31:16]
54              uint32_t data_length                                             : 18, // [17:0]
55                       pool_id                                                 :  6, // [23:18]
56                       wifi_qos                                                :  8; // [31:24]
57              uint32_t data_offset                                             : 12, // [11:0]
58                       l4_csum_status                                          :  1, // [12:12]
59                       l3_csum_status                                          :  1, // [13:13]
60                       hash_flag                                               :  2, // [15:14]
61                       hash_value                                              : 16; // [31:16]
62              uint32_t dscp                                                    :  8, // [7:0]
63                       valid_toggle                                            :  1, // [8:8]
64                       pppoe_flag                                              :  1, // [9:9]
65                       svlan_flag                                              :  1, // [10:10]
66                       cvlan_flag                                              :  1, // [11:11]
67                       pid                                                     :  4, // [15:12]
68                       l3_offset                                               :  8, // [23:16]
69                       l4_offset                                               :  8; // [31:24]
70 #else
71              uint32_t buffer_addr_lo                                          : 32; // [31:0]
72              uint32_t reserved_1a                                             :  1, // [31:31]
73                       more                                                    :  1, // [30:30]
74                       int_pri                                                 :  4, // [29:26]
75                       reserved_1b                                             :  1, // [25:25]
76                       service_code                                            :  9, // [24:16]
77                       wifi_qos_flag                                           :  1, // [15:15]
78                       tunnel_type                                             :  1, // [14:14]
79                       tunnel_term_ind                                         :  1, // [13:13]
80                       cpu_code_valid                                          :  1, // [12:12]
81                       known_ind                                               :  1, // [11:11]
82                       fake_mac_header                                         :  1, // [10:10]
83                       drop_prec                                               :  2, // [9:8]
84                       buffer_addr_hi                                          :  8; // [7:0]
85              uint32_t opaque_lo                                               : 32; // [31:0]
86              uint32_t opaque_hi                                               : 32; // [31:0]
87              uint32_t dst_info                                                : 16, // [31:16]
88                       src_info                                                : 16; // [15:0]
89              uint32_t wifi_qos                                                :  8, // [31:24]
90                       pool_id                                                 :  6, // [23:18]
91                       data_length                                             : 18; // [17:0]
92              uint32_t hash_value                                              : 16, // [31:16]
93                       hash_flag                                               :  2, // [15:14]
94                       l3_csum_status                                          :  1, // [13:13]
95                       l4_csum_status                                          :  1, // [12:12]
96                       data_offset                                             : 12; // [11:0]
97              uint32_t l4_offset                                               :  8, // [31:24]
98                       l3_offset                                               :  8, // [23:16]
99                       pid                                                     :  4, // [15:12]
100                       cvlan_flag                                              :  1, // [11:11]
101                       svlan_flag                                              :  1, // [10:10]
102                       pppoe_flag                                              :  1, // [9:9]
103                       valid_toggle                                            :  1, // [8:8]
104                       dscp                                                    :  8; // [7:0]
105 #endif
106 };
107 
108 
109 /* Description		BUFFER_ADDR_LO
110 
111 			Consumer: TCL
112 			Producer: PPE DMA/SW
113 
114 			Lower 32 bits of the buffer address buffer_addr_31_0.
115 
116 			This is the address of the starting point of the buffer
117 			directly from the PPE Rx Fill descriptor. TCL needs to calculate
118 			 the packet data address based on DATA_OFFSET.
119 			<legal all>
120 */
121 
122 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET                            0x00000000
123 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB                               0
124 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB                               31
125 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK                              0xffffffff
126 
127 
128 /* Description		BUFFER_ADDR_HI
129 
130 			Consumer: TCL/TXDMA
131 			Producer: PPE DMA/SW
132 
133 			Higher 8 bits of the buffer address buffer_addr_39_32 (Not
134 			 supported in Alder PPE but could be supported by PPE in
135 			 future). Also see BUFFER_ADDR_LO.
136 			<legal all>
137 */
138 
139 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET                            0x00000004
140 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB                               0
141 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB                               7
142 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK                              0x000000ff
143 
144 
145 /* Description		DROP_PREC
146 
147 			Consumer: TCL/TQM
148 			Producer: Switch Core
149 
150 			Packet drop precedence
151 
152 			Waikiki TCL maps DROP_PREC to field msdu_color in structure
153 			 'TX_MSDU_DETAILS' in  'TQM_ENTRANCE_RING' if the internal
154 			 parameter 'DROP_PREC_ENABLE' is set (see field DST_INFO)
155 			and DROP_PREC is set to a legal value. Otherwise msdu_color
156 			 is set to MSDU_COLORLESS.
157 
158 			<enum 0 PPE_drop_prec_green>
159 			<enum 1 PPE_drop_prec_yellow>
160 			<enum 2 PPE_drop_prec_red>
161 			<legal 0-2>
162 */
163 
164 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET                                 0x00000004
165 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB                                    8
166 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB                                    9
167 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK                                   0x00000300
168 
169 
170 /* Description		FAKE_MAC_HEADER
171 
172 			Consumer: SW
173 			Producer: Switch Core
174 
175 			Indicates the MAC header is fake (Not supported for direct
176 			 switch connect)
177 			0:  No fake MAC header
178 			1:  Fake MAC header
179 			<legal 0>
180 */
181 
182 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET                           0x00000004
183 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB                              10
184 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB                              10
185 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK                             0x00000400
186 
187 
188 /* Description		KNOWN_IND
189 
190 			Consumer: TCL
191 			Producer: Switch Core
192 
193 			Known packet indication (Ignored by Waikiki TCL)
194 			0: packet is unknown flooding.
195 			1: packet is forwarded by any known entry.
196 			<legal all>
197 */
198 
199 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET                                 0x00000004
200 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB                                    11
201 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB                                    11
202 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK                                   0x00000800
203 
204 
205 /* Description		CPU_CODE_VALID
206 
207 			Consumer: SW
208 			Producer: Switch Core
209 
210 			Indicates validity of 'CPU_CODE' (used to indicate the reason
211 			 the packet is sent to the CPU) (Not supported for direct
212 			 switch connect)
213 			0: Invalid
214 			1: Valid
215 			<legal 0>
216 */
217 
218 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET                            0x00000004
219 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB                               12
220 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB                               12
221 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK                              0x00001000
222 
223 
224 /* Description		TUNNEL_TERM_IND
225 
226 			Consumer: TCL
227 			Producer: Switch Core
228 
229 			Tunnel termination indication (Ignored by Waikiki TCL)
230 			0: packet is not decapsulated
231 			1: packet is decapsulated
232 			<legal all>
233 */
234 
235 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET                           0x00000004
236 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB                              13
237 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB                              13
238 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK                             0x00002000
239 
240 
241 /* Description		TUNNEL_TYPE
242 
243 			Consumer: TCL
244 			Producer: Switch Core
245 
246 			Tunnel Type (Ignored by Waikiki TCL)
247 			0: Layer 2 tunnel
248 			1: Layer 3 tunnel
249 			<legal all>
250 */
251 
252 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET                               0x00000004
253 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB                                  14
254 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB                                  14
255 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK                                 0x00004000
256 
257 
258 /* Description		WIFI_QOS_FLAG
259 
260 			Consumer: TCL
261 			Producer: Switch Core
262 
263 			Wi-Fi QoS Flag
264 			0: If WIFI_QOS[7] is set, WIFI_QOS[3:1] provides a 3-bit
265 			 HLOS_TID value and HLOS_TID_overwrite is enabled, else
266 			there is no overwrite.
267 			1: WIFI_QOS[5:0] provides a 6-bit "flow pointer override"
268 			value by using:
269 			who_classify_info_sel = WIFI_QOS[5:4],
270 			HLOS_TID = WIFI_QOS[3:1],
271 			flow_override = WIFI_QOS[0],
272 			and HLOS_TID_overwrite and flow_override_enable are set.
273 
274 
275 			Also see field INT_PRI for another way to enable HLOS_TID_overwrite.
276 
277 			<legal all>
278 */
279 
280 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET                             0x00000004
281 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB                                15
282 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB                                15
283 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK                               0x00008000
284 
285 
286 /* Description		SERVICE_CODE
287 
288 			Consumer: TCL
289 			Producer: Switch Core
290 
291 			Opaque service code between engines (Ignored by Waikiki
292 			TCL)
293 			0: Indicates the end of service path
294 			<legal all>
295 */
296 
297 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET                              0x00000004
298 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB                                 16
299 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB                                 24
300 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK                                0x01ff0000
301 
302 
303 /* Description		RESERVED_1B
304 
305 			<legal 0, 1>
306 */
307 
308 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET                               0x00000004
309 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB                                  25
310 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB                                  25
311 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK                                 0x02000000
312 
313 
314 /* Description		INT_PRI
315 
316 			Consumer: TCL
317 			Producer: Switch Core
318 
319 			Internal/User Priority (Ignored by Waikiki TCL)
320 
321 			Waikiki TCL maps INT_PRI to HLOS_TID using an internal mapping
322 			 table if the internal parameter 'USE_PPE_INT_PRI_FOR_TID'
323 			is set (see field DST_INFO) and WIFI_QOS_FLAG is unset and
324 			 WIFI_QOS[7] is unset.
325 			<legal all>
326 */
327 
328 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET                                   0x00000004
329 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB                                      26
330 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB                                      29
331 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK                                     0x3c000000
332 
333 
334 /* Description		MORE
335 
336 			Consumer: TCL
337 			Producer: PPE DMA
338 
339 			0: The last segment of packet
340 			1: More segments to follow, indicating scatter/gather (Not
341 			 supported in Waikiki TCL)
342 			<legal all>
343 */
344 
345 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET                                      0x00000004
346 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB                                         30
347 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB                                         30
348 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK                                        0x40000000
349 
350 
351 /* Description		RESERVED_1A
352 
353 			<legal 0>
354 */
355 
356 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET                               0x00000004
357 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB                                  31
358 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB                                  31
359 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK                                 0x80000000
360 
361 
362 /* Description		OPAQUE_LO
363 
364 			Consumer: TCL/WBM/SW
365 			Producer: PPE DMA/SW
366 
367 			Lower 32 bits of opaque SW value
368 
369 			OPAQUE_LO[19:0] are used for Sw_buffer_cookie with OPAQUE_LO[31:20]
370 			ignored, for direct switch connect.
371 			<legal all>
372 */
373 
374 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET                                 0x00000008
375 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB                                    0
376 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB                                    31
377 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK                                   0xffffffff
378 
379 
380 /* Description		OPAQUE_HI
381 
382 			Consumer: SW
383 			Producer: PPE DMA/SW
384 
385 			Higher 32 bits of opaque SW value, ignored completely for
386 			 direct switch connect
387 			<legal all>
388 */
389 
390 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET                                 0x0000000c
391 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB                                    0
392 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB                                    31
393 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK                                   0xffffffff
394 
395 
396 /* Description		SRC_INFO
397 
398 			Consumer: TCL
399 			Producer: Switch Core
400 
401 			Source port: SRC_INFO[15:12] = 'b0010, SRC_INFO[11:0] is
402 			 the PORT_ID (Ignored by Waikiki TCL).
403 			See DST_INFO for PORT_ID values.
404 			<legal 8192-8447>
405 */
406 
407 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET                                  0x00000010
408 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB                                     0
409 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB                                     15
410 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK                                    0x0000ffff
411 
412 
413 /* Description		DST_INFO
414 
415 			Consumer: TCL
416 			Producer: Switch Core
417 
418 			Destination port or next hop information
419 
420 			DST_INFO[15:12] = 'b0000 indicates invalid information.
421 			If DST_INFO[15:12] = 'b0001, DST_INFO[11:0] is the next
422 			hop index (Not supported for direct switch connect).
423 			If DST_INFO[15:12] = 'b0010, DST_INFO[11:0] is the PORT_ID,
424 			which Waikiki TCL can process.
425 			If DST_INFO[15:12] = 'b0011, DST_INFO[11:0] is the destination
426 			 port bitmap (Not supported for direct switch connect).
427 
428 			PORT_ID:
429 			0-31 indicates a physical Ethernet port.
430 			32-63 indicates a link aggregation group (LAG) of ports (Not
431 			 supported for direct switch connect).
432 			64-255 indicates a virtual port, which Waikiki TCL maps
433 			to Bank_id, PMAC_ID, vdev_id, To_FW and Search_index. Waikiki
434 			 TCL also maps this to internal parameters 'USE_PPE_INT_PRI_FOR_TID'
435 			and 'DROP_PREC_ENABLE' (see fields INT_PRI and DROP_PREC).
436 
437 			Other values are reserved.
438 			<legal 0-8447,12288-16383>
439 */
440 
441 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET                                  0x00000010
442 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB                                     16
443 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB                                     31
444 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK                                    0xffff0000
445 
446 
447 /* Description		DATA_LENGTH
448 
449 			Consumer: TCL/TXDMA
450 			Producer: PPE DMA
451 
452 			Length of valid packet data in the current buffer in bytes
453 			 (Bits [17:16] not supported in Alder PPE and bits [17:14]
454 			not supported in Waikiki)
455 			<legal all>
456 */
457 
458 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET                               0x00000014
459 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB                                  0
460 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB                                  17
461 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK                                 0x0003ffff
462 
463 
464 /* Description		POOL_ID
465 
466 			Consumer: TCL/SW
467 			Producer: PPE DMA/SW
468 
469 			To be used for hardware buffer management (Not supported
470 			 in Alder PPE and ignored by Waikiki TCL)
471 
472 			SW must ensure 1:1 mapping between PPE Rx Fill and PPE Rx
473 			 completion descriptors.
474 			<legal all>
475 */
476 
477 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET                                   0x00000014
478 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB                                      18
479 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB                                      23
480 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK                                     0x00fc0000
481 
482 
483 /* Description		WIFI_QOS
484 
485 			Consumer: TCL
486 			Producer: Switch Core
487 
488 			Wi-Fi QoS Value
489 
490 			Waikiki TCL maps as follows:
491 			who_classify_info_sel = WIFI_QOS[5:4] if WIFI_QOS_FLAG set
492 
493 			HLOS_TID = WIFI_QOS[3:1] if HLOS_TID_overwrite enabled
494 			flow_override = WIFI_QOS [0] if WIFI_QOS_FLAG set
495 			flow_override_enable = WIFI_QOS_FLAG
496 			HLOS_TID_overwrite = WIFI_QOS_FLAG || WIFI_QOS[7]
497 
498 			WIFI_QOS[6] is ignored by Waikiki TCL.
499 
500 			Also see field INT_PRI for another way to enable HLOS_TID_overwrite.
501 
502 			<legal all>
503 */
504 
505 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET                                  0x00000014
506 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB                                     24
507 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB                                     31
508 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK                                    0xff000000
509 
510 
511 /* Description		DATA_OFFSET
512 
513 			Consumer: TCL
514 			Producer: PPE DMA
515 
516 			Offset to the packet data from the buffer address
517 			<legal all>
518 */
519 
520 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET                               0x00000018
521 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB                                  0
522 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB                                  11
523 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK                                 0x00000fff
524 
525 
526 /* Description		L4_CSUM_STATUS
527 
528 			Consumer: TCL
529 			Producer: PPE DMA/Switch Core
530 
531 			Layer 4 checksum verification result (Ignored by Waikiki
532 			 TCL)
533 			0: Unknown or invalid
534 			1: Valid
535 			The default value is 0. Only when PPE DMA performs the checksum
536 			 calculation and the result is correct, is this bit set.
537 
538 			<legal all>
539 */
540 
541 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET                            0x00000018
542 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB                               12
543 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB                               12
544 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK                              0x00001000
545 
546 
547 /* Description		L3_CSUM_STATUS
548 
549 			Consumer: TCL
550 			Producer: PPE DMA/Switch Core
551 
552 			Layer 3 checksum verification result (Ignored by Waikiki
553 			 TCL)
554 			0: Unknown or invalid
555 			1: Valid
556 			The default value is 0. Only when PPE DMA performs the checksum
557 			 calculation and the result is correct, is this bit set.
558 
559 			<legal all>
560 */
561 
562 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET                            0x00000018
563 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB                               13
564 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB                               13
565 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK                              0x00002000
566 
567 
568 /* Description		HASH_FLAG
569 
570 			Consumer: SW
571 			Producer: Switch Core
572 
573 			Hash type (Ignored by Waikiki TCL)
574 			00: Hash invalid
575 			01: 5-tuple hash
576 			10: 3-tuple hash
577 			11: Reserved
578 			<legal 0-2>
579 */
580 
581 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET                                 0x00000018
582 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB                                    14
583 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB                                    15
584 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK                                   0x0000c000
585 
586 
587 /* Description		HASH_VALUE
588 
589 			Consumer: SW
590 			Producer: Switch Core
591 
592 			Hash value (Ignored by Waikiki TCL)
593 			<legal all>
594 */
595 
596 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET                                0x00000018
597 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB                                   16
598 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB                                   31
599 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK                                  0xffff0000
600 
601 
602 /* Description		DSCP
603 
604 			Consumer: TCL
605 			Producer: PPE DMA/Switch Core
606 
607 			Differential Services Code Point value (Ignored by Waikiki
608 			 TCL)
609 			<legal all>
610 */
611 
612 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET                                      0x0000001c
613 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB                                         0
614 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB                                         7
615 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK                                        0x000000ff
616 
617 
618 /* Description		VALID_TOGGLE
619 
620 			Consumer: TCL
621 			Producer: PPE DMA
622 
623 			Toggle bit to indicate the validity of the descriptor (Ignored
624 			 by Waikiki TCL).
625 			The value is toggled when the producer pointer wraps around.
626 
627 			<legal all>
628 */
629 
630 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET                              0x0000001c
631 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB                                 8
632 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB                                 8
633 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK                                0x00000100
634 
635 
636 /* Description		PPPOE_FLAG
637 
638 			Consumer: TCL
639 			Producer: Switch Core
640 
641 			Indicates a PPPoE packet (Ignored by Waikiki TCL)
642 			0: No PPPoE header
643 			1: PPPoE header exists
644 			<legal all>
645 */
646 
647 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET                                0x0000001c
648 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB                                   9
649 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB                                   9
650 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK                                  0x00000200
651 
652 
653 /* Description		SVLAN_FLAG
654 
655 			Consumer: TCL
656 			Producer: PPE DMA/Switch Core
657 
658 			Indicates the existence of S-VLAN tag (Ignored by Waikiki
659 			 TCL)
660 			0: No S-VLAN
661 			1: S-VLAN exists, including priority
662 			<legal all>
663 */
664 
665 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET                                0x0000001c
666 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB                                   10
667 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB                                   10
668 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK                                  0x00000400
669 
670 
671 /* Description		CVLAN_FLAG
672 
673 			Consumer: TCL
674 			Producer: PPE DMA/Switch Core
675 
676 			Indicates the existence of C-VLAN tag (Ignored by Waikiki
677 			 TCL)
678 			0: No C-VLAN
679 			1: C-VLAN exists, including priority
680 			<legal all>
681 */
682 
683 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET                                0x0000001c
684 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB                                   11
685 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB                                   11
686 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK                                  0x00000800
687 
688 
689 /* Description		PID
690 
691 			Consumer: TCL
692 			Producer: Switch Core
693 
694 			Protocol ID, indicating the protocol type of the packet (Ignored
695 			 by Waikiki TCL).
696 			0: IPv4 (no supported L4)
697 			1: TCP over IPv4
698 			2: UDP over IPv4
699 			3: UDP-Lite over IPv4
700 			4: IPv6 (no supported L4)
701 			5: TCP over IPv6
702 			6: UDP over IPv6
703 			7: UDP-Lite over IPv6
704 			8: Non-IP
705 			Other values are reserved
706 			<legal 0-8>
707 */
708 
709 #define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET                                       0x0000001c
710 #define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB                                          12
711 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB                                          15
712 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK                                         0x0000f000
713 
714 
715 /* Description		L3_OFFSET
716 
717 			Consumer: TCL
718 			Producer: PPE DMA
719 
720 			Layer 3 header offset from DATA_OFFSET (Ignored by Waikiki
721 			 TCL)
722 			<legal all>
723 */
724 
725 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET                                 0x0000001c
726 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB                                    16
727 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB                                    23
728 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK                                   0x00ff0000
729 
730 
731 /* Description		L4_OFFSET
732 
733 			Consumer: TCL
734 			Producer: PPE DMA
735 
736 			Layer 4 header offset from DATA_OFFSET (Ignored by Waikiki
737 			 TCL)
738 			<legal all>
739 */
740 
741 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET                                 0x0000001c
742 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB                                    24
743 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB                                    31
744 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK                                   0xff000000
745 
746 
747 
748 #endif   // TCL_ENTRANCE_FROM_PPE_RING
749