1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_PPDU_END_USER_STATS_H_ 19 #define _RX_PPDU_END_USER_STATS_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #include "rx_rxpcu_classification_overview.h" 24 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 25 26 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 27 28 29 struct rx_ppdu_end_user_stats { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 struct rx_rxpcu_classification_overview rxpcu_classification_details; 32 uint32_t sta_full_aid : 13, // [12:0] 33 mcs : 4, // [16:13] 34 nss : 3, // [19:17] 35 expected_response_ack_or_ba : 1, // [20:20] 36 reserved_1a : 11; // [31:21] 37 uint32_t sw_peer_id : 16, // [15:0] 38 mpdu_cnt_fcs_err : 11, // [26:16] 39 sw2rxdma0_buf_source_used : 1, // [27:27] 40 fw2rxdma_pmac0_buf_source_used : 1, // [28:28] 41 sw2rxdma1_buf_source_used : 1, // [29:29] 42 sw2rxdma_exception_buf_source_used : 1, // [30:30] 43 fw2rxdma_pmac1_buf_source_used : 1; // [31:31] 44 uint32_t mpdu_cnt_fcs_ok : 11, // [10:0] 45 frame_control_info_valid : 1, // [11:11] 46 qos_control_info_valid : 1, // [12:12] 47 ht_control_info_valid : 1, // [13:13] 48 data_sequence_control_info_valid : 1, // [14:14] 49 ht_control_info_null_valid : 1, // [15:15] 50 rxdma2fw_pmac1_ring_used : 1, // [16:16] 51 rxdma2reo_ring_used : 1, // [17:17] 52 rxdma2fw_pmac0_ring_used : 1, // [18:18] 53 rxdma2sw_ring_used : 1, // [19:19] 54 rxdma_release_ring_used : 1, // [20:20] 55 ht_control_field_pkt_type : 4, // [24:21] 56 rxdma2reo_remote0_ring_used : 1, // [25:25] 57 rxdma2reo_remote1_ring_used : 1, // [26:26] 58 reserved_3b : 5; // [31:27] 59 uint32_t ast_index : 16, // [15:0] 60 frame_control_field : 16; // [31:16] 61 uint32_t first_data_seq_ctrl : 16, // [15:0] 62 qos_control_field : 16; // [31:16] 63 uint32_t ht_control_field : 32; // [31:0] 64 uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] 65 uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] 66 uint32_t udp_msdu_count : 16, // [15:0] 67 tcp_msdu_count : 16; // [31:16] 68 uint32_t other_msdu_count : 16, // [15:0] 69 tcp_ack_msdu_count : 16; // [31:16] 70 uint32_t sw_response_reference_ptr : 32; // [31:0] 71 uint32_t received_qos_data_tid_bitmap : 16, // [15:0] 72 received_qos_data_tid_eosp_bitmap : 16; // [31:16] 73 uint32_t qosctrl_15_8_tid0 : 8, // [7:0] 74 qosctrl_15_8_tid1 : 8, // [15:8] 75 qosctrl_15_8_tid2 : 8, // [23:16] 76 qosctrl_15_8_tid3 : 8; // [31:24] 77 uint32_t qosctrl_15_8_tid4 : 8, // [7:0] 78 qosctrl_15_8_tid5 : 8, // [15:8] 79 qosctrl_15_8_tid6 : 8, // [23:16] 80 qosctrl_15_8_tid7 : 8; // [31:24] 81 uint32_t qosctrl_15_8_tid8 : 8, // [7:0] 82 qosctrl_15_8_tid9 : 8, // [15:8] 83 qosctrl_15_8_tid10 : 8, // [23:16] 84 qosctrl_15_8_tid11 : 8; // [31:24] 85 uint32_t qosctrl_15_8_tid12 : 8, // [7:0] 86 qosctrl_15_8_tid13 : 8, // [15:8] 87 qosctrl_15_8_tid14 : 8, // [23:16] 88 qosctrl_15_8_tid15 : 8; // [31:24] 89 uint32_t mpdu_ok_byte_count : 25, // [24:0] 90 ampdu_delim_ok_count_6_0 : 7; // [31:25] 91 uint32_t ampdu_delim_err_count : 25, // [24:0] 92 ampdu_delim_ok_count_13_7 : 7; // [31:25] 93 uint32_t mpdu_err_byte_count : 25, // [24:0] 94 ampdu_delim_ok_count_20_14 : 7; // [31:25] 95 uint32_t non_consecutive_delimiter_err : 16, // [15:0] 96 retried_msdu_count : 16; // [31:16] 97 uint32_t ht_control_null_field : 32; // [31:0] 98 uint32_t sw_response_reference_ptr_ext : 32; // [31:0] 99 uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 100 frame_control_info_null_valid : 1, // [1:1] 101 frame_control_field_null : 16, // [17:2] 102 retried_mpdu_count : 11, // [28:18] 103 reserved_23a : 3; // [31:29] 104 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 105 sw_frame_group_id : 7, // [8:2] 106 reserved_24a : 4, // [12:9] 107 frame_control_info_mgmt_ctrl_valid : 1, // [13:13] 108 mac_addr_ad2_valid : 1, // [14:14] 109 mcast_bcast : 1, // [15:15] 110 frame_control_field_mgmt_ctrl : 16; // [31:16] 111 uint32_t user_ppdu_len : 24, // [23:0] 112 reserved_25a : 8; // [31:24] 113 uint32_t mac_addr_ad2_31_0 : 32; // [31:0] 114 uint32_t mac_addr_ad2_47_32 : 16, // [15:0] 115 amsdu_msdu_count : 16; // [31:16] 116 uint32_t non_amsdu_msdu_count : 16, // [15:0] 117 ucast_msdu_count : 16; // [31:16] 118 uint32_t bcast_msdu_count : 16, // [15:0] 119 mcast_bcast_msdu_count : 16; // [31:16] 120 #else 121 struct rx_rxpcu_classification_overview rxpcu_classification_details; 122 uint32_t reserved_1a : 11, // [31:21] 123 expected_response_ack_or_ba : 1, // [20:20] 124 nss : 3, // [19:17] 125 mcs : 4, // [16:13] 126 sta_full_aid : 13; // [12:0] 127 uint32_t fw2rxdma_pmac1_buf_source_used : 1, // [31:31] 128 sw2rxdma_exception_buf_source_used : 1, // [30:30] 129 sw2rxdma1_buf_source_used : 1, // [29:29] 130 fw2rxdma_pmac0_buf_source_used : 1, // [28:28] 131 sw2rxdma0_buf_source_used : 1, // [27:27] 132 mpdu_cnt_fcs_err : 11, // [26:16] 133 sw_peer_id : 16; // [15:0] 134 uint32_t reserved_3b : 5, // [31:27] 135 rxdma2reo_remote1_ring_used : 1, // [26:26] 136 rxdma2reo_remote0_ring_used : 1, // [25:25] 137 ht_control_field_pkt_type : 4, // [24:21] 138 rxdma_release_ring_used : 1, // [20:20] 139 rxdma2sw_ring_used : 1, // [19:19] 140 rxdma2fw_pmac0_ring_used : 1, // [18:18] 141 rxdma2reo_ring_used : 1, // [17:17] 142 rxdma2fw_pmac1_ring_used : 1, // [16:16] 143 ht_control_info_null_valid : 1, // [15:15] 144 data_sequence_control_info_valid : 1, // [14:14] 145 ht_control_info_valid : 1, // [13:13] 146 qos_control_info_valid : 1, // [12:12] 147 frame_control_info_valid : 1, // [11:11] 148 mpdu_cnt_fcs_ok : 11; // [10:0] 149 uint32_t frame_control_field : 16, // [31:16] 150 ast_index : 16; // [15:0] 151 uint32_t qos_control_field : 16, // [31:16] 152 first_data_seq_ctrl : 16; // [15:0] 153 uint32_t ht_control_field : 32; // [31:0] 154 uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] 155 uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] 156 uint32_t tcp_msdu_count : 16, // [31:16] 157 udp_msdu_count : 16; // [15:0] 158 uint32_t tcp_ack_msdu_count : 16, // [31:16] 159 other_msdu_count : 16; // [15:0] 160 uint32_t sw_response_reference_ptr : 32; // [31:0] 161 uint32_t received_qos_data_tid_eosp_bitmap : 16, // [31:16] 162 received_qos_data_tid_bitmap : 16; // [15:0] 163 uint32_t qosctrl_15_8_tid3 : 8, // [31:24] 164 qosctrl_15_8_tid2 : 8, // [23:16] 165 qosctrl_15_8_tid1 : 8, // [15:8] 166 qosctrl_15_8_tid0 : 8; // [7:0] 167 uint32_t qosctrl_15_8_tid7 : 8, // [31:24] 168 qosctrl_15_8_tid6 : 8, // [23:16] 169 qosctrl_15_8_tid5 : 8, // [15:8] 170 qosctrl_15_8_tid4 : 8; // [7:0] 171 uint32_t qosctrl_15_8_tid11 : 8, // [31:24] 172 qosctrl_15_8_tid10 : 8, // [23:16] 173 qosctrl_15_8_tid9 : 8, // [15:8] 174 qosctrl_15_8_tid8 : 8; // [7:0] 175 uint32_t qosctrl_15_8_tid15 : 8, // [31:24] 176 qosctrl_15_8_tid14 : 8, // [23:16] 177 qosctrl_15_8_tid13 : 8, // [15:8] 178 qosctrl_15_8_tid12 : 8; // [7:0] 179 uint32_t ampdu_delim_ok_count_6_0 : 7, // [31:25] 180 mpdu_ok_byte_count : 25; // [24:0] 181 uint32_t ampdu_delim_ok_count_13_7 : 7, // [31:25] 182 ampdu_delim_err_count : 25; // [24:0] 183 uint32_t ampdu_delim_ok_count_20_14 : 7, // [31:25] 184 mpdu_err_byte_count : 25; // [24:0] 185 uint32_t retried_msdu_count : 16, // [31:16] 186 non_consecutive_delimiter_err : 16; // [15:0] 187 uint32_t ht_control_null_field : 32; // [31:0] 188 uint32_t sw_response_reference_ptr_ext : 32; // [31:0] 189 uint32_t reserved_23a : 3, // [31:29] 190 retried_mpdu_count : 11, // [28:18] 191 frame_control_field_null : 16, // [17:2] 192 frame_control_info_null_valid : 1, // [1:1] 193 corrupted_due_to_fifo_delay : 1; // [0:0] 194 uint32_t frame_control_field_mgmt_ctrl : 16, // [31:16] 195 mcast_bcast : 1, // [15:15] 196 mac_addr_ad2_valid : 1, // [14:14] 197 frame_control_info_mgmt_ctrl_valid : 1, // [13:13] 198 reserved_24a : 4, // [12:9] 199 sw_frame_group_id : 7, // [8:2] 200 rxpcu_mpdu_filter_in_category : 2; // [1:0] 201 uint32_t reserved_25a : 8, // [31:24] 202 user_ppdu_len : 24; // [23:0] 203 uint32_t mac_addr_ad2_31_0 : 32; // [31:0] 204 uint32_t amsdu_msdu_count : 16, // [31:16] 205 mac_addr_ad2_47_32 : 16; // [15:0] 206 uint32_t ucast_msdu_count : 16, // [31:16] 207 non_amsdu_msdu_count : 16; // [15:0] 208 uint32_t mcast_bcast_msdu_count : 16, // [31:16] 209 bcast_msdu_count : 16; // [15:0] 210 #endif 211 }; 212 213 214 /* Description RXPCU_CLASSIFICATION_DETAILS 215 216 Details related to what RXPCU classification types of MPDUs 217 have been received 218 */ 219 220 221 /* Description FILTER_PASS_MPDUS 222 223 When set, at least one Filter Pass MPDU has been received. 224 FCS might or might not have been passing. 225 226 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 227 this field is the "OR of all the users. 228 <legal all> 229 */ 230 231 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 232 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 233 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 234 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 235 236 237 /* Description FILTER_PASS_MPDUS_FCS_OK 238 239 When set, at least one Filter Pass MPDU has been received 240 that has a correct FCS. 241 242 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 243 this field is the "OR of all the users. 244 245 <legal all> 246 */ 247 248 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 249 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 250 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 251 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 252 253 254 /* Description MONITOR_DIRECT_MPDUS 255 256 When set, at least one Monitor Direct MPDU has been received. 257 FCS might or might not have been passing 258 259 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 260 this field is the "OR of all the users. 261 <legal all> 262 */ 263 264 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 265 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 266 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 267 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 268 269 270 /* Description MONITOR_DIRECT_MPDUS_FCS_OK 271 272 When set, at least one Monitor Direct MPDU has been received 273 that has a correct FCS. 274 275 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 276 this field is the "OR of all the users. 277 278 <legal all> 279 */ 280 281 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 282 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 283 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 284 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 285 286 287 /* Description MONITOR_OTHER_MPDUS 288 289 When set, at least one Monitor Direct MPDU has been received. 290 FCS might or might not have been passing. 291 292 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 293 this field is the "OR of all the users. 294 <legal all> 295 */ 296 297 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 298 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 299 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 300 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 301 302 303 /* Description MONITOR_OTHER_MPDUS_FCS_OK 304 305 When set, at least one Monitor Direct MPDU has been received 306 that has a correct FCS. 307 308 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 309 this field is the "OR of all the users. 310 <legal all> 311 */ 312 313 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 314 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 315 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 316 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 317 318 319 /* Description PHYRX_ABORT_RECEIVED 320 321 When set, PPDU reception was aborted by the PHY 322 <legal all> 323 */ 324 325 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 326 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 327 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 328 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 329 330 331 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS 332 333 When set, at least one 'Filter Pass Monitor Override' MPDU 334 has been received. FCS might or might not have been passing. 335 336 337 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 338 this field is the "OR of all the users. 339 <legal all> 340 */ 341 342 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 343 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 344 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 345 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 346 347 348 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK 349 350 When set, at least one 'Filter Pass Monitor Override' MPDU 351 has been received that has a correct FCS. 352 353 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 354 this field is the "OR of all the users. 355 356 <legal all> 357 */ 358 359 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 360 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 361 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 362 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 363 364 365 /* Description RESERVED_0 366 367 <legal 0> 368 */ 369 370 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 371 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 372 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 373 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 374 375 376 /* Description PHY_PPDU_ID 377 378 A ppdu counter value that PHY increments for every PPDU 379 received. The counter value wraps around 380 <legal all> 381 */ 382 383 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 384 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 385 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 386 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 387 388 389 /* Description STA_FULL_AID 390 391 Consumer: FW 392 Producer: RXPCU 393 394 The full AID of this station. 395 396 <legal all> 397 */ 398 399 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 400 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 401 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 402 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 403 404 405 /* Description MCS 406 407 MCS of the received frame 408 409 For details, refer to MCS_TYPE description 410 Note: This is "rate" in case of 11a/11b 411 412 <legal all> 413 */ 414 415 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 416 #define RX_PPDU_END_USER_STATS_MCS_LSB 45 417 #define RX_PPDU_END_USER_STATS_MCS_MSB 48 418 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 419 420 421 /* Description NSS 422 423 Number of spatial streams. 424 425 NOTE: RXPCU derives this from the 'Mimo_ss_bitmap' 426 427 <enum 0 1_spatial_stream>Single spatial stream 428 <enum 1 2_spatial_streams>2 spatial streams 429 <enum 2 3_spatial_streams>3 spatial streams 430 <enum 3 4_spatial_streams>4 spatial streams 431 <enum 4 5_spatial_streams>5 spatial streams 432 <enum 5 6_spatial_streams>6 spatial streams 433 <enum 6 7_spatial_streams>7 spatial streams 434 <enum 7 8_spatial_streams>8 spatial streams 435 */ 436 437 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 438 #define RX_PPDU_END_USER_STATS_NSS_LSB 49 439 #define RX_PPDU_END_USER_STATS_NSS_MSB 51 440 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 441 442 443 /* Description EXPECTED_RESPONSE_ACK_OR_BA 444 445 When set, it indicates an Ack or BA matching 'EXPECTED_RESPONSE' 446 from TXPCU 447 */ 448 449 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 450 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 451 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 452 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 453 454 455 /* Description RESERVED_1A 456 457 <legal 0> 458 */ 459 460 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 461 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 462 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 463 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 464 465 466 /* Description SW_PEER_ID 467 468 This field indicates a unique peer identifier, set from 469 the field 'sw_peer_id' in the AST entry corresponding to 470 this MPDU. It is provided by RXPCU. 471 A value of 0xFFFF indicates no AST entry was found or no 472 AST search was performed. 473 <legal all> 474 */ 475 476 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 477 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 478 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 479 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff 480 481 482 /* Description MPDU_CNT_FCS_ERR 483 484 The number of MPDUs received from this STA in this PPDU 485 with FCS errors 486 <legal all> 487 */ 488 489 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 490 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 491 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 492 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 493 494 495 /* Description SW2RXDMA0_BUF_SOURCE_USED 496 497 Field filled in by RXDMA 498 499 When set, RXDMA has used the sw2rxdma0 buffer ring as source 500 for at least one of the frames in this PPDU. 501 */ 502 503 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 504 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 505 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 506 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 507 508 509 /* Description FW2RXDMA_PMAC0_BUF_SOURCE_USED 510 511 Field filled in by RXDMA 512 513 When set, RXDMA has used the fw2rxdma buffer ring for PMAC0 514 as source for at least one of the frames in this PPDU. 515 */ 516 517 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 518 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 519 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 520 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 521 522 523 /* Description SW2RXDMA1_BUF_SOURCE_USED 524 525 Field filled in by RXDMA 526 527 When set, RXDMA has used the sw2rxdma1 buffer ring as source 528 for at least one of the frames in this PPDU. 529 */ 530 531 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 532 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 533 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 534 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 535 536 537 /* Description SW2RXDMA_EXCEPTION_BUF_SOURCE_USED 538 539 Field filled in by RXDMA 540 541 When set, RXDMA has used the sw2rxdma_exception buffer ring 542 as source for at least one of the frames in this PPDU. 543 */ 544 545 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 546 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 547 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 548 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 549 550 551 /* Description FW2RXDMA_PMAC1_BUF_SOURCE_USED 552 553 Field filled in by RXDMA 554 555 When set, RXDMA has used the fw2rxdma buffer ring for PMAC1 556 as source for at least one of the frames in this PPDU. 557 */ 558 559 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 560 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 561 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 562 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 563 564 565 /* Description MPDU_CNT_FCS_OK 566 567 The number of MPDUs received from this STA in this PPDU 568 with correct FCS 569 <legal all> 570 */ 571 572 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 573 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 574 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 575 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 576 577 578 /* Description FRAME_CONTROL_INFO_VALID 579 580 When set, the frame_control_info field contains valid information 581 582 <legal all> 583 */ 584 585 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 586 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 587 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 588 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 589 590 591 /* Description QOS_CONTROL_INFO_VALID 592 593 When set, the QoS_control_info field contains valid information 594 595 <legal all> 596 */ 597 598 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 599 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 600 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 601 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 602 603 604 /* Description HT_CONTROL_INFO_VALID 605 606 When set, the HT_control_field contains valid information 607 608 <legal all> 609 */ 610 611 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 612 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 613 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 614 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 615 616 617 /* Description DATA_SEQUENCE_CONTROL_INFO_VALID 618 619 When set, the First_data_seq_ctrl field contains valid information 620 621 <legal all> 622 */ 623 624 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 625 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 626 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 627 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 628 629 630 /* Description HT_CONTROL_INFO_NULL_VALID 631 632 When set, the HT_control_NULL_field contains valid information 633 634 <legal all> 635 */ 636 637 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 638 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 639 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 640 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 641 642 643 /* Description RXDMA2FW_PMAC1_RING_USED 644 645 Field filled in by RXDMA 646 647 Set when at least one frame during this PPDU got pushed 648 to this ring by RXDMA 649 */ 650 651 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 652 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 653 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 654 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 655 656 657 /* Description RXDMA2REO_RING_USED 658 659 Field filled in by RXDMA 660 661 Set when at least one frame during this PPDU got pushed 662 to this ring by RXDMA 663 */ 664 665 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 666 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 667 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 668 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 669 670 671 /* Description RXDMA2FW_PMAC0_RING_USED 672 673 Field filled in by RXDMA 674 675 Set when at least one frame during this PPDU got pushed 676 to this ring by RXDMA 677 */ 678 679 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 680 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 681 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 682 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 683 684 685 /* Description RXDMA2SW_RING_USED 686 687 Field filled in by RXDMA 688 689 Set when at least one frame during this PPDU got pushed 690 to this ring by RXDMA 691 */ 692 693 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 694 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 695 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 696 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 697 698 699 /* Description RXDMA_RELEASE_RING_USED 700 701 Field filled in by RXDMA 702 703 Set when at least one frame during this PPDU got pushed 704 to this ring by RXDMA 705 */ 706 707 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 708 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 709 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 710 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 711 712 713 /* Description HT_CONTROL_FIELD_PKT_TYPE 714 715 Field only valid when HT_control_info_valid or HT_control_info_NULL_valid 716 is set. 717 718 Indicates what the PHY receive type was for receiving this 719 frame. Can help determine if the HT_CONTROL field shall 720 be interpreted as HT/VHT or HE. 721 722 NOTE: later on in the 11ax IEEE spec a bit within the HT 723 control field was introduced that explicitly indicated 724 how to interpret the HT control field.... As HT, VHT, or 725 HE. 726 727 <enum 0 dot11a>802.11a PPDU type 728 <enum 1 dot11b>802.11b PPDU type 729 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 730 <enum 3 dot11ac>802.11ac PPDU type 731 <enum 4 dot11ax>802.11ax PPDU type 732 <enum 5 dot11ba>802.11ba (WUR) PPDU type 733 <enum 6 dot11be>802.11be PPDU type 734 <enum 7 dot11az>802.11az (ranging) PPDU type 735 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 736 & aborted) 737 */ 738 739 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 740 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 741 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 742 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 743 744 745 /* Description RXDMA2REO_REMOTE0_RING_USED 746 747 Field filled in by RXDMA 748 749 Set when at least one frame during this PPDU got pushed 750 to this ring by RXDMA 751 */ 752 753 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 754 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 755 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 756 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 757 758 759 /* Description RXDMA2REO_REMOTE1_RING_USED 760 761 Field filled in by RXDMA 762 763 Set when at least one frame during this PPDU got pushed 764 to this ring by RXDMA 765 */ 766 767 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 768 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 769 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 770 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 771 772 773 /* Description RESERVED_3B 774 775 <legal 0> 776 */ 777 778 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 779 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 780 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 781 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 782 783 784 /* Description AST_INDEX 785 786 This field indicates the index of the AST entry corresponding 787 to this MPDU. It is provided by the GSE module instantiated 788 in RXPCU. 789 A value of 0xFFFF indicates an invalid AST index, meaning 790 that No AST entry was found or NO AST search was performed 791 792 <legal all> 793 */ 794 795 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 796 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 797 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 798 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff 799 800 801 /* Description FRAME_CONTROL_FIELD 802 803 Field only valid when Frame_control_info_valid is set. 804 805 Last successfully received Frame_control field of data frame 806 (excluding Data NULL/ QoS Null) for this user 807 Mainly used to track the PM state of the transmitted device 808 809 810 NOTE: only data frame info is needed, as control and management 811 frames are already routed to the FW. 812 <legal all> 813 */ 814 815 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 816 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 817 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 818 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 819 820 821 /* Description FIRST_DATA_SEQ_CTRL 822 823 Field only valid when Data_sequence_control_info_valid is 824 set. 825 826 Sequence control field of the first data frame (excluding 827 Data NULL or QoS Data null) received for this user with 828 correct FCS 829 830 NOTE: only data frame info is needed, as control and management 831 frames are already routed to the FW. 832 <legal all> 833 */ 834 835 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 836 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 837 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 838 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 839 840 841 /* Description QOS_CONTROL_FIELD 842 843 Field only valid when QoS_control_info_valid is set. 844 845 Last successfully received QoS_control field of data frame 846 (excluding Data NULL/ QoS Null) for this user 847 848 Note that in case of multi TID, this field can only reflect 849 the last properly received MPDU, and thus can not indicate 850 all potentially different TIDs that had been received earlier. 851 852 853 There are however per TID fields, that will contain among 854 other things all buffer status info: See 855 QoSCtrl_15_8_tid??? 856 <legal all> 857 */ 858 859 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 860 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 861 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 862 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 863 864 865 /* Description HT_CONTROL_FIELD 866 867 Field only valid when HT_control_info_valid is set. 868 869 Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL 870 field of data frames, excluding QoS Null frames for this 871 user. 872 873 NOTE: HT control fields from QoS Null frames are captured 874 in field HT_control_NULL_field 875 <legal all> 876 */ 877 878 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 879 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 880 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 881 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 882 883 884 /* Description FCS_OK_BITMAP_31_0 885 886 Bitmap indicates in order of received MPDUs, which MPDUs 887 had an passing FCS or had an error. 888 1: FCS OK 889 0: FCS error 890 <legal all> 891 */ 892 893 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 894 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 895 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 896 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 897 898 899 /* Description FCS_OK_BITMAP_63_32 900 901 Bitmap indicates in order of received MPDUs, which MPDUs 902 had an passing FCS or had an error. 903 1: FCS OK 904 0: FCS error 905 906 NOTE: for users 0, 1, 2 and 3, additional bitmap info (up 907 to 256 bitmap window) is provided in RX_PPDU_END_USER_STATS_EXT 908 TLV 909 <legal all> 910 */ 911 912 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 913 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 914 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 915 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff 916 917 918 /* Description UDP_MSDU_COUNT 919 920 Field filled in by RX OLE 921 Set to 0 by RXPCU 922 923 The number of MSDUs that are part of MPDUs without FCS error, 924 that contain UDP frames. 925 <legal all> 926 */ 927 928 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 929 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 930 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 931 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 932 933 934 /* Description TCP_MSDU_COUNT 935 936 Field filled in by RX OLE 937 Set to 0 by RXPCU 938 939 The number of MSDUs that are part of MPDUs without FCS error, 940 that contain TCP frames. 941 942 (Note: This does NOT include TCP-ACK) 943 <legal all> 944 */ 945 946 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 947 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 948 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 949 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 950 951 952 /* Description OTHER_MSDU_COUNT 953 954 Field filled in by RX OLE 955 Set to 0 by RXPCU 956 957 The number of MSDUs that are part of MPDUs without FCS error, 958 that contain neither UDP or TCP frames. 959 960 Includes Management and control frames. 961 962 <legal all> 963 */ 964 965 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 966 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 967 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 968 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff 969 970 971 /* Description TCP_ACK_MSDU_COUNT 972 973 Field filled in by RX OLE 974 Set to 0 by RXPCU 975 976 The number of MSDUs that are part of MPDUs without FCS error, 977 that contain TCP ack frames. 978 <legal all> 979 */ 980 981 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 982 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 983 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 984 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 985 986 987 /* Description SW_RESPONSE_REFERENCE_PTR 988 989 Pointer that SW uses to refer back to an expected response 990 reception. Used for Rate adaptation purposes. 991 When a reception occurs that is not tied to an expected 992 response, this field is set to 0x0. 993 994 Note: further on in this TLV there is also the field: Sw_response_reference_ptr_ext. 995 996 <legal all> 997 */ 998 999 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 1000 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 1001 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 1002 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 1003 1004 1005 /* Description RECEIVED_QOS_DATA_TID_BITMAP 1006 1007 Whenever a frame is received that contains a QoS control 1008 field (that includes QoS Data and/or QoS Null), the bit 1009 in this field that corresponds to the received TID shall 1010 be set. 1011 ...Bitmap[0] = TID0 1012 ...Bitmap[1] = TID1 1013 Etc. 1014 <legal all> 1015 */ 1016 1017 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 1018 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 1019 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 1020 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff 1021 1022 1023 /* Description RECEIVED_QOS_DATA_TID_EOSP_BITMAP 1024 1025 Field initialized to 0 1026 For every QoS Data frame that is correctly received, the 1027 EOSP bit of that frame is copied over into the corresponding 1028 TID related field. 1029 Note that this implies that the bits here represent the 1030 EOSP bit status for each TID of the last MPDU received for 1031 that TID. 1032 1033 received TID shall be set. 1034 ...eosp_bitmap[0] = eosp of TID0 1035 ...eosp_bitmap[1] = eosp of TID1 1036 Etc. 1037 <legal all> 1038 */ 1039 1040 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 1041 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 1042 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 1043 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 1044 1045 1046 /* Description QOSCTRL_15_8_TID0 1047 1048 Field only valid when Received_qos_data_tid_bitmap[0] is 1049 set 1050 1051 QoS control field bits 15-8 of the last properly received 1052 MPDU with a QoS control field embedded, with TID == 0 1053 */ 1054 1055 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 1056 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 1057 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 1058 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 1059 1060 1061 /* Description QOSCTRL_15_8_TID1 1062 1063 Field only valid when Received_qos_data_tid_bitmap[1] is 1064 set 1065 1066 QoS control field bits 15-8 of the last properly received 1067 MPDU with a QoS control field embedded, with TID == 1 1068 */ 1069 1070 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 1071 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 1072 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 1073 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 1074 1075 1076 /* Description QOSCTRL_15_8_TID2 1077 1078 Field only valid when Received_qos_data_tid_bitmap[2] is 1079 set 1080 1081 QoS control field bits 15-8 of the last properly received 1082 MPDU with a QoS control field embedded, with TID == 2 1083 */ 1084 1085 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 1086 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 1087 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 1088 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 1089 1090 1091 /* Description QOSCTRL_15_8_TID3 1092 1093 Field only valid when Received_qos_data_tid_bitmap[3] is 1094 set 1095 1096 QoS control field bits 15-8 of the last properly received 1097 MPDU with a QoS control field embedded, with TID == 3 1098 */ 1099 1100 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 1101 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 1102 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 1103 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 1104 1105 1106 /* Description QOSCTRL_15_8_TID4 1107 1108 Field only valid when Received_qos_data_tid_bitmap[4] is 1109 set 1110 1111 QoS control field bits 15-8 of the last properly received 1112 MPDU with a QoS control field embedded, with TID == 4 1113 */ 1114 1115 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 1116 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 1117 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 1118 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff 1119 1120 1121 /* Description QOSCTRL_15_8_TID5 1122 1123 Field only valid when Received_qos_data_tid_bitmap[5] is 1124 set 1125 1126 QoS control field bits 15-8 of the last properly received 1127 MPDU with a QoS control field embedded, with TID == 5 1128 */ 1129 1130 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 1131 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 1132 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 1133 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 1134 1135 1136 /* Description QOSCTRL_15_8_TID6 1137 1138 Field only valid when Received_qos_data_tid_bitmap[6] is 1139 set 1140 1141 QoS control field bits 15-8 of the last properly received 1142 MPDU with a QoS control field embedded, with TID == 6 1143 */ 1144 1145 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 1146 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 1147 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 1148 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 1149 1150 1151 /* Description QOSCTRL_15_8_TID7 1152 1153 Field only valid when Received_qos_data_tid_bitmap[7] is 1154 set 1155 1156 QoS control field bits 15-8 of the last properly received 1157 MPDU with a QoS control field embedded, with TID == 7 1158 */ 1159 1160 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 1161 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 1162 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 1163 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 1164 1165 1166 /* Description QOSCTRL_15_8_TID8 1167 1168 Field only valid when Received_qos_data_tid_bitmap[8] is 1169 set 1170 1171 QoS control field bits 15-8 of the last properly received 1172 MPDU with a QoS control field embedded, with TID == 8 1173 */ 1174 1175 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 1176 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 1177 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 1178 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 1179 1180 1181 /* Description QOSCTRL_15_8_TID9 1182 1183 Field only valid when Received_qos_data_tid_bitmap[9] is 1184 set 1185 1186 QoS control field bits 15-8 of the last properly received 1187 MPDU with a QoS control field embedded, with TID == 9 1188 */ 1189 1190 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 1191 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 1192 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 1193 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 1194 1195 1196 /* Description QOSCTRL_15_8_TID10 1197 1198 Field only valid when Received_qos_data_tid_bitmap[10] is 1199 set 1200 1201 QoS control field bits 15-8 of the last properly received 1202 MPDU with a QoS control field embedded, with TID == 10 1203 1204 */ 1205 1206 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 1207 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 1208 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 1209 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 1210 1211 1212 /* Description QOSCTRL_15_8_TID11 1213 1214 Field only valid when Received_qos_data_tid_bitmap[11] is 1215 set 1216 1217 QoS control field bits 15-8 of the last properly received 1218 MPDU with a QoS control field embedded, with TID == 11 1219 1220 */ 1221 1222 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 1223 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 1224 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 1225 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 1226 1227 1228 /* Description QOSCTRL_15_8_TID12 1229 1230 Field only valid when Received_qos_data_tid_bitmap[12] is 1231 set 1232 1233 QoS control field bits 15-8 of the last properly received 1234 MPDU with a QoS control field embedded, with TID == 12 1235 1236 */ 1237 1238 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 1239 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 1240 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 1241 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff 1242 1243 1244 /* Description QOSCTRL_15_8_TID13 1245 1246 Field only valid when Received_qos_data_tid_bitmap[13] is 1247 set 1248 1249 QoS control field bits 15-8 of the last properly received 1250 MPDU with a QoS control field embedded, with TID == 13 1251 1252 */ 1253 1254 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 1255 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 1256 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 1257 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 1258 1259 1260 /* Description QOSCTRL_15_8_TID14 1261 1262 Field only valid when Received_qos_data_tid_bitmap[14] is 1263 set 1264 1265 QoS control field bits 15-8 of the last properly received 1266 MPDU with a QoS control field embedded, with TID == 14 1267 1268 */ 1269 1270 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 1271 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 1272 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 1273 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 1274 1275 1276 /* Description QOSCTRL_15_8_TID15 1277 1278 Field only valid when Received_qos_data_tid_bitmap[15] is 1279 set 1280 1281 QoS control field bits 15-8 of the last properly received 1282 MPDU with a QoS control field embedded, with TID == 15 1283 1284 */ 1285 1286 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 1287 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 1288 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 1289 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 1290 1291 1292 /* Description MPDU_OK_BYTE_COUNT 1293 1294 The number of bytes received within an MPDU for this user 1295 with correct FCS. This includes the FCS field 1296 1297 NOTE: 1298 The sum of the four fields..... 1299 Mpdu_ok_byte_count + 1300 mpdu_err_byte_count + 1301 (Ampdu_delim_ok_count x 4) + (Ampdu_delim_err_count x 4) 1302 1303 .....is the total number of bytes that were received for 1304 this user from the PHY. 1305 1306 <legal all> 1307 */ 1308 1309 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 1310 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 1311 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 1312 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 1313 1314 1315 /* Description AMPDU_DELIM_OK_COUNT_6_0 1316 1317 Number of AMPDU delimiter received with correct structure 1318 1319 LSB 7 bits from this counter 1320 1321 Note that this is a delimiter count and not byte count. 1322 To get to the number of bytes occupied by these delimiters, 1323 multiply this number by 4 1324 1325 <legal all> 1326 */ 1327 1328 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 1329 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 1330 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 1331 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 1332 1333 1334 /* Description AMPDU_DELIM_ERR_COUNT 1335 1336 The number of MPDU delimiter errors counted for this user. 1337 1338 1339 Note that this is a delimiter count and not byte count. 1340 To get to the number of bytes occupied by these delimiters, 1341 multiply this number by 4 1342 <legal all> 1343 */ 1344 1345 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 1346 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 1347 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 1348 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff 1349 1350 1351 /* Description AMPDU_DELIM_OK_COUNT_13_7 1352 1353 Number of AMPDU delimiters received with correct structure 1354 1355 Bits 13-7 from this counter 1356 1357 Note that this is a delimiter count and not byte count. 1358 To get to the number of bytes occupied by these delimiters, 1359 multiply this number by 4 1360 <legal all> 1361 */ 1362 1363 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 1364 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 1365 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 1366 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 1367 1368 1369 /* Description MPDU_ERR_BYTE_COUNT 1370 1371 The number of bytes belonging to MPDUs with an FCS error. 1372 This includes the FCS field. 1373 1374 <legal all> 1375 */ 1376 1377 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 1378 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 1379 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 1380 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 1381 1382 1383 /* Description AMPDU_DELIM_OK_COUNT_20_14 1384 1385 Number of AMPDU delimiters received with correct structure 1386 1387 Bits 20-14 from this counter 1388 1389 Note that this is a delimiter count and not byte count. 1390 To get to the number of bytes occupied by these delimiters, 1391 multiply this number by 4 1392 1393 <legal all> 1394 */ 1395 1396 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 1397 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 1398 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 1399 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 1400 1401 1402 /* Description NON_CONSECUTIVE_DELIMITER_ERR 1403 1404 The number of times an MPDU delimiter error is detected 1405 that is not immediately preceded by another MPDU delimiter 1406 also with FCS error. 1407 1408 The counter saturates at 0xFFFF 1409 1410 <legal all> 1411 */ 1412 1413 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 1414 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 1415 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 1416 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff 1417 1418 1419 /* Description RETRIED_MSDU_COUNT 1420 1421 Field filled in by RX OLE 1422 Set to 0 by RXPCU 1423 1424 The number of MSDUs that are part of MPDUs without FCS error, 1425 that have the retry bit set. 1426 <legal all> 1427 */ 1428 1429 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 1430 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 1431 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 1432 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 1433 1434 1435 /* Description HT_CONTROL_NULL_FIELD 1436 1437 Field only valid when HT_control_info_NULL_valid is set. 1438 1439 1440 Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL 1441 field from QoS Null frame for this user. 1442 <legal all> 1443 */ 1444 1445 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 1446 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 1447 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 1448 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 1449 1450 1451 /* Description SW_RESPONSE_REFERENCE_PTR_EXT 1452 1453 Extended Pointer info that SW uses to refer back to an expected 1454 response transmission. Used for Rate adaptation purposes. 1455 1456 When a reception occurs that is not tied to an expected 1457 response, this field is set to 0x0. 1458 1459 Note: earlier on in this TLV there is also the field: Sw_response_reference_ptr. 1460 1461 <legal all> 1462 */ 1463 1464 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 1465 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 1466 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 1467 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff 1468 1469 1470 /* Description CORRUPTED_DUE_TO_FIFO_DELAY 1471 1472 Set if Rx PCU avoided a hang due to SFM delays by writing 1473 a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' 1474 1475 */ 1476 1477 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 1478 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 1479 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 1480 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 1481 1482 1483 /* Description FRAME_CONTROL_INFO_NULL_VALID 1484 1485 When set, Frame_control_field_null contains valid information 1486 1487 <legal all> 1488 */ 1489 1490 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 1491 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 1492 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 1493 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 1494 1495 1496 /* Description FRAME_CONTROL_FIELD_NULL 1497 1498 Field only valid when Frame_control_info_null_valid is set. 1499 1500 1501 Last successfully received Frame_control field of Data Null/QoS 1502 Null for this user, mainly used to track the PM state of 1503 the transmitted device 1504 <legal all> 1505 */ 1506 1507 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 1508 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 1509 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 1510 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 1511 1512 1513 /* Description RETRIED_MPDU_COUNT 1514 1515 Field filled in by RXPCU 1516 1517 The number of MPDUs without FCS error, that have the retry 1518 bit set. 1519 <legal all> 1520 */ 1521 1522 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 1523 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 1524 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 1525 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 1526 1527 1528 /* Description RESERVED_23A 1529 1530 <legal 0> 1531 */ 1532 1533 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 1534 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 1535 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 1536 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 1537 1538 1539 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 1540 1541 Field indicates what the reason was that the last successfully 1542 received MPDU was allowed to come into the receive path 1543 by RXPCU. 1544 <enum 0 rxpcu_filter_pass> The last MPDU passed the normal 1545 frame filter programming of rxpcu 1546 <enum 1 rxpcu_monitor_client> The last MPDU did NOT pass 1547 the regular frame filter and would have been dropped, were 1548 it not for the frame fitting into the 'monitor_client' 1549 category. 1550 <enum 2 rxpcu_monitor_other> The last MPDU did NOT pass 1551 the regular frame filter and also did not pass the rxpcu_monitor_client 1552 filter. It would have been dropped accept that it did pass 1553 the 'monitor_other' category. 1554 <enum 3 rxpcu_filter_pass_monitor_ovrd> The last MPDU passed 1555 the normal frame filter programming of RXPCU but additionally 1556 fit into the 'monitor_override_client' category. 1557 1558 Hamilton and Waikiki did not include this (and any subsequent) 1559 word. 1560 <legal 0-3> 1561 */ 1562 1563 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 1564 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1565 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 1566 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 1567 1568 1569 /* Description SW_FRAME_GROUP_ID 1570 1571 SW processes frames based on certain classifications. This 1572 field indicates to what sw classification the last successfully 1573 received MPDU is mapped. 1574 The classification is given in priority order 1575 1576 <enum 0 sw_frame_group_NDP_frame> 1577 1578 <enum 1 sw_frame_group_Multicast_data> 1579 <enum 2 sw_frame_group_Unicast_data> 1580 <enum 3 sw_frame_group_Null_data > This includes mpdus of 1581 type Data Null. 1582 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 1583 Null frames except in UL MU or TB PPDUs. 1584 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 1585 QoS Null frames in UL MU or TB PPDUs. 1586 1587 <enum 4 sw_frame_group_mgmt_0000 > 1588 <enum 5 sw_frame_group_mgmt_0001 > 1589 <enum 6 sw_frame_group_mgmt_0010 > 1590 <enum 7 sw_frame_group_mgmt_0011 > 1591 <enum 8 sw_frame_group_mgmt_0100 > 1592 <enum 9 sw_frame_group_mgmt_0101 > 1593 <enum 10 sw_frame_group_mgmt_0110 > 1594 <enum 11 sw_frame_group_mgmt_0111 > 1595 <enum 12 sw_frame_group_mgmt_1000 > 1596 <enum 13 sw_frame_group_mgmt_1001 > 1597 <enum 14 sw_frame_group_mgmt_1010 > 1598 <enum 15 sw_frame_group_mgmt_1011 > 1599 <enum 16 sw_frame_group_mgmt_1100 > 1600 <enum 17 sw_frame_group_mgmt_1101 > 1601 <enum 18 sw_frame_group_mgmt_1110 > 1602 <enum 19 sw_frame_group_mgmt_1111 > 1603 1604 <enum 20 sw_frame_group_ctrl_0000 > 1605 <enum 21 sw_frame_group_ctrl_0001 > 1606 <enum 22 sw_frame_group_ctrl_0010 > 1607 <enum 23 sw_frame_group_ctrl_0011 > 1608 <enum 24 sw_frame_group_ctrl_0100 > 1609 <enum 25 sw_frame_group_ctrl_0101 > 1610 <enum 26 sw_frame_group_ctrl_0110 > 1611 <enum 27 sw_frame_group_ctrl_0111 > 1612 <enum 28 sw_frame_group_ctrl_1000 > 1613 <enum 29 sw_frame_group_ctrl_1001 > 1614 <enum 30 sw_frame_group_ctrl_1010 > 1615 <enum 31 sw_frame_group_ctrl_1011 > 1616 <enum 32 sw_frame_group_ctrl_1100 > 1617 <enum 33 sw_frame_group_ctrl_1101 > 1618 <enum 34 sw_frame_group_ctrl_1110 > 1619 <enum 35 sw_frame_group_ctrl_1111 > 1620 1621 <enum 36 sw_frame_group_unsupported> This covers type 3 1622 and protocol version != 0 1623 1624 <enum 37 sw_frame_group_phy_error> PHY reported an error 1625 1626 1627 <legal 0-39> 1628 */ 1629 1630 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 1631 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 1632 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 1633 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 1634 1635 1636 /* Description RESERVED_24A 1637 1638 <legal 0> 1639 */ 1640 1641 #define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 1642 #define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 1643 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 1644 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 1645 1646 1647 /* Description FRAME_CONTROL_INFO_MGMT_CTRL_VALID 1648 1649 When set, Frame_control_field_mgmt_ctrl contains valid information. 1650 1651 <legal all> 1652 */ 1653 1654 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 1655 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 1656 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 1657 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 1658 1659 1660 /* Description MAC_ADDR_AD2_VALID 1661 1662 When set, the fields mac_addr_ad2_... contain valid information. 1663 1664 <legal all> 1665 */ 1666 1667 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 1668 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 1669 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 1670 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 1671 1672 1673 /* Description MCAST_BCAST 1674 1675 Multicast / broadcast indicator 1676 1677 Only set when the MAC address 1 bit 0 is set indicating 1678 mcast/bcast and the BSSID matches one of the BSSID registers, 1679 for the last successfully received MPDU 1680 <legal all> 1681 */ 1682 1683 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 1684 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 1685 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 1686 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 1687 1688 1689 /* Description FRAME_CONTROL_FIELD_MGMT_CTRL 1690 1691 Field only valid when Frame_control_info_mgmt_ctrl_valid 1692 is set 1693 1694 Last successfully received 'Frame control' field of control 1695 or management frames for this user, mainly used in Rx monitor 1696 mode 1697 <legal all> 1698 */ 1699 1700 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 1701 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 1702 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 1703 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 1704 1705 1706 /* Description USER_PPDU_LEN 1707 1708 The sum of the mpdu_length fields of all the 'RX_MPDU_START' 1709 TLVs generated for this user for this PPDU 1710 */ 1711 1712 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 1713 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 1714 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 1715 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 1716 1717 1718 /* Description RESERVED_25A 1719 1720 <legal 0> 1721 */ 1722 1723 #define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 1724 #define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 1725 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 1726 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 1727 1728 1729 /* Description MAC_ADDR_AD2_31_0 1730 1731 Field only valid when mac_addr_ad2_valid is set 1732 1733 The least significant 4 bytes of the last successfully received 1734 frame's MAC Address AD2 1735 <legal all> 1736 */ 1737 1738 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 1739 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 1740 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 1741 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff 1742 1743 1744 /* Description MAC_ADDR_AD2_47_32 1745 1746 Field only valid when mac_addr_ad2_valid is set 1747 1748 The 2 most significant bytes of the last successfully received 1749 frame's MAC Address AD2 1750 <legal all> 1751 */ 1752 1753 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 1754 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 1755 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 1756 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 1757 1758 1759 /* Description AMSDU_MSDU_COUNT 1760 1761 Field filled in by RX OLE 1762 Set to 0 by RXPCU 1763 1764 The number of MSDUs that are part of A-MSDUs that are part 1765 of MPDUs without FCS error 1766 <legal all> 1767 */ 1768 1769 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 1770 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 1771 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 1772 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 1773 1774 1775 /* Description NON_AMSDU_MSDU_COUNT 1776 1777 Field filled in by RX OLE 1778 Set to 0 by RXPCU 1779 1780 The number of MSDUs that are not part of A-MSDUs that are 1781 part of MPDUs without FCS error 1782 <legal all> 1783 */ 1784 1785 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 1786 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 1787 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 1788 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff 1789 1790 1791 /* Description UCAST_MSDU_COUNT 1792 1793 Field filled in by RX OLE 1794 Set to 0 by RXPCU 1795 1796 The number of MSDUs that are part of MPDUs without FCS error, 1797 that are directed to a unicast destination address 1798 <legal all> 1799 */ 1800 1801 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1802 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 1803 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 1804 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 1805 1806 1807 /* Description BCAST_MSDU_COUNT 1808 1809 Field filled in by RX OLE 1810 Set to 0 by RXPCU 1811 1812 The number of MSDUs that are part of MPDUs without FCS error, 1813 whose destination addresses are broadcast (0xFFFF_FFFF_FFFF) 1814 1815 <legal all> 1816 */ 1817 1818 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1819 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 1820 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 1821 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 1822 1823 1824 /* Description MCAST_BCAST_MSDU_COUNT 1825 1826 Field filled in by RX OLE 1827 Set to 0 by RXPCU 1828 1829 The number of MSDUs that are part of MPDUs without FCS error, 1830 whose destination addresses are either multicast or broadcast 1831 1832 <legal all> 1833 */ 1834 1835 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1836 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 1837 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 1838 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 1839 1840 1841 1842 #endif // RX_PPDU_END_USER_STATS 1843