1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _RX_MSDU_START_H_
27 #define _RX_MSDU_START_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_RX_MSDU_START 10
32 
33 #define NUM_OF_QWORDS_RX_MSDU_START 5
34 
35 
36 struct rx_msdu_start {
37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
38              uint32_t rxpcu_mpdu_filter_in_category                           :  2, // [1:0]
39                       sw_frame_group_id                                       :  7, // [8:2]
40                       reserved_0                                              :  7, // [15:9]
41                       phy_ppdu_id                                             : 16; // [31:16]
42              uint32_t msdu_length                                             : 14, // [13:0]
43                       stbc                                                    :  1, // [14:14]
44                       ipsec_esp                                               :  1, // [15:15]
45                       l3_offset                                               :  7, // [22:16]
46                       ipsec_ah                                                :  1, // [23:23]
47                       l4_offset                                               :  8; // [31:24]
48              uint32_t msdu_number                                             :  8, // [7:0]
49                       decap_format                                            :  2, // [9:8]
50                       ipv4_proto                                              :  1, // [10:10]
51                       ipv6_proto                                              :  1, // [11:11]
52                       tcp_proto                                               :  1, // [12:12]
53                       udp_proto                                               :  1, // [13:13]
54                       ip_frag                                                 :  1, // [14:14]
55                       tcp_only_ack                                            :  1, // [15:15]
56                       da_is_bcast_mcast                                       :  1, // [16:16]
57                       toeplitz_hash_sel                                       :  2, // [18:17]
58                       ip_fixed_header_valid                                   :  1, // [19:19]
59                       ip_extn_header_valid                                    :  1, // [20:20]
60                       tcp_udp_header_valid                                    :  1, // [21:21]
61                       mesh_control_present                                    :  1, // [22:22]
62                       ldpc                                                    :  1, // [23:23]
63                       ip4_protocol_ip6_next_header                            :  8; // [31:24]
64              uint32_t toeplitz_hash_2_or_4                                    : 32; // [31:0]
65              uint32_t flow_id_toeplitz                                        : 32; // [31:0]
66              uint32_t user_rssi                                               :  8, // [7:0]
67                       pkt_type                                                :  4, // [11:8]
68                       sgi                                                     :  2, // [13:12]
69                       rate_mcs                                                :  4, // [17:14]
70                       receive_bandwidth                                       :  3, // [20:18]
71                       reception_type                                          :  3, // [23:21]
72                       mimo_ss_bitmap                                          :  8; // [31:24]
73              uint32_t ppdu_start_timestamp_31_0                               : 32; // [31:0]
74              uint32_t ppdu_start_timestamp_63_32                              : 32; // [31:0]
75              uint32_t sw_phy_meta_data                                        : 32; // [31:0]
76              uint32_t vlan_ctag_ci                                            : 16, // [15:0]
77                       vlan_stag_ci                                            : 16; // [31:16]
78 #else
79              uint32_t phy_ppdu_id                                             : 16, // [31:16]
80                       reserved_0                                              :  7, // [15:9]
81                       sw_frame_group_id                                       :  7, // [8:2]
82                       rxpcu_mpdu_filter_in_category                           :  2; // [1:0]
83              uint32_t l4_offset                                               :  8, // [31:24]
84                       ipsec_ah                                                :  1, // [23:23]
85                       l3_offset                                               :  7, // [22:16]
86                       ipsec_esp                                               :  1, // [15:15]
87                       stbc                                                    :  1, // [14:14]
88                       msdu_length                                             : 14; // [13:0]
89              uint32_t ip4_protocol_ip6_next_header                            :  8, // [31:24]
90                       ldpc                                                    :  1, // [23:23]
91                       mesh_control_present                                    :  1, // [22:22]
92                       tcp_udp_header_valid                                    :  1, // [21:21]
93                       ip_extn_header_valid                                    :  1, // [20:20]
94                       ip_fixed_header_valid                                   :  1, // [19:19]
95                       toeplitz_hash_sel                                       :  2, // [18:17]
96                       da_is_bcast_mcast                                       :  1, // [16:16]
97                       tcp_only_ack                                            :  1, // [15:15]
98                       ip_frag                                                 :  1, // [14:14]
99                       udp_proto                                               :  1, // [13:13]
100                       tcp_proto                                               :  1, // [12:12]
101                       ipv6_proto                                              :  1, // [11:11]
102                       ipv4_proto                                              :  1, // [10:10]
103                       decap_format                                            :  2, // [9:8]
104                       msdu_number                                             :  8; // [7:0]
105              uint32_t toeplitz_hash_2_or_4                                    : 32; // [31:0]
106              uint32_t flow_id_toeplitz                                        : 32; // [31:0]
107              uint32_t mimo_ss_bitmap                                          :  8, // [31:24]
108                       reception_type                                          :  3, // [23:21]
109                       receive_bandwidth                                       :  3, // [20:18]
110                       rate_mcs                                                :  4, // [17:14]
111                       sgi                                                     :  2, // [13:12]
112                       pkt_type                                                :  4, // [11:8]
113                       user_rssi                                               :  8; // [7:0]
114              uint32_t ppdu_start_timestamp_31_0                               : 32; // [31:0]
115              uint32_t ppdu_start_timestamp_63_32                              : 32; // [31:0]
116              uint32_t sw_phy_meta_data                                        : 32; // [31:0]
117              uint32_t vlan_stag_ci                                            : 16, // [31:16]
118                       vlan_ctag_ci                                            : 16; // [15:0]
119 #endif
120 };
121 
122 
123 /* Description		RXPCU_MPDU_FILTER_IN_CATEGORY
124 
125 			Field indicates what the reason was that this MPDU frame
126 			 was allowed to come into the receive path by RXPCU
127 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal frame
128 			 filter programming of rxpcu
129 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
130 			 regular frame filter and would have been dropped, were
131 			it not for the frame fitting into the 'monitor_client' category.
132 
133 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
134 			regular frame filter and also did not pass the rxpcu_monitor_client
135 			 filter. It would have been dropped accept that it did pass
136 			 the 'monitor_other' category.
137 			<enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed
138 			 the normal frame filter programming of RXPCU but additionally
139 			 fit into the 'monitor_override_client' category.
140 			<legal 0-3>
141 */
142 
143 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                          0x0000000000000000
144 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                             0
145 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                             1
146 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                            0x0000000000000003
147 
148 
149 /* Description		SW_FRAME_GROUP_ID
150 
151 			SW processes frames based on certain classifications. This
152 			 field indicates to what sw classification this MPDU is
153 			mapped.
154 			The classification is given in priority order
155 
156 			<enum 0 sw_frame_group_NDP_frame>
157 
158 			<enum 1 sw_frame_group_Multicast_data>
159 			<enum 2 sw_frame_group_Unicast_data>
160 			<enum 3 sw_frame_group_Null_data > This includes mpdus of
161 			 type Data Null.
162 			Hamilton v1 included QoS Data Null as well here.
163 			<enum 38 sw_frame_group_QoS_Null_data> This includes QoS
164 			 Null frames except in UL MU or TB PPDUs.
165 			<enum 39 sw_frame_group_QoS_Null_data_TB> This includes
166 			QoS Null frames in UL MU or TB PPDUs.
167 
168 			<enum 4 sw_frame_group_mgmt_0000 >
169 			<enum 5 sw_frame_group_mgmt_0001 >
170 			<enum 6 sw_frame_group_mgmt_0010 >
171 			<enum 7 sw_frame_group_mgmt_0011 >
172 			<enum 8 sw_frame_group_mgmt_0100 >
173 			<enum 9 sw_frame_group_mgmt_0101 >
174 			<enum 10 sw_frame_group_mgmt_0110 >
175 			<enum 11 sw_frame_group_mgmt_0111 >
176 			<enum 12 sw_frame_group_mgmt_1000 >
177 			<enum 13 sw_frame_group_mgmt_1001 >
178 			<enum 14 sw_frame_group_mgmt_1010 >
179 			<enum 15 sw_frame_group_mgmt_1011 >
180 			<enum 16 sw_frame_group_mgmt_1100 >
181 			<enum 17 sw_frame_group_mgmt_1101 >
182 			<enum 18 sw_frame_group_mgmt_1110 >
183 			<enum 19 sw_frame_group_mgmt_1111 >
184 
185 			<enum 20 sw_frame_group_ctrl_0000 >
186 			<enum 21 sw_frame_group_ctrl_0001 >
187 			<enum 22 sw_frame_group_ctrl_0010 >
188 			<enum 23 sw_frame_group_ctrl_0011 >
189 			<enum 24 sw_frame_group_ctrl_0100 >
190 			<enum 25 sw_frame_group_ctrl_0101 >
191 			<enum 26 sw_frame_group_ctrl_0110 >
192 			<enum 27 sw_frame_group_ctrl_0111 >
193 			<enum 28 sw_frame_group_ctrl_1000 >
194 			<enum 29 sw_frame_group_ctrl_1001 >
195 			<enum 30 sw_frame_group_ctrl_1010 >
196 			<enum 31 sw_frame_group_ctrl_1011 >
197 			<enum 32 sw_frame_group_ctrl_1100 >
198 			<enum 33 sw_frame_group_ctrl_1101 >
199 			<enum 34 sw_frame_group_ctrl_1110 >
200 			<enum 35 sw_frame_group_ctrl_1111 >
201 
202 			<enum 36 sw_frame_group_unsupported> This covers type 3
203 			and protocol version != 0
204 
205 			<enum 37 sw_frame_group_phy_error> PHY reported an error
206 
207 
208 			<legal 0-39>
209 */
210 
211 #define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET                                      0x0000000000000000
212 #define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB                                         2
213 #define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB                                         8
214 #define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK                                        0x00000000000001fc
215 
216 
217 /* Description		RESERVED_0
218 
219 			<legal 0>
220 */
221 
222 #define RX_MSDU_START_RESERVED_0_OFFSET                                             0x0000000000000000
223 #define RX_MSDU_START_RESERVED_0_LSB                                                9
224 #define RX_MSDU_START_RESERVED_0_MSB                                                15
225 #define RX_MSDU_START_RESERVED_0_MASK                                               0x000000000000fe00
226 
227 
228 /* Description		PHY_PPDU_ID
229 
230 			A ppdu counter value that PHY increments for every PPDU
231 			received. The counter value wraps around
232 			<legal all>
233 */
234 
235 #define RX_MSDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
236 #define RX_MSDU_START_PHY_PPDU_ID_LSB                                               16
237 #define RX_MSDU_START_PHY_PPDU_ID_MSB                                               31
238 #define RX_MSDU_START_PHY_PPDU_ID_MASK                                              0x00000000ffff0000
239 
240 
241 /* Description		MSDU_LENGTH
242 
243 			MSDU length in bytes after decapsulation.
244 
245 			This field is still valid for MPDU frames without A-MSDU.
246 			 It still represents MSDU length after decapsulation
247 */
248 
249 #define RX_MSDU_START_MSDU_LENGTH_OFFSET                                            0x0000000000000000
250 #define RX_MSDU_START_MSDU_LENGTH_LSB                                               32
251 #define RX_MSDU_START_MSDU_LENGTH_MSB                                               45
252 #define RX_MSDU_START_MSDU_LENGTH_MASK                                              0x00003fff00000000
253 
254 
255 /* Description		STBC
256 
257 			When set, use STBC transmission rates
258 */
259 
260 #define RX_MSDU_START_STBC_OFFSET                                                   0x0000000000000000
261 #define RX_MSDU_START_STBC_LSB                                                      46
262 #define RX_MSDU_START_STBC_MSB                                                      46
263 #define RX_MSDU_START_STBC_MASK                                                     0x0000400000000000
264 
265 
266 /* Description		IPSEC_ESP
267 
268 			Set if IPv4/v6 packet is using IPsec ESP
269 */
270 
271 #define RX_MSDU_START_IPSEC_ESP_OFFSET                                              0x0000000000000000
272 #define RX_MSDU_START_IPSEC_ESP_LSB                                                 47
273 #define RX_MSDU_START_IPSEC_ESP_MSB                                                 47
274 #define RX_MSDU_START_IPSEC_ESP_MASK                                                0x0000800000000000
275 
276 
277 /* Description		L3_OFFSET
278 
279 			Depending upon mode bit, this field either indicates the
280 			 L3 offset in bytes from the start of the RX_HEADER or the
281 			 IP offset in bytes from the start of the packet after decapsulation.
282 			 The latter is only valid if ipv4_proto or ipv6_proto is
283 			 set.
284 */
285 
286 #define RX_MSDU_START_L3_OFFSET_OFFSET                                              0x0000000000000000
287 #define RX_MSDU_START_L3_OFFSET_LSB                                                 48
288 #define RX_MSDU_START_L3_OFFSET_MSB                                                 54
289 #define RX_MSDU_START_L3_OFFSET_MASK                                                0x007f000000000000
290 
291 
292 /* Description		IPSEC_AH
293 
294 			Set if IPv4/v6 packet is using IPsec AH
295 */
296 
297 #define RX_MSDU_START_IPSEC_AH_OFFSET                                               0x0000000000000000
298 #define RX_MSDU_START_IPSEC_AH_LSB                                                  55
299 #define RX_MSDU_START_IPSEC_AH_MSB                                                  55
300 #define RX_MSDU_START_IPSEC_AH_MASK                                                 0x0080000000000000
301 
302 
303 /* Description		L4_OFFSET
304 
305 			Depending upon mode bit, this field either indicates the
306 			 L4 offset nin bytes from the start of RX_HEADER(only valid
307 			 if either ipv4_proto or ipv6_proto is set to 1) or indicates
308 			 the offset in bytes to the start of TCP or UDP header from
309 			 the start of the IP header after decapsulation(Only valid
310 			 if tcp_proto or udp_proto is set).  The value 0 indicates
311 			 that the offset is longer than 127 bytes.
312 */
313 
314 #define RX_MSDU_START_L4_OFFSET_OFFSET                                              0x0000000000000000
315 #define RX_MSDU_START_L4_OFFSET_LSB                                                 56
316 #define RX_MSDU_START_L4_OFFSET_MSB                                                 63
317 #define RX_MSDU_START_L4_OFFSET_MASK                                                0xff00000000000000
318 
319 
320 /* Description		MSDU_NUMBER
321 
322 			Indicates the MSDU number within a MPDU.  This value is
323 			reset to zero at the start of each MPDU.  If the number
324 			of MSDU exceeds 255 this number will wrap using modulo 256.
325 
326 */
327 
328 #define RX_MSDU_START_MSDU_NUMBER_OFFSET                                            0x0000000000000008
329 #define RX_MSDU_START_MSDU_NUMBER_LSB                                               0
330 #define RX_MSDU_START_MSDU_NUMBER_MSB                                               7
331 #define RX_MSDU_START_MSDU_NUMBER_MASK                                              0x00000000000000ff
332 
333 
334 /* Description		DECAP_FORMAT
335 
336 			Indicates the format after decapsulation:
337 
338 			<enum 0 RAW> No encapsulation
339 			<enum 1 Native_WiFi>
340 			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses SNAP/LLC)
341 
342 			<enum 3 802_3> Indicate Ethernet
343 
344 			<legal all>
345 */
346 
347 #define RX_MSDU_START_DECAP_FORMAT_OFFSET                                           0x0000000000000008
348 #define RX_MSDU_START_DECAP_FORMAT_LSB                                              8
349 #define RX_MSDU_START_DECAP_FORMAT_MSB                                              9
350 #define RX_MSDU_START_DECAP_FORMAT_MASK                                             0x0000000000000300
351 
352 
353 /* Description		IPV4_PROTO
354 
355 			Set if L2 layer indicates IPv4 protocol.
356 */
357 
358 #define RX_MSDU_START_IPV4_PROTO_OFFSET                                             0x0000000000000008
359 #define RX_MSDU_START_IPV4_PROTO_LSB                                                10
360 #define RX_MSDU_START_IPV4_PROTO_MSB                                                10
361 #define RX_MSDU_START_IPV4_PROTO_MASK                                               0x0000000000000400
362 
363 
364 /* Description		IPV6_PROTO
365 
366 			Set if L2 layer indicates IPv6 protocol.
367 */
368 
369 #define RX_MSDU_START_IPV6_PROTO_OFFSET                                             0x0000000000000008
370 #define RX_MSDU_START_IPV6_PROTO_LSB                                                11
371 #define RX_MSDU_START_IPV6_PROTO_MSB                                                11
372 #define RX_MSDU_START_IPV6_PROTO_MASK                                               0x0000000000000800
373 
374 
375 /* Description		TCP_PROTO
376 
377 			Set if the ipv4_proto or ipv6_proto are set and the IP protocol
378 			 indicates TCP.
379 */
380 
381 #define RX_MSDU_START_TCP_PROTO_OFFSET                                              0x0000000000000008
382 #define RX_MSDU_START_TCP_PROTO_LSB                                                 12
383 #define RX_MSDU_START_TCP_PROTO_MSB                                                 12
384 #define RX_MSDU_START_TCP_PROTO_MASK                                                0x0000000000001000
385 
386 
387 /* Description		UDP_PROTO
388 
389 			Set if the ipv4_proto or ipv6_proto are set and the IP protocol
390 			 indicates UDP.
391 */
392 
393 #define RX_MSDU_START_UDP_PROTO_OFFSET                                              0x0000000000000008
394 #define RX_MSDU_START_UDP_PROTO_LSB                                                 13
395 #define RX_MSDU_START_UDP_PROTO_MSB                                                 13
396 #define RX_MSDU_START_UDP_PROTO_MASK                                                0x0000000000002000
397 
398 
399 /* Description		IP_FRAG
400 
401 			Indicates that either the IP More frag bit is set or IP
402 			frag number is non-zero.  If set indicates that this is
403 			a fragmented IP packet.
404 */
405 
406 #define RX_MSDU_START_IP_FRAG_OFFSET                                                0x0000000000000008
407 #define RX_MSDU_START_IP_FRAG_LSB                                                   14
408 #define RX_MSDU_START_IP_FRAG_MSB                                                   14
409 #define RX_MSDU_START_IP_FRAG_MASK                                                  0x0000000000004000
410 
411 
412 /* Description		TCP_ONLY_ACK
413 
414 			Set if only the TCP Ack bit is set in the TCP flags and
415 			if the TCP payload is 0.
416 */
417 
418 #define RX_MSDU_START_TCP_ONLY_ACK_OFFSET                                           0x0000000000000008
419 #define RX_MSDU_START_TCP_ONLY_ACK_LSB                                              15
420 #define RX_MSDU_START_TCP_ONLY_ACK_MSB                                              15
421 #define RX_MSDU_START_TCP_ONLY_ACK_MASK                                             0x0000000000008000
422 
423 
424 /* Description		DA_IS_BCAST_MCAST
425 
426 			The destination address is broadcast or multicast.
427 */
428 
429 #define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET                                      0x0000000000000008
430 #define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB                                         16
431 #define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB                                         16
432 #define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK                                        0x0000000000010000
433 
434 
435 /* Description		TOEPLITZ_HASH_SEL
436 
437 			Actual choosen Hash.
438 
439 			0 -> Toeplitz hash of 2-tuple (IP source address, IP destination
440 			 address)1 -> Toeplitz hash of 4-tuple (IP source address,
441 			IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP)
442 			destination port)
443 			2 -> Toeplitz of flow_id
444 			3 -> "Zero" is used
445 			<legal all>
446 */
447 
448 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET                                      0x0000000000000008
449 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB                                         17
450 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB                                         18
451 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK                                        0x0000000000060000
452 
453 
454 /* Description		IP_FIXED_HEADER_VALID
455 
456 			Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
457 			fully within first 256 bytes of the packet
458 */
459 
460 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET                                  0x0000000000000008
461 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB                                     19
462 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB                                     19
463 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK                                    0x0000000000080000
464 
465 
466 /* Description		IP_EXTN_HEADER_VALID
467 
468 			IPv6/IPv6 header, including IPv4 options and recognizable
469 			 extension headers parsed fully within first 256 bytes of
470 			 the packet
471 */
472 
473 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET                                   0x0000000000000008
474 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB                                      20
475 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB                                      20
476 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK                                     0x0000000000100000
477 
478 
479 /* Description		TCP_UDP_HEADER_VALID
480 
481 			Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
482 			header parsed fully within first 256 bytes of the packet
483 
484 */
485 
486 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET                                   0x0000000000000008
487 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB                                      21
488 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB                                      21
489 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK                                     0x0000000000200000
490 
491 
492 /* Description		MESH_CONTROL_PRESENT
493 
494 			When set, this MSDU includes the 'Mesh Control' field
495 			<legal all>
496 */
497 
498 #define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET                                   0x0000000000000008
499 #define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB                                      22
500 #define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB                                      22
501 #define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK                                     0x0000000000400000
502 
503 
504 /* Description		LDPC
505 
506 			When set, indicates that LDPC coding was used.
507 			<legal all>
508 */
509 
510 #define RX_MSDU_START_LDPC_OFFSET                                                   0x0000000000000008
511 #define RX_MSDU_START_LDPC_LSB                                                      23
512 #define RX_MSDU_START_LDPC_MSB                                                      23
513 #define RX_MSDU_START_LDPC_MASK                                                     0x0000000000800000
514 
515 
516 /* Description		IP4_PROTOCOL_IP6_NEXT_HEADER
517 
518 			For IPv4 this is the 8 bit protocol field (when ipv4_proto
519 			 is set).  For IPv6 this is the 8 bit next_header field (when
520 			 ipv6_proto is set).
521 */
522 
523 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                           0x0000000000000008
524 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                              24
525 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                              31
526 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                             0x00000000ff000000
527 
528 
529 /* Description		TOEPLITZ_HASH_2_OR_4
530 
531 			Controlled by multiple RxOLE registers for TCP/UDP over
532 			IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple
533 			IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz
534 			 hash computed over 4-tuple IPv4 or IPv6 src/dest addresses
535 			 and src/dest ports is reported. The Flow_id_toeplitz hash
536 			 can also be reported here. Usually the hash reported here
537 			 is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy
538 			 in 'RXPT_CLASSIFY_INFO').
539 
540 			In Pine, optionally the 3-tuple Toeplitz hash over IPv4
541 			or IPv6 src/dest addresses and L4 protocol can be reported
542 			 here. (Unsupported in HastingsPrime)
543 */
544 
545 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET                                   0x0000000000000008
546 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB                                      32
547 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB                                      63
548 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK                                     0xffffffff00000000
549 
550 
551 /* Description		FLOW_ID_TOEPLITZ
552 
553 			Toeplitz hash of 5-tuple
554 			{IP source address, IP destination address, IP source port,
555 			IP destination port, L4 protocol}  in case of non-IPSec.
556 
557 			In case of IPSec - Toeplitz hash of 4-tuple
558 			{IP source address, IP destination address, SPI, L4 protocol}
559 
560 
561 			In Pine, optionally the 3-tuple Toeplitz hash over IPv4
562 			or IPv6 src/dest addresses and L4 protocol can be reported
563 			 here. (Unsupported in HastingsPrime)
564 
565 			The relevant Toeplitz key registers are provided in RxOLE's
566 			 instance of common parser module. These registers are separate
567 			 from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The
568 			 actual value will be passed on from common parser module
569 			 to RxOLE in one of the WHO_* TLVs.
570 			<legal all>
571 */
572 
573 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET                                       0x0000000000000010
574 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB                                          0
575 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB                                          31
576 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK                                         0x00000000ffffffff
577 
578 
579 /* Description		USER_RSSI
580 
581 			RSSI for this user
582 			<legal all>
583 */
584 
585 #define RX_MSDU_START_USER_RSSI_OFFSET                                              0x0000000000000010
586 #define RX_MSDU_START_USER_RSSI_LSB                                                 32
587 #define RX_MSDU_START_USER_RSSI_MSB                                                 39
588 #define RX_MSDU_START_USER_RSSI_MASK                                                0x000000ff00000000
589 
590 
591 /* Description		PKT_TYPE
592 
593 			Packet type:
594 			<enum 0 dot11a>802.11a PPDU type
595 			<enum 1 dot11b>802.11b PPDU type
596 			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
597 			<enum 3 dot11ac>802.11ac PPDU type
598 			<enum 4 dot11ax>802.11ax PPDU type
599 			<enum 5 dot11ba>802.11ba (WUR) PPDU type
600 			<enum 6 dot11be>802.11be PPDU type
601 			<enum 7 dot11az>802.11az (ranging) PPDU type
602 			<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
603 			 & aborted)
604 */
605 
606 #define RX_MSDU_START_PKT_TYPE_OFFSET                                               0x0000000000000010
607 #define RX_MSDU_START_PKT_TYPE_LSB                                                  40
608 #define RX_MSDU_START_PKT_TYPE_MSB                                                  43
609 #define RX_MSDU_START_PKT_TYPE_MASK                                                 0x00000f0000000000
610 
611 
612 /* Description		SGI
613 
614 			Field only valid when pkt type is HT, VHT or HE.
615 
616 			<enum 0     0_8_us_sgi > Legacy normal GI. Can also be used
617 			 for HE
618 			<enum 1     0_4_us_sgi > Legacy short GI. Can also be used
619 			 for HE
620 			<enum 2     1_6_us_sgi > HE related GI
621 			<enum 3     3_2_us_sgi > HE related GI
622 			<legal 0 - 3>
623 */
624 
625 #define RX_MSDU_START_SGI_OFFSET                                                    0x0000000000000010
626 #define RX_MSDU_START_SGI_LSB                                                       44
627 #define RX_MSDU_START_SGI_MSB                                                       45
628 #define RX_MSDU_START_SGI_MASK                                                      0x0000300000000000
629 
630 
631 /* Description		RATE_MCS
632 
633 			For details, refer to  MCS_TYPE description
634 			Note: This is "rate" in case of 11a/11b
635 
636 			<legal all>
637 */
638 
639 #define RX_MSDU_START_RATE_MCS_OFFSET                                               0x0000000000000010
640 #define RX_MSDU_START_RATE_MCS_LSB                                                  46
641 #define RX_MSDU_START_RATE_MCS_MSB                                                  49
642 #define RX_MSDU_START_RATE_MCS_MASK                                                 0x0003c00000000000
643 
644 
645 /* Description		RECEIVE_BANDWIDTH
646 
647 			Full receive Bandwidth
648 
649 			<enum 0 20_mhz>20 Mhz BW
650 			<enum 1 40_mhz>40 Mhz BW
651 			<enum 2 80_mhz>80 Mhz BW
652 			<enum 3 160_mhz>160 Mhz BW
653 			<enum 4 320_mhz>320 Mhz BW
654 			<enum 5 240_mhz>240 Mhz BW
655 */
656 
657 #define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET                                      0x0000000000000010
658 #define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB                                         50
659 #define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB                                         52
660 #define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK                                        0x001c000000000000
661 
662 
663 /* Description		RECEPTION_TYPE
664 
665 			Indicates what type of reception this is.
666 			<enum 0     reception_type_SU > Basic SU reception (not
667 			part of OFDMA or MIMO)
668 			<enum 1     reception_type_MU_MIMO > This is related to
669 			DL type of reception
670 			<enum 2     reception_type_MU_OFDMA >  This is related to
671 			 DL type of reception
672 			<enum 3     reception_type_MU_OFDMA_MIMO >  This is related
673 			 to DL type of reception
674 			<enum 4     reception_type_UL_MU_MIMO > This is related
675 			to UL type of reception
676 			<enum 5     reception_type_UL_MU_OFDMA >  This is related
677 			 to UL type of reception
678 			<enum 6     reception_type_UL_MU_OFDMA_MIMO >  This is related
679 			 to UL type of reception
680 
681 			<legal 0-6>
682 */
683 
684 #define RX_MSDU_START_RECEPTION_TYPE_OFFSET                                         0x0000000000000010
685 #define RX_MSDU_START_RECEPTION_TYPE_LSB                                            53
686 #define RX_MSDU_START_RECEPTION_TYPE_MSB                                            55
687 #define RX_MSDU_START_RECEPTION_TYPE_MASK                                           0x00e0000000000000
688 
689 
690 /* Description		MIMO_SS_BITMAP
691 
692 			Field only valid when Reception_type for the MPDU from this
693 			 STA is some form of MIMO reception
694 
695 			Bitmap, with each bit indicating if the related spatial
696 			stream is used for this STA
697 			LSB related to SS 0
698 
699 			0: spatial stream not used for this reception
700 			1: spatial stream used for this reception
701 
702 			<legal all>
703 */
704 
705 #define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET                                         0x0000000000000010
706 #define RX_MSDU_START_MIMO_SS_BITMAP_LSB                                            56
707 #define RX_MSDU_START_MIMO_SS_BITMAP_MSB                                            63
708 #define RX_MSDU_START_MIMO_SS_BITMAP_MASK                                           0xff00000000000000
709 
710 
711 /* Description		PPDU_START_TIMESTAMP_31_0
712 
713 			Timestamp that indicates when the PPDU that contained this
714 			 MPDU started on the medium, lower 32 bits
715 			<legal all>
716 */
717 
718 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000018
719 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
720 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
721 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
722 
723 
724 /* Description		PPDU_START_TIMESTAMP_63_32
725 
726 			Timestamp that indicates when the PPDU that contained this
727 			 MPDU started on the medium, upper 32 bits
728 			<legal all>
729 */
730 
731 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000018
732 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
733 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
734 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
735 
736 
737 /* Description		SW_PHY_META_DATA
738 
739 			SW programmed Meta data provided by the PHY.
740 
741 			Can be used for SW to indicate the channel the device is
742 			 on.
743 			<legal all>
744 */
745 
746 #define RX_MSDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000020
747 #define RX_MSDU_START_SW_PHY_META_DATA_LSB                                          0
748 #define RX_MSDU_START_SW_PHY_META_DATA_MSB                                          31
749 #define RX_MSDU_START_SW_PHY_META_DATA_MASK                                         0x00000000ffffffff
750 
751 
752 /* Description		VLAN_CTAG_CI
753 
754 			2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC
755 
756 */
757 
758 #define RX_MSDU_START_VLAN_CTAG_CI_OFFSET                                           0x0000000000000020
759 #define RX_MSDU_START_VLAN_CTAG_CI_LSB                                              32
760 #define RX_MSDU_START_VLAN_CTAG_CI_MSB                                              47
761 #define RX_MSDU_START_VLAN_CTAG_CI_MASK                                             0x0000ffff00000000
762 
763 
764 /* Description		VLAN_STAG_CI
765 
766 			2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC
767 			 in case of double VLAN
768 */
769 
770 #define RX_MSDU_START_VLAN_STAG_CI_OFFSET                                           0x0000000000000020
771 #define RX_MSDU_START_VLAN_STAG_CI_LSB                                              48
772 #define RX_MSDU_START_VLAN_STAG_CI_MSB                                              63
773 #define RX_MSDU_START_VLAN_STAG_CI_MASK                                             0xffff000000000000
774 
775 
776 
777 #endif   // RX_MSDU_START
778