1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_LINK_H_ 18 #define _RX_MSDU_LINK_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #include "buffer_addr_info.h" 24 #include "rx_msdu_details.h" 25 #define NUM_OF_DWORDS_RX_MSDU_LINK 32 26 27 28 struct rx_msdu_link { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_descriptor_header descriptor_header; 31 struct buffer_addr_info next_msdu_link_desc_addr_info; 32 uint32_t receive_queue_number : 16, // [15:0] 33 first_rx_msdu_link_struct : 1, // [16:16] 34 reserved_3a : 15; // [31:17] 35 uint32_t pn_31_0 : 32; // [31:0] 36 uint32_t pn_63_32 : 32; // [31:0] 37 uint32_t pn_95_64 : 32; // [31:0] 38 uint32_t pn_127_96 : 32; // [31:0] 39 struct rx_msdu_details msdu_0; 40 struct rx_msdu_details msdu_1; 41 struct rx_msdu_details msdu_2; 42 struct rx_msdu_details msdu_3; 43 struct rx_msdu_details msdu_4; 44 struct rx_msdu_details msdu_5; 45 #else 46 struct uniform_descriptor_header descriptor_header; 47 struct buffer_addr_info next_msdu_link_desc_addr_info; 48 uint32_t reserved_3a : 15, // [31:17] 49 first_rx_msdu_link_struct : 1, // [16:16] 50 receive_queue_number : 16; // [15:0] 51 uint32_t pn_31_0 : 32; // [31:0] 52 uint32_t pn_63_32 : 32; // [31:0] 53 uint32_t pn_95_64 : 32; // [31:0] 54 uint32_t pn_127_96 : 32; // [31:0] 55 struct rx_msdu_details msdu_0; 56 struct rx_msdu_details msdu_1; 57 struct rx_msdu_details msdu_2; 58 struct rx_msdu_details msdu_3; 59 struct rx_msdu_details msdu_4; 60 struct rx_msdu_details msdu_5; 61 #endif 62 }; 63 64 65 /* Description DESCRIPTOR_HEADER 66 67 Details about which module owns this struct. 68 Note that sub field "Buffer_type" shall be set to "Receive_MSDU_Link_descriptor" 69 70 */ 71 72 73 /* Description OWNER 74 75 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 76 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 77 78 The owner of this data structure: 79 <enum 0 WBM_owned> Buffer Manager currently owns this data 80 structure. 81 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 82 data structure. 83 <enum 2 TQM_owned> Transmit Queue Manager currently owns 84 this data structure. 85 <enum 3 RXDMA_owned> Receive DMA currently owns this data 86 structure. 87 <enum 4 REO_owned> Reorder currently owns this data structure. 88 89 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 90 91 92 <legal 0-5> 93 */ 94 95 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 96 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 97 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 98 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 99 100 101 /* Description BUFFER_TYPE 102 103 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 104 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 105 106 Field describing what contents format is of this descriptor 107 108 109 <enum 0 Transmit_MSDU_Link_descriptor> 110 <enum 1 Transmit_MPDU_Link_descriptor> 111 <enum 2 Transmit_MPDU_Queue_head_descriptor> 112 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 113 <enum 4 Transmit_flow_descriptor> 114 <enum 5 Transmit_buffer> NOT TO BE USED: 115 116 <enum 6 Receive_MSDU_Link_descriptor> 117 <enum 7 Receive_MPDU_Link_descriptor> 118 <enum 8 Receive_REO_queue_descriptor> 119 <enum 9 Receive_REO_queue_1k_descriptor> 120 <enum 10 Receive_REO_queue_ext_descriptor> 121 122 <enum 11 Receive_buffer> 123 124 <enum 12 Idle_link_list_entry> 125 126 <legal 0-12> 127 */ 128 129 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 130 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 131 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 132 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 133 134 135 /* Description TX_MPDU_QUEUE_NUMBER 136 137 Consumer: TQM/Debug 138 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 139 140 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 141 142 143 Indicates the MPDU queue ID to which this MPDU descriptor 144 belongs 145 Used for tracking and debugging 146 147 Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 148 word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 149 for this. 150 <legal all> 151 */ 152 153 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 154 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 155 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 156 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 157 158 159 /* Description RESERVED_0A 160 161 <legal 0> 162 */ 163 164 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 165 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 166 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 167 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 168 169 170 /* Description NEXT_MSDU_LINK_DESC_ADDR_INFO 171 172 Details of the physical address of the next MSDU link descriptor 173 that contains info about additional MSDUs that are part 174 of this MPDU. 175 */ 176 177 178 /* Description BUFFER_ADDR_31_0 179 180 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 181 descriptor OR Link Descriptor 182 183 In case of 'NULL' pointer, this field is set to 0 184 <legal all> 185 */ 186 187 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 188 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 189 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 190 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 191 192 193 /* Description BUFFER_ADDR_39_32 194 195 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 196 descriptor OR Link Descriptor 197 198 In case of 'NULL' pointer, this field is set to 0 199 <legal all> 200 */ 201 202 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 203 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 204 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 205 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 206 207 208 /* Description RETURN_BUFFER_MANAGER 209 210 Consumer: WBM 211 Producer: SW/FW 212 213 In case of 'NULL' pointer, this field is set to 0 214 215 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 216 descriptor OR link descriptor that is being pointed to 217 shall be returned after the frame has been processed. It 218 is used by WBM for routing purposes. 219 220 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 221 to the WMB buffer idle list 222 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 223 to the WBM idle link descriptor idle list, where the chip 224 0 WBM is chosen in case of a multi-chip config 225 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 226 to the chip 1 WBM idle link descriptor idle list 227 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 228 to the chip 2 WBM idle link descriptor idle list 229 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 230 returned to chip 3 WBM idle link descriptor idle list 231 <enum 4 FW_BM> This buffer shall be returned to the FW 232 <enum 5 SW0_BM> This buffer shall be returned to the SW, 233 ring 0 234 <enum 6 SW1_BM> This buffer shall be returned to the SW, 235 ring 1 236 <enum 7 SW2_BM> This buffer shall be returned to the SW, 237 ring 2 238 <enum 8 SW3_BM> This buffer shall be returned to the SW, 239 ring 3 240 <enum 9 SW4_BM> This buffer shall be returned to the SW, 241 ring 4 242 <enum 10 SW5_BM> This buffer shall be returned to the SW, 243 ring 5 244 <enum 11 SW6_BM> This buffer shall be returned to the SW, 245 ring 6 246 247 <legal 0-12> 248 */ 249 250 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 251 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 252 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 253 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 254 255 256 /* Description SW_BUFFER_COOKIE 257 258 Cookie field exclusively used by SW. 259 260 In case of 'NULL' pointer, this field is set to 0 261 262 HW ignores the contents, accept that it passes the programmed 263 value on to other descriptors together with the physical 264 address 265 266 Field can be used by SW to for example associate the buffers 267 physical address with the virtual address 268 The bit definitions as used by SW are within SW HLD specification 269 270 271 NOTE1: 272 The three most significant bits can have a special meaning 273 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 274 and field transmit_bw_restriction is set 275 276 In case of NON punctured transmission: 277 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 278 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 279 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 280 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 281 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 282 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 283 Sw_buffer_cookie[19:18] = 2'b11: reserved 284 285 In case of punctured transmission: 286 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 287 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 288 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 289 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 290 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 291 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 292 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 293 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 294 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 295 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 296 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 297 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 298 Sw_buffer_cookie[19:18] = 2'b11: reserved 299 300 Note: a punctured transmission is indicated by the presence 301 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 302 303 <legal all> 304 */ 305 306 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 307 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 308 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 309 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 310 311 312 /* Description RECEIVE_QUEUE_NUMBER 313 314 Indicates the Receive queue to which this MPDU descriptor 315 belongs 316 Used for tracking, finding bugs and debugging. 317 <legal all> 318 */ 319 320 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 321 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 322 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 323 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 324 325 326 /* Description FIRST_RX_MSDU_LINK_STRUCT 327 328 When set, this RX_MSDU_link descriptor is the first one 329 in the MSDU link list. Field MSDU_0 points to the very first 330 MSDU buffer descriptor in the MPDU 331 <legal all> 332 */ 333 334 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c 335 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 336 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 337 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 338 339 340 /* Description RESERVED_3A 341 342 <legal 0> 343 */ 344 345 #define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c 346 #define RX_MSDU_LINK_RESERVED_3A_LSB 17 347 #define RX_MSDU_LINK_RESERVED_3A_MSB 31 348 #define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 349 350 351 /* Description PN_31_0 352 353 Field only valid when First_RX_MSDU_link_struct is set. 354 355 356 31-0 bits of the 256-bit packet number bitmap. 357 <legal all> 358 */ 359 360 #define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 361 #define RX_MSDU_LINK_PN_31_0_LSB 0 362 #define RX_MSDU_LINK_PN_31_0_MSB 31 363 #define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff 364 365 366 /* Description PN_63_32 367 368 Field only valid when First_RX_MSDU_link_struct is set. 369 370 371 63-32 bits of the 256-bit packet number bitmap. 372 <legal all> 373 */ 374 375 #define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 376 #define RX_MSDU_LINK_PN_63_32_LSB 0 377 #define RX_MSDU_LINK_PN_63_32_MSB 31 378 #define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff 379 380 381 /* Description PN_95_64 382 383 Field only valid when First_RX_MSDU_link_struct is set. 384 385 386 95-64 bits of the 256-bit packet number bitmap. 387 <legal all> 388 */ 389 390 #define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 391 #define RX_MSDU_LINK_PN_95_64_LSB 0 392 #define RX_MSDU_LINK_PN_95_64_MSB 31 393 #define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff 394 395 396 /* Description PN_127_96 397 398 Field only valid when First_RX_MSDU_link_struct is set. 399 400 401 127-96 bits of the 256-bit packet number bitmap. 402 <legal all> 403 */ 404 405 #define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c 406 #define RX_MSDU_LINK_PN_127_96_LSB 0 407 #define RX_MSDU_LINK_PN_127_96_MSB 31 408 #define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff 409 410 411 /* Description MSDU_0 412 413 When First_RX_MSDU_link_struct is set, this MSDU is the 414 first in the MPDU 415 416 When First_RX_MSDU_link_struct is NOT set, this MSDU follows 417 the last MSDU in the previous RX_MSDU_link data structure 418 419 */ 420 421 422 /* Description BUFFER_ADDR_INFO_DETAILS 423 424 Consumer: REO/SW 425 Producer: RXDMA 426 427 Details of the physical address of the buffer containing 428 an MSDU (or entire MPDU) 429 */ 430 431 432 /* Description BUFFER_ADDR_31_0 433 434 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 435 descriptor OR Link Descriptor 436 437 In case of 'NULL' pointer, this field is set to 0 438 <legal all> 439 */ 440 441 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 442 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 443 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 444 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 445 446 447 /* Description BUFFER_ADDR_39_32 448 449 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 450 descriptor OR Link Descriptor 451 452 In case of 'NULL' pointer, this field is set to 0 453 <legal all> 454 */ 455 456 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 457 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 458 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 459 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 460 461 462 /* Description RETURN_BUFFER_MANAGER 463 464 Consumer: WBM 465 Producer: SW/FW 466 467 In case of 'NULL' pointer, this field is set to 0 468 469 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 470 descriptor OR link descriptor that is being pointed to 471 shall be returned after the frame has been processed. It 472 is used by WBM for routing purposes. 473 474 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 475 to the WMB buffer idle list 476 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 477 to the WBM idle link descriptor idle list, where the chip 478 0 WBM is chosen in case of a multi-chip config 479 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 480 to the chip 1 WBM idle link descriptor idle list 481 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 482 to the chip 2 WBM idle link descriptor idle list 483 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 484 returned to chip 3 WBM idle link descriptor idle list 485 <enum 4 FW_BM> This buffer shall be returned to the FW 486 <enum 5 SW0_BM> This buffer shall be returned to the SW, 487 ring 0 488 <enum 6 SW1_BM> This buffer shall be returned to the SW, 489 ring 1 490 <enum 7 SW2_BM> This buffer shall be returned to the SW, 491 ring 2 492 <enum 8 SW3_BM> This buffer shall be returned to the SW, 493 ring 3 494 <enum 9 SW4_BM> This buffer shall be returned to the SW, 495 ring 4 496 <enum 10 SW5_BM> This buffer shall be returned to the SW, 497 ring 5 498 <enum 11 SW6_BM> This buffer shall be returned to the SW, 499 ring 6 500 501 <legal 0-12> 502 */ 503 504 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 505 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 506 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 507 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 508 509 510 /* Description SW_BUFFER_COOKIE 511 512 Cookie field exclusively used by SW. 513 514 In case of 'NULL' pointer, this field is set to 0 515 516 HW ignores the contents, accept that it passes the programmed 517 value on to other descriptors together with the physical 518 address 519 520 Field can be used by SW to for example associate the buffers 521 physical address with the virtual address 522 The bit definitions as used by SW are within SW HLD specification 523 524 525 NOTE1: 526 The three most significant bits can have a special meaning 527 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 528 and field transmit_bw_restriction is set 529 530 In case of NON punctured transmission: 531 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 532 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 533 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 534 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 535 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 536 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 537 Sw_buffer_cookie[19:18] = 2'b11: reserved 538 539 In case of punctured transmission: 540 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 541 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 542 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 543 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 544 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 545 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 546 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 547 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 548 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 549 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 550 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 551 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 552 Sw_buffer_cookie[19:18] = 2'b11: reserved 553 554 Note: a punctured transmission is indicated by the presence 555 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 556 557 <legal all> 558 */ 559 560 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 561 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 562 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 563 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 564 565 566 /* Description RX_MSDU_DESC_INFO_DETAILS 567 568 Consumer: REO/SW 569 Producer: RXDMA 570 571 General information related to the MSDU that should be passed 572 on from RXDMA all the way to to the REO destination ring. 573 574 */ 575 576 577 /* Description FIRST_MSDU_IN_MPDU_FLAG 578 579 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 580 multiple buffers, this field will be valid in the Last 581 buffer used by the MSDU 582 583 <enum 0 Not_first_msdu> This is not the first MSDU in the 584 MPDU. 585 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 586 587 588 <legal all> 589 */ 590 591 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 592 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 593 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 594 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 595 596 597 /* Description LAST_MSDU_IN_MPDU_FLAG 598 599 Consumer: WBM/REO/SW/FW 600 Producer: RXDMA 601 602 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 603 multiple buffers, this field will be valid in the Last 604 buffer used by the MSDU 605 606 <enum 0 Not_last_msdu> There are more MSDUs linked to this 607 MSDU that belongs to this MPDU 608 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 609 This setting is only allowed in combination with 'Msdu_continuation' 610 set to 0. This implies that when an msdu is spread out over 611 multiple buffers and thus msdu_continuation is set, only 612 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 613 be set. 614 615 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 616 are set, the MPDU that this MSDU belongs to only contains 617 a single MSDU. 618 619 620 <legal all> 621 */ 622 623 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 624 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 625 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 626 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 627 628 629 /* Description MSDU_CONTINUATION 630 631 When set, this MSDU buffer was not able to hold the entire 632 MSDU. The next buffer will therefor contain additional 633 information related to this MSDU. 634 635 <legal all> 636 */ 637 638 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 639 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 640 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 641 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 642 643 644 /* Description MSDU_LENGTH 645 646 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 647 multiple buffers, this field will be valid in the First 648 buffer used by MSDU. 649 650 Full MSDU length in bytes after decapsulation. 651 652 This field is still valid for MPDU frames without A-MSDU. 653 It still represents MSDU length after decapsulation 654 655 Or in case of RAW MPDUs, it indicates the length of the 656 entire MPDU (without FCS field) 657 <legal all> 658 */ 659 660 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 661 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 662 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 663 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 664 665 666 /* Description MSDU_DROP 667 668 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 669 multiple buffers, this field will be valid in the Last 670 buffer used by the MSDU 671 672 When set, REO shall drop this MSDU and not forward it to 673 any other ring... 674 <legal all> 675 */ 676 677 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 678 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 679 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 680 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 681 682 683 /* Description SA_IS_VALID 684 685 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 686 multiple buffers, this field will be valid in the Last 687 buffer used by the MSDU 688 689 Indicates that OLE found a valid SA entry for this MSDU 690 <legal all> 691 */ 692 693 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 694 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 695 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 696 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 697 698 699 /* Description DA_IS_VALID 700 701 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 702 multiple buffers, this field will be valid in the Last 703 buffer used by the MSDU 704 705 Indicates that OLE found a valid DA entry for this MSDU 706 <legal all> 707 */ 708 709 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 710 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 711 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 712 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 713 714 715 /* Description DA_IS_MCBC 716 717 Field Only valid if "da_is_valid" is set 718 719 Indicates the DA address was a Multicast of Broadcast address 720 for this MSDU 721 <legal all> 722 */ 723 724 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 725 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 726 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 727 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 728 729 730 /* Description L3_HEADER_PADDING_MSB 731 732 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 733 as the LSB is always zero) 734 Number of bytes padded to make sure that the L3 header will 735 always start of a Dword boundary 736 <legal all> 737 */ 738 739 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 740 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 741 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 742 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 743 744 745 /* Description TCP_UDP_CHKSUM_FAIL 746 747 Passed on from 'RX_ATTENTION' TLV 748 Indicates that the computed checksum did not match the checksum 749 in the TCP/UDP header. 750 <legal all> 751 */ 752 753 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 754 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 755 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 756 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 757 758 759 /* Description IP_CHKSUM_FAIL 760 761 Passed on from 'RX_ATTENTION' TLV 762 Indicates that the computed checksum did not match the checksum 763 in the IP header. 764 <legal all> 765 */ 766 767 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 768 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 769 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 770 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 771 772 773 /* Description FR_DS 774 775 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 776 TLV 777 Set if the 'from DS' bit is set in the frame control. 778 <legal all> 779 */ 780 781 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 782 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 783 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 784 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 785 786 787 /* Description TO_DS 788 789 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 790 TLV 791 Set if the 'to DS' bit is set in the frame control. 792 <legal all> 793 */ 794 795 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 796 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 797 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 798 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 799 800 801 /* Description INTRA_BSS 802 803 This packet needs intra-BSS routing by SW as the 'vdev_id' 804 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 805 that this MSDU was got in. 806 807 <legal all> 808 */ 809 810 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 811 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 812 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 813 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 814 815 816 /* Description DEST_CHIP_ID 817 818 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 819 to support intra-BSS routing with multi-chip multi-link 820 operation. 821 822 This indicates into which chip's TCL the packet should be 823 queued. 824 825 <legal all> 826 */ 827 828 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 829 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 830 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 831 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 832 833 834 /* Description DECAP_FORMAT 835 836 Indicates the format after decapsulation: 837 838 <enum 0 RAW> No encapsulation 839 <enum 1 Native_WiFi> 840 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 841 842 <enum 3 802_3> Indicate Ethernet 843 844 <legal all> 845 */ 846 847 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 848 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 849 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 850 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 851 852 853 /* Description DEST_CHIP_PMAC_ID 854 855 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 856 to support intra-BSS routing with multi-chip multi-link 857 operation. 858 859 This indicates into which link/'vdev' the packet should 860 be queued in TCL. 861 862 <legal all> 863 */ 864 865 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000028 866 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 867 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 868 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 869 870 871 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 872 873 Consumer: REO/SW 874 Producer: RXDMA 875 876 Extended information related to the MSDU that is passed 877 on from RXDMA to REO but not part of the REO destination 878 ring. Some fields are passed on to PPE. 879 */ 880 881 882 /* Description REO_DESTINATION_INDICATION 883 884 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 885 multiple buffers, this field will be valid in the Last 886 buffer used by the MSDU 887 888 The ID of the REO exit ring where the MSDU frame shall push 889 after (MPDU level) reordering has finished. 890 891 <enum 0 reo_destination_sw0> Reo will push the frame into 892 the REO2SW0 ring 893 <enum 1 reo_destination_sw1> Reo will push the frame into 894 the REO2SW1 ring 895 <enum 2 reo_destination_sw2> Reo will push the frame into 896 the REO2SW2 ring 897 <enum 3 reo_destination_sw3> Reo will push the frame into 898 the REO2SW3 ring 899 <enum 4 reo_destination_sw4> Reo will push the frame into 900 the REO2SW4 ring 901 <enum 5 reo_destination_release> Reo will push the frame 902 into the REO_release ring 903 <enum 6 reo_destination_fw> Reo will push the frame into 904 the REO2FW ring 905 <enum 7 reo_destination_sw5> Reo will push the frame into 906 the REO2SW5 ring (REO remaps this in chips without REO2SW5 907 ring, e.g. Pine) 908 <enum 8 reo_destination_sw6> Reo will push the frame into 909 the REO2SW6 ring (REO remaps this in chips without REO2SW6 910 ring, e.g. Pine) 911 <enum 9 reo_destination_sw7> Reo will push the frame into 912 the REO2SW7 ring (REO remaps this in chips without REO2SW7 913 ring) 914 <enum 10 reo_destination_sw8> Reo will push the frame into 915 the REO2SW8 ring (REO remaps this in chips without REO2SW8 916 ring) 917 <enum 11 reo_destination_11> REO remaps this 918 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 919 REO remaps this 920 <enum 14 reo_destination_14> REO remaps this 921 <enum 15 reo_destination_15> REO remaps this 922 <enum 16 reo_destination_16> REO remaps this 923 <enum 17 reo_destination_17> REO remaps this 924 <enum 18 reo_destination_18> REO remaps this 925 <enum 19 reo_destination_19> REO remaps this 926 <enum 20 reo_destination_20> REO remaps this 927 <enum 21 reo_destination_21> REO remaps this 928 <enum 22 reo_destination_22> REO remaps this 929 <enum 23 reo_destination_23> REO remaps this 930 <enum 24 reo_destination_24> REO remaps this 931 <enum 25 reo_destination_25> REO remaps this 932 <enum 26 reo_destination_26> REO remaps this 933 <enum 27 reo_destination_27> REO remaps this 934 <enum 28 reo_destination_28> REO remaps this 935 <enum 29 reo_destination_29> REO remaps this 936 <enum 30 reo_destination_30> REO remaps this 937 <enum 31 reo_destination_31> REO remaps this 938 939 <legal all> 940 */ 941 942 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c 943 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 944 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 945 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 946 947 948 /* Description SERVICE_CODE 949 950 Opaque service code between PPE and Wi-Fi 951 952 This field gets passed on by REO to PPE in the EDMA descriptor 953 ('REO_TO_PPE_RING'). 954 955 <legal all> 956 */ 957 958 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c 959 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 960 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 961 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 962 963 964 /* Description PRIORITY_VALID 965 966 This field gets passed on by REO to PPE in the EDMA descriptor 967 ('REO_TO_PPE_RING'). 968 969 <legal all> 970 */ 971 972 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c 973 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 974 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 975 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 976 977 978 /* Description DATA_OFFSET 979 980 The offset to Rx packet data within the buffer (including 981 Rx DMA offset programming and L3 header padding inserted 982 by Rx OLE). 983 984 This field gets passed on by REO to PPE in the EDMA descriptor 985 ('REO_TO_PPE_RING'). 986 987 <legal all> 988 */ 989 990 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c 991 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 992 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 993 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 994 995 996 /* Description SRC_LINK_ID 997 998 Consumer: SW 999 Producer: RXDMA 1000 1001 Set to the link ID of the PMAC that received the frame 1002 <legal all> 1003 */ 1004 1005 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c 1006 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 1007 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 1008 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 1009 1010 1011 /* Description RESERVED_0A 1012 1013 <legal 0> 1014 */ 1015 1016 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c 1017 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 1018 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 1019 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 1020 1021 1022 /* Description MSDU_1 1023 1024 Details of next MSDU in this (MSDU flow) linked list 1025 */ 1026 1027 1028 /* Description BUFFER_ADDR_INFO_DETAILS 1029 1030 Consumer: REO/SW 1031 Producer: RXDMA 1032 1033 Details of the physical address of the buffer containing 1034 an MSDU (or entire MPDU) 1035 */ 1036 1037 1038 /* Description BUFFER_ADDR_31_0 1039 1040 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1041 descriptor OR Link Descriptor 1042 1043 In case of 'NULL' pointer, this field is set to 0 1044 <legal all> 1045 */ 1046 1047 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 1048 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1049 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 1050 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1051 1052 1053 /* Description BUFFER_ADDR_39_32 1054 1055 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1056 descriptor OR Link Descriptor 1057 1058 In case of 'NULL' pointer, this field is set to 0 1059 <legal all> 1060 */ 1061 1062 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 1063 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1064 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 1065 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1066 1067 1068 /* Description RETURN_BUFFER_MANAGER 1069 1070 Consumer: WBM 1071 Producer: SW/FW 1072 1073 In case of 'NULL' pointer, this field is set to 0 1074 1075 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1076 descriptor OR link descriptor that is being pointed to 1077 shall be returned after the frame has been processed. It 1078 is used by WBM for routing purposes. 1079 1080 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1081 to the WMB buffer idle list 1082 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1083 to the WBM idle link descriptor idle list, where the chip 1084 0 WBM is chosen in case of a multi-chip config 1085 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1086 to the chip 1 WBM idle link descriptor idle list 1087 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1088 to the chip 2 WBM idle link descriptor idle list 1089 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1090 returned to chip 3 WBM idle link descriptor idle list 1091 <enum 4 FW_BM> This buffer shall be returned to the FW 1092 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1093 ring 0 1094 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1095 ring 1 1096 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1097 ring 2 1098 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1099 ring 3 1100 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1101 ring 4 1102 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1103 ring 5 1104 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1105 ring 6 1106 1107 <legal 0-12> 1108 */ 1109 1110 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1111 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1112 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 1113 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1114 1115 1116 /* Description SW_BUFFER_COOKIE 1117 1118 Cookie field exclusively used by SW. 1119 1120 In case of 'NULL' pointer, this field is set to 0 1121 1122 HW ignores the contents, accept that it passes the programmed 1123 value on to other descriptors together with the physical 1124 address 1125 1126 Field can be used by SW to for example associate the buffers 1127 physical address with the virtual address 1128 The bit definitions as used by SW are within SW HLD specification 1129 1130 1131 NOTE1: 1132 The three most significant bits can have a special meaning 1133 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1134 and field transmit_bw_restriction is set 1135 1136 In case of NON punctured transmission: 1137 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1138 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1139 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1140 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1141 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1142 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1143 Sw_buffer_cookie[19:18] = 2'b11: reserved 1144 1145 In case of punctured transmission: 1146 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1147 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1148 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1149 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1150 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1151 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1152 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1153 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1154 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1155 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1156 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1157 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1158 Sw_buffer_cookie[19:18] = 2'b11: reserved 1159 1160 Note: a punctured transmission is indicated by the presence 1161 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1162 1163 <legal all> 1164 */ 1165 1166 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 1167 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 1168 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 1169 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 1170 1171 1172 /* Description RX_MSDU_DESC_INFO_DETAILS 1173 1174 Consumer: REO/SW 1175 Producer: RXDMA 1176 1177 General information related to the MSDU that should be passed 1178 on from RXDMA all the way to to the REO destination ring. 1179 1180 */ 1181 1182 1183 /* Description FIRST_MSDU_IN_MPDU_FLAG 1184 1185 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1186 multiple buffers, this field will be valid in the Last 1187 buffer used by the MSDU 1188 1189 <enum 0 Not_first_msdu> This is not the first MSDU in the 1190 MPDU. 1191 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 1192 1193 1194 <legal all> 1195 */ 1196 1197 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1198 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1199 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 1200 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1201 1202 1203 /* Description LAST_MSDU_IN_MPDU_FLAG 1204 1205 Consumer: WBM/REO/SW/FW 1206 Producer: RXDMA 1207 1208 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1209 multiple buffers, this field will be valid in the Last 1210 buffer used by the MSDU 1211 1212 <enum 0 Not_last_msdu> There are more MSDUs linked to this 1213 MSDU that belongs to this MPDU 1214 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 1215 This setting is only allowed in combination with 'Msdu_continuation' 1216 set to 0. This implies that when an msdu is spread out over 1217 multiple buffers and thus msdu_continuation is set, only 1218 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 1219 be set. 1220 1221 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 1222 are set, the MPDU that this MSDU belongs to only contains 1223 a single MSDU. 1224 1225 1226 <legal all> 1227 */ 1228 1229 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1230 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1231 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 1232 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1233 1234 1235 /* Description MSDU_CONTINUATION 1236 1237 When set, this MSDU buffer was not able to hold the entire 1238 MSDU. The next buffer will therefor contain additional 1239 information related to this MSDU. 1240 1241 <legal all> 1242 */ 1243 1244 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 1245 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1246 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 1247 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1248 1249 1250 /* Description MSDU_LENGTH 1251 1252 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 1253 multiple buffers, this field will be valid in the First 1254 buffer used by MSDU. 1255 1256 Full MSDU length in bytes after decapsulation. 1257 1258 This field is still valid for MPDU frames without A-MSDU. 1259 It still represents MSDU length after decapsulation 1260 1261 Or in case of RAW MPDUs, it indicates the length of the 1262 entire MPDU (without FCS field) 1263 <legal all> 1264 */ 1265 1266 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 1267 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1268 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 1269 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1270 1271 1272 /* Description MSDU_DROP 1273 1274 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1275 multiple buffers, this field will be valid in the Last 1276 buffer used by the MSDU 1277 1278 When set, REO shall drop this MSDU and not forward it to 1279 any other ring... 1280 <legal all> 1281 */ 1282 1283 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 1284 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 1285 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 1286 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 1287 1288 1289 /* Description SA_IS_VALID 1290 1291 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1292 multiple buffers, this field will be valid in the Last 1293 buffer used by the MSDU 1294 1295 Indicates that OLE found a valid SA entry for this MSDU 1296 <legal all> 1297 */ 1298 1299 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 1300 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 1301 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 1302 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 1303 1304 1305 /* Description DA_IS_VALID 1306 1307 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1308 multiple buffers, this field will be valid in the Last 1309 buffer used by the MSDU 1310 1311 Indicates that OLE found a valid DA entry for this MSDU 1312 <legal all> 1313 */ 1314 1315 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 1316 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 1317 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 1318 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 1319 1320 1321 /* Description DA_IS_MCBC 1322 1323 Field Only valid if "da_is_valid" is set 1324 1325 Indicates the DA address was a Multicast of Broadcast address 1326 for this MSDU 1327 <legal all> 1328 */ 1329 1330 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 1331 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 1332 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 1333 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 1334 1335 1336 /* Description L3_HEADER_PADDING_MSB 1337 1338 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 1339 as the LSB is always zero) 1340 Number of bytes padded to make sure that the L3 header will 1341 always start of a Dword boundary 1342 <legal all> 1343 */ 1344 1345 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 1346 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 1347 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 1348 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 1349 1350 1351 /* Description TCP_UDP_CHKSUM_FAIL 1352 1353 Passed on from 'RX_ATTENTION' TLV 1354 Indicates that the computed checksum did not match the checksum 1355 in the TCP/UDP header. 1356 <legal all> 1357 */ 1358 1359 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 1360 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 1361 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 1362 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 1363 1364 1365 /* Description IP_CHKSUM_FAIL 1366 1367 Passed on from 'RX_ATTENTION' TLV 1368 Indicates that the computed checksum did not match the checksum 1369 in the IP header. 1370 <legal all> 1371 */ 1372 1373 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 1374 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 1375 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 1376 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 1377 1378 1379 /* Description FR_DS 1380 1381 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1382 TLV 1383 Set if the 'from DS' bit is set in the frame control. 1384 <legal all> 1385 */ 1386 1387 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 1388 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 1389 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 1390 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 1391 1392 1393 /* Description TO_DS 1394 1395 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1396 TLV 1397 Set if the 'to DS' bit is set in the frame control. 1398 <legal all> 1399 */ 1400 1401 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 1402 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 1403 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 1404 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 1405 1406 1407 /* Description INTRA_BSS 1408 1409 This packet needs intra-BSS routing by SW as the 'vdev_id' 1410 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 1411 that this MSDU was got in. 1412 1413 <legal all> 1414 */ 1415 1416 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 1417 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 1418 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 1419 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 1420 1421 1422 /* Description DEST_CHIP_ID 1423 1424 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 1425 to support intra-BSS routing with multi-chip multi-link 1426 operation. 1427 1428 This indicates into which chip's TCL the packet should be 1429 queued. 1430 1431 <legal all> 1432 */ 1433 1434 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 1435 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 1436 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 1437 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 1438 1439 1440 /* Description DECAP_FORMAT 1441 1442 Indicates the format after decapsulation: 1443 1444 <enum 0 RAW> No encapsulation 1445 <enum 1 Native_WiFi> 1446 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1447 1448 <enum 3 802_3> Indicate Ethernet 1449 1450 <legal all> 1451 */ 1452 1453 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 1454 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 1455 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 1456 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 1457 1458 1459 /* Description DEST_CHIP_PMAC_ID 1460 1461 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 1462 to support intra-BSS routing with multi-chip multi-link 1463 operation. 1464 1465 This indicates into which link/'vdev' the packet should 1466 be queued in TCL. 1467 1468 <legal all> 1469 */ 1470 1471 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000038 1472 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 1473 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 1474 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 1475 1476 1477 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 1478 1479 Consumer: REO/SW 1480 Producer: RXDMA 1481 1482 Extended information related to the MSDU that is passed 1483 on from RXDMA to REO but not part of the REO destination 1484 ring. Some fields are passed on to PPE. 1485 */ 1486 1487 1488 /* Description REO_DESTINATION_INDICATION 1489 1490 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1491 multiple buffers, this field will be valid in the Last 1492 buffer used by the MSDU 1493 1494 The ID of the REO exit ring where the MSDU frame shall push 1495 after (MPDU level) reordering has finished. 1496 1497 <enum 0 reo_destination_sw0> Reo will push the frame into 1498 the REO2SW0 ring 1499 <enum 1 reo_destination_sw1> Reo will push the frame into 1500 the REO2SW1 ring 1501 <enum 2 reo_destination_sw2> Reo will push the frame into 1502 the REO2SW2 ring 1503 <enum 3 reo_destination_sw3> Reo will push the frame into 1504 the REO2SW3 ring 1505 <enum 4 reo_destination_sw4> Reo will push the frame into 1506 the REO2SW4 ring 1507 <enum 5 reo_destination_release> Reo will push the frame 1508 into the REO_release ring 1509 <enum 6 reo_destination_fw> Reo will push the frame into 1510 the REO2FW ring 1511 <enum 7 reo_destination_sw5> Reo will push the frame into 1512 the REO2SW5 ring (REO remaps this in chips without REO2SW5 1513 ring, e.g. Pine) 1514 <enum 8 reo_destination_sw6> Reo will push the frame into 1515 the REO2SW6 ring (REO remaps this in chips without REO2SW6 1516 ring, e.g. Pine) 1517 <enum 9 reo_destination_sw7> Reo will push the frame into 1518 the REO2SW7 ring (REO remaps this in chips without REO2SW7 1519 ring) 1520 <enum 10 reo_destination_sw8> Reo will push the frame into 1521 the REO2SW8 ring (REO remaps this in chips without REO2SW8 1522 ring) 1523 <enum 11 reo_destination_11> REO remaps this 1524 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 1525 REO remaps this 1526 <enum 14 reo_destination_14> REO remaps this 1527 <enum 15 reo_destination_15> REO remaps this 1528 <enum 16 reo_destination_16> REO remaps this 1529 <enum 17 reo_destination_17> REO remaps this 1530 <enum 18 reo_destination_18> REO remaps this 1531 <enum 19 reo_destination_19> REO remaps this 1532 <enum 20 reo_destination_20> REO remaps this 1533 <enum 21 reo_destination_21> REO remaps this 1534 <enum 22 reo_destination_22> REO remaps this 1535 <enum 23 reo_destination_23> REO remaps this 1536 <enum 24 reo_destination_24> REO remaps this 1537 <enum 25 reo_destination_25> REO remaps this 1538 <enum 26 reo_destination_26> REO remaps this 1539 <enum 27 reo_destination_27> REO remaps this 1540 <enum 28 reo_destination_28> REO remaps this 1541 <enum 29 reo_destination_29> REO remaps this 1542 <enum 30 reo_destination_30> REO remaps this 1543 <enum 31 reo_destination_31> REO remaps this 1544 1545 <legal all> 1546 */ 1547 1548 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c 1549 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 1550 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 1551 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 1552 1553 1554 /* Description SERVICE_CODE 1555 1556 Opaque service code between PPE and Wi-Fi 1557 1558 This field gets passed on by REO to PPE in the EDMA descriptor 1559 ('REO_TO_PPE_RING'). 1560 1561 <legal all> 1562 */ 1563 1564 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c 1565 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 1566 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 1567 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 1568 1569 1570 /* Description PRIORITY_VALID 1571 1572 This field gets passed on by REO to PPE in the EDMA descriptor 1573 ('REO_TO_PPE_RING'). 1574 1575 <legal all> 1576 */ 1577 1578 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c 1579 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 1580 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 1581 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 1582 1583 1584 /* Description DATA_OFFSET 1585 1586 The offset to Rx packet data within the buffer (including 1587 Rx DMA offset programming and L3 header padding inserted 1588 by Rx OLE). 1589 1590 This field gets passed on by REO to PPE in the EDMA descriptor 1591 ('REO_TO_PPE_RING'). 1592 1593 <legal all> 1594 */ 1595 1596 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c 1597 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 1598 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 1599 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 1600 1601 1602 /* Description SRC_LINK_ID 1603 1604 Consumer: SW 1605 Producer: RXDMA 1606 1607 Set to the link ID of the PMAC that received the frame 1608 <legal all> 1609 */ 1610 1611 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c 1612 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 1613 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 1614 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 1615 1616 1617 /* Description RESERVED_0A 1618 1619 <legal 0> 1620 */ 1621 1622 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c 1623 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 1624 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 1625 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 1626 1627 1628 /* Description MSDU_2 1629 1630 Details of next MSDU in this (MSDU flow) linked list 1631 */ 1632 1633 1634 /* Description BUFFER_ADDR_INFO_DETAILS 1635 1636 Consumer: REO/SW 1637 Producer: RXDMA 1638 1639 Details of the physical address of the buffer containing 1640 an MSDU (or entire MPDU) 1641 */ 1642 1643 1644 /* Description BUFFER_ADDR_31_0 1645 1646 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1647 descriptor OR Link Descriptor 1648 1649 In case of 'NULL' pointer, this field is set to 0 1650 <legal all> 1651 */ 1652 1653 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 1654 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1655 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 1656 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1657 1658 1659 /* Description BUFFER_ADDR_39_32 1660 1661 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1662 descriptor OR Link Descriptor 1663 1664 In case of 'NULL' pointer, this field is set to 0 1665 <legal all> 1666 */ 1667 1668 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 1669 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1670 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 1671 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1672 1673 1674 /* Description RETURN_BUFFER_MANAGER 1675 1676 Consumer: WBM 1677 Producer: SW/FW 1678 1679 In case of 'NULL' pointer, this field is set to 0 1680 1681 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1682 descriptor OR link descriptor that is being pointed to 1683 shall be returned after the frame has been processed. It 1684 is used by WBM for routing purposes. 1685 1686 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1687 to the WMB buffer idle list 1688 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1689 to the WBM idle link descriptor idle list, where the chip 1690 0 WBM is chosen in case of a multi-chip config 1691 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1692 to the chip 1 WBM idle link descriptor idle list 1693 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1694 to the chip 2 WBM idle link descriptor idle list 1695 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1696 returned to chip 3 WBM idle link descriptor idle list 1697 <enum 4 FW_BM> This buffer shall be returned to the FW 1698 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1699 ring 0 1700 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1701 ring 1 1702 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1703 ring 2 1704 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1705 ring 3 1706 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1707 ring 4 1708 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1709 ring 5 1710 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1711 ring 6 1712 1713 <legal 0-12> 1714 */ 1715 1716 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1717 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1718 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 1719 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1720 1721 1722 /* Description SW_BUFFER_COOKIE 1723 1724 Cookie field exclusively used by SW. 1725 1726 In case of 'NULL' pointer, this field is set to 0 1727 1728 HW ignores the contents, accept that it passes the programmed 1729 value on to other descriptors together with the physical 1730 address 1731 1732 Field can be used by SW to for example associate the buffers 1733 physical address with the virtual address 1734 The bit definitions as used by SW are within SW HLD specification 1735 1736 1737 NOTE1: 1738 The three most significant bits can have a special meaning 1739 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1740 and field transmit_bw_restriction is set 1741 1742 In case of NON punctured transmission: 1743 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1744 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1745 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1746 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1747 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1748 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1749 Sw_buffer_cookie[19:18] = 2'b11: reserved 1750 1751 In case of punctured transmission: 1752 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1753 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1754 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1755 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1756 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1757 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1758 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1759 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1760 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1761 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1762 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1763 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1764 Sw_buffer_cookie[19:18] = 2'b11: reserved 1765 1766 Note: a punctured transmission is indicated by the presence 1767 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1768 1769 <legal all> 1770 */ 1771 1772 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 1773 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 1774 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 1775 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 1776 1777 1778 /* Description RX_MSDU_DESC_INFO_DETAILS 1779 1780 Consumer: REO/SW 1781 Producer: RXDMA 1782 1783 General information related to the MSDU that should be passed 1784 on from RXDMA all the way to to the REO destination ring. 1785 1786 */ 1787 1788 1789 /* Description FIRST_MSDU_IN_MPDU_FLAG 1790 1791 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1792 multiple buffers, this field will be valid in the Last 1793 buffer used by the MSDU 1794 1795 <enum 0 Not_first_msdu> This is not the first MSDU in the 1796 MPDU. 1797 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 1798 1799 1800 <legal all> 1801 */ 1802 1803 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1804 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1805 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 1806 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1807 1808 1809 /* Description LAST_MSDU_IN_MPDU_FLAG 1810 1811 Consumer: WBM/REO/SW/FW 1812 Producer: RXDMA 1813 1814 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1815 multiple buffers, this field will be valid in the Last 1816 buffer used by the MSDU 1817 1818 <enum 0 Not_last_msdu> There are more MSDUs linked to this 1819 MSDU that belongs to this MPDU 1820 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 1821 This setting is only allowed in combination with 'Msdu_continuation' 1822 set to 0. This implies that when an msdu is spread out over 1823 multiple buffers and thus msdu_continuation is set, only 1824 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 1825 be set. 1826 1827 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 1828 are set, the MPDU that this MSDU belongs to only contains 1829 a single MSDU. 1830 1831 1832 <legal all> 1833 */ 1834 1835 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1836 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1837 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 1838 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1839 1840 1841 /* Description MSDU_CONTINUATION 1842 1843 When set, this MSDU buffer was not able to hold the entire 1844 MSDU. The next buffer will therefor contain additional 1845 information related to this MSDU. 1846 1847 <legal all> 1848 */ 1849 1850 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 1851 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1852 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 1853 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1854 1855 1856 /* Description MSDU_LENGTH 1857 1858 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 1859 multiple buffers, this field will be valid in the First 1860 buffer used by MSDU. 1861 1862 Full MSDU length in bytes after decapsulation. 1863 1864 This field is still valid for MPDU frames without A-MSDU. 1865 It still represents MSDU length after decapsulation 1866 1867 Or in case of RAW MPDUs, it indicates the length of the 1868 entire MPDU (without FCS field) 1869 <legal all> 1870 */ 1871 1872 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 1873 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1874 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 1875 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1876 1877 1878 /* Description MSDU_DROP 1879 1880 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1881 multiple buffers, this field will be valid in the Last 1882 buffer used by the MSDU 1883 1884 When set, REO shall drop this MSDU and not forward it to 1885 any other ring... 1886 <legal all> 1887 */ 1888 1889 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 1890 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 1891 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 1892 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 1893 1894 1895 /* Description SA_IS_VALID 1896 1897 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1898 multiple buffers, this field will be valid in the Last 1899 buffer used by the MSDU 1900 1901 Indicates that OLE found a valid SA entry for this MSDU 1902 <legal all> 1903 */ 1904 1905 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 1906 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 1907 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 1908 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 1909 1910 1911 /* Description DA_IS_VALID 1912 1913 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1914 multiple buffers, this field will be valid in the Last 1915 buffer used by the MSDU 1916 1917 Indicates that OLE found a valid DA entry for this MSDU 1918 <legal all> 1919 */ 1920 1921 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 1922 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 1923 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 1924 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 1925 1926 1927 /* Description DA_IS_MCBC 1928 1929 Field Only valid if "da_is_valid" is set 1930 1931 Indicates the DA address was a Multicast of Broadcast address 1932 for this MSDU 1933 <legal all> 1934 */ 1935 1936 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 1937 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 1938 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 1939 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 1940 1941 1942 /* Description L3_HEADER_PADDING_MSB 1943 1944 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 1945 as the LSB is always zero) 1946 Number of bytes padded to make sure that the L3 header will 1947 always start of a Dword boundary 1948 <legal all> 1949 */ 1950 1951 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 1952 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 1953 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 1954 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 1955 1956 1957 /* Description TCP_UDP_CHKSUM_FAIL 1958 1959 Passed on from 'RX_ATTENTION' TLV 1960 Indicates that the computed checksum did not match the checksum 1961 in the TCP/UDP header. 1962 <legal all> 1963 */ 1964 1965 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 1966 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 1967 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 1968 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 1969 1970 1971 /* Description IP_CHKSUM_FAIL 1972 1973 Passed on from 'RX_ATTENTION' TLV 1974 Indicates that the computed checksum did not match the checksum 1975 in the IP header. 1976 <legal all> 1977 */ 1978 1979 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 1980 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 1981 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 1982 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 1983 1984 1985 /* Description FR_DS 1986 1987 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1988 TLV 1989 Set if the 'from DS' bit is set in the frame control. 1990 <legal all> 1991 */ 1992 1993 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 1994 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 1995 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 1996 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 1997 1998 1999 /* Description TO_DS 2000 2001 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 2002 TLV 2003 Set if the 'to DS' bit is set in the frame control. 2004 <legal all> 2005 */ 2006 2007 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 2008 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 2009 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 2010 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 2011 2012 2013 /* Description INTRA_BSS 2014 2015 This packet needs intra-BSS routing by SW as the 'vdev_id' 2016 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 2017 that this MSDU was got in. 2018 2019 <legal all> 2020 */ 2021 2022 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 2023 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 2024 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 2025 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 2026 2027 2028 /* Description DEST_CHIP_ID 2029 2030 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2031 to support intra-BSS routing with multi-chip multi-link 2032 operation. 2033 2034 This indicates into which chip's TCL the packet should be 2035 queued. 2036 2037 <legal all> 2038 */ 2039 2040 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 2041 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 2042 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 2043 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 2044 2045 2046 /* Description DECAP_FORMAT 2047 2048 Indicates the format after decapsulation: 2049 2050 <enum 0 RAW> No encapsulation 2051 <enum 1 Native_WiFi> 2052 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 2053 2054 <enum 3 802_3> Indicate Ethernet 2055 2056 <legal all> 2057 */ 2058 2059 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 2060 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 2061 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 2062 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 2063 2064 2065 /* Description DEST_CHIP_PMAC_ID 2066 2067 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2068 to support intra-BSS routing with multi-chip multi-link 2069 operation. 2070 2071 This indicates into which link/'vdev' the packet should 2072 be queued in TCL. 2073 2074 <legal all> 2075 */ 2076 2077 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000048 2078 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 2079 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 2080 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 2081 2082 2083 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 2084 2085 Consumer: REO/SW 2086 Producer: RXDMA 2087 2088 Extended information related to the MSDU that is passed 2089 on from RXDMA to REO but not part of the REO destination 2090 ring. Some fields are passed on to PPE. 2091 */ 2092 2093 2094 /* Description REO_DESTINATION_INDICATION 2095 2096 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2097 multiple buffers, this field will be valid in the Last 2098 buffer used by the MSDU 2099 2100 The ID of the REO exit ring where the MSDU frame shall push 2101 after (MPDU level) reordering has finished. 2102 2103 <enum 0 reo_destination_sw0> Reo will push the frame into 2104 the REO2SW0 ring 2105 <enum 1 reo_destination_sw1> Reo will push the frame into 2106 the REO2SW1 ring 2107 <enum 2 reo_destination_sw2> Reo will push the frame into 2108 the REO2SW2 ring 2109 <enum 3 reo_destination_sw3> Reo will push the frame into 2110 the REO2SW3 ring 2111 <enum 4 reo_destination_sw4> Reo will push the frame into 2112 the REO2SW4 ring 2113 <enum 5 reo_destination_release> Reo will push the frame 2114 into the REO_release ring 2115 <enum 6 reo_destination_fw> Reo will push the frame into 2116 the REO2FW ring 2117 <enum 7 reo_destination_sw5> Reo will push the frame into 2118 the REO2SW5 ring (REO remaps this in chips without REO2SW5 2119 ring, e.g. Pine) 2120 <enum 8 reo_destination_sw6> Reo will push the frame into 2121 the REO2SW6 ring (REO remaps this in chips without REO2SW6 2122 ring, e.g. Pine) 2123 <enum 9 reo_destination_sw7> Reo will push the frame into 2124 the REO2SW7 ring (REO remaps this in chips without REO2SW7 2125 ring) 2126 <enum 10 reo_destination_sw8> Reo will push the frame into 2127 the REO2SW8 ring (REO remaps this in chips without REO2SW8 2128 ring) 2129 <enum 11 reo_destination_11> REO remaps this 2130 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 2131 REO remaps this 2132 <enum 14 reo_destination_14> REO remaps this 2133 <enum 15 reo_destination_15> REO remaps this 2134 <enum 16 reo_destination_16> REO remaps this 2135 <enum 17 reo_destination_17> REO remaps this 2136 <enum 18 reo_destination_18> REO remaps this 2137 <enum 19 reo_destination_19> REO remaps this 2138 <enum 20 reo_destination_20> REO remaps this 2139 <enum 21 reo_destination_21> REO remaps this 2140 <enum 22 reo_destination_22> REO remaps this 2141 <enum 23 reo_destination_23> REO remaps this 2142 <enum 24 reo_destination_24> REO remaps this 2143 <enum 25 reo_destination_25> REO remaps this 2144 <enum 26 reo_destination_26> REO remaps this 2145 <enum 27 reo_destination_27> REO remaps this 2146 <enum 28 reo_destination_28> REO remaps this 2147 <enum 29 reo_destination_29> REO remaps this 2148 <enum 30 reo_destination_30> REO remaps this 2149 <enum 31 reo_destination_31> REO remaps this 2150 2151 <legal all> 2152 */ 2153 2154 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c 2155 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 2156 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 2157 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 2158 2159 2160 /* Description SERVICE_CODE 2161 2162 Opaque service code between PPE and Wi-Fi 2163 2164 This field gets passed on by REO to PPE in the EDMA descriptor 2165 ('REO_TO_PPE_RING'). 2166 2167 <legal all> 2168 */ 2169 2170 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c 2171 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 2172 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 2173 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 2174 2175 2176 /* Description PRIORITY_VALID 2177 2178 This field gets passed on by REO to PPE in the EDMA descriptor 2179 ('REO_TO_PPE_RING'). 2180 2181 <legal all> 2182 */ 2183 2184 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c 2185 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 2186 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 2187 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 2188 2189 2190 /* Description DATA_OFFSET 2191 2192 The offset to Rx packet data within the buffer (including 2193 Rx DMA offset programming and L3 header padding inserted 2194 by Rx OLE). 2195 2196 This field gets passed on by REO to PPE in the EDMA descriptor 2197 ('REO_TO_PPE_RING'). 2198 2199 <legal all> 2200 */ 2201 2202 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c 2203 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 2204 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 2205 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 2206 2207 2208 /* Description SRC_LINK_ID 2209 2210 Consumer: SW 2211 Producer: RXDMA 2212 2213 Set to the link ID of the PMAC that received the frame 2214 <legal all> 2215 */ 2216 2217 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c 2218 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 2219 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 2220 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 2221 2222 2223 /* Description RESERVED_0A 2224 2225 <legal 0> 2226 */ 2227 2228 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c 2229 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 2230 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 2231 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 2232 2233 2234 /* Description MSDU_3 2235 2236 Details of next MSDU in this (MSDU flow) linked list 2237 */ 2238 2239 2240 /* Description BUFFER_ADDR_INFO_DETAILS 2241 2242 Consumer: REO/SW 2243 Producer: RXDMA 2244 2245 Details of the physical address of the buffer containing 2246 an MSDU (or entire MPDU) 2247 */ 2248 2249 2250 /* Description BUFFER_ADDR_31_0 2251 2252 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2253 descriptor OR Link Descriptor 2254 2255 In case of 'NULL' pointer, this field is set to 0 2256 <legal all> 2257 */ 2258 2259 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 2260 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2261 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 2262 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2263 2264 2265 /* Description BUFFER_ADDR_39_32 2266 2267 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2268 descriptor OR Link Descriptor 2269 2270 In case of 'NULL' pointer, this field is set to 0 2271 <legal all> 2272 */ 2273 2274 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 2275 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2276 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 2277 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2278 2279 2280 /* Description RETURN_BUFFER_MANAGER 2281 2282 Consumer: WBM 2283 Producer: SW/FW 2284 2285 In case of 'NULL' pointer, this field is set to 0 2286 2287 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2288 descriptor OR link descriptor that is being pointed to 2289 shall be returned after the frame has been processed. It 2290 is used by WBM for routing purposes. 2291 2292 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2293 to the WMB buffer idle list 2294 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2295 to the WBM idle link descriptor idle list, where the chip 2296 0 WBM is chosen in case of a multi-chip config 2297 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2298 to the chip 1 WBM idle link descriptor idle list 2299 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2300 to the chip 2 WBM idle link descriptor idle list 2301 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2302 returned to chip 3 WBM idle link descriptor idle list 2303 <enum 4 FW_BM> This buffer shall be returned to the FW 2304 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2305 ring 0 2306 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2307 ring 1 2308 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2309 ring 2 2310 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2311 ring 3 2312 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2313 ring 4 2314 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2315 ring 5 2316 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2317 ring 6 2318 2319 <legal 0-12> 2320 */ 2321 2322 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2323 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2324 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 2325 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2326 2327 2328 /* Description SW_BUFFER_COOKIE 2329 2330 Cookie field exclusively used by SW. 2331 2332 In case of 'NULL' pointer, this field is set to 0 2333 2334 HW ignores the contents, accept that it passes the programmed 2335 value on to other descriptors together with the physical 2336 address 2337 2338 Field can be used by SW to for example associate the buffers 2339 physical address with the virtual address 2340 The bit definitions as used by SW are within SW HLD specification 2341 2342 2343 NOTE1: 2344 The three most significant bits can have a special meaning 2345 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2346 and field transmit_bw_restriction is set 2347 2348 In case of NON punctured transmission: 2349 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2350 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2351 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2352 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2353 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2354 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2355 Sw_buffer_cookie[19:18] = 2'b11: reserved 2356 2357 In case of punctured transmission: 2358 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2359 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2360 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2361 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2362 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2363 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2364 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2365 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2366 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2367 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2368 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2369 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2370 Sw_buffer_cookie[19:18] = 2'b11: reserved 2371 2372 Note: a punctured transmission is indicated by the presence 2373 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2374 2375 <legal all> 2376 */ 2377 2378 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 2379 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 2380 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 2381 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 2382 2383 2384 /* Description RX_MSDU_DESC_INFO_DETAILS 2385 2386 Consumer: REO/SW 2387 Producer: RXDMA 2388 2389 General information related to the MSDU that should be passed 2390 on from RXDMA all the way to to the REO destination ring. 2391 2392 */ 2393 2394 2395 /* Description FIRST_MSDU_IN_MPDU_FLAG 2396 2397 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2398 multiple buffers, this field will be valid in the Last 2399 buffer used by the MSDU 2400 2401 <enum 0 Not_first_msdu> This is not the first MSDU in the 2402 MPDU. 2403 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 2404 2405 2406 <legal all> 2407 */ 2408 2409 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2410 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2411 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 2412 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2413 2414 2415 /* Description LAST_MSDU_IN_MPDU_FLAG 2416 2417 Consumer: WBM/REO/SW/FW 2418 Producer: RXDMA 2419 2420 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2421 multiple buffers, this field will be valid in the Last 2422 buffer used by the MSDU 2423 2424 <enum 0 Not_last_msdu> There are more MSDUs linked to this 2425 MSDU that belongs to this MPDU 2426 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 2427 This setting is only allowed in combination with 'Msdu_continuation' 2428 set to 0. This implies that when an msdu is spread out over 2429 multiple buffers and thus msdu_continuation is set, only 2430 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 2431 be set. 2432 2433 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 2434 are set, the MPDU that this MSDU belongs to only contains 2435 a single MSDU. 2436 2437 2438 <legal all> 2439 */ 2440 2441 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2442 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2443 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 2444 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2445 2446 2447 /* Description MSDU_CONTINUATION 2448 2449 When set, this MSDU buffer was not able to hold the entire 2450 MSDU. The next buffer will therefor contain additional 2451 information related to this MSDU. 2452 2453 <legal all> 2454 */ 2455 2456 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 2457 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2458 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 2459 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2460 2461 2462 /* Description MSDU_LENGTH 2463 2464 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 2465 multiple buffers, this field will be valid in the First 2466 buffer used by MSDU. 2467 2468 Full MSDU length in bytes after decapsulation. 2469 2470 This field is still valid for MPDU frames without A-MSDU. 2471 It still represents MSDU length after decapsulation 2472 2473 Or in case of RAW MPDUs, it indicates the length of the 2474 entire MPDU (without FCS field) 2475 <legal all> 2476 */ 2477 2478 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 2479 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2480 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 2481 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2482 2483 2484 /* Description MSDU_DROP 2485 2486 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2487 multiple buffers, this field will be valid in the Last 2488 buffer used by the MSDU 2489 2490 When set, REO shall drop this MSDU and not forward it to 2491 any other ring... 2492 <legal all> 2493 */ 2494 2495 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 2496 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 2497 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 2498 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 2499 2500 2501 /* Description SA_IS_VALID 2502 2503 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2504 multiple buffers, this field will be valid in the Last 2505 buffer used by the MSDU 2506 2507 Indicates that OLE found a valid SA entry for this MSDU 2508 <legal all> 2509 */ 2510 2511 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 2512 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 2513 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 2514 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 2515 2516 2517 /* Description DA_IS_VALID 2518 2519 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2520 multiple buffers, this field will be valid in the Last 2521 buffer used by the MSDU 2522 2523 Indicates that OLE found a valid DA entry for this MSDU 2524 <legal all> 2525 */ 2526 2527 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 2528 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 2529 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 2530 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 2531 2532 2533 /* Description DA_IS_MCBC 2534 2535 Field Only valid if "da_is_valid" is set 2536 2537 Indicates the DA address was a Multicast of Broadcast address 2538 for this MSDU 2539 <legal all> 2540 */ 2541 2542 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 2543 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 2544 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 2545 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 2546 2547 2548 /* Description L3_HEADER_PADDING_MSB 2549 2550 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 2551 as the LSB is always zero) 2552 Number of bytes padded to make sure that the L3 header will 2553 always start of a Dword boundary 2554 <legal all> 2555 */ 2556 2557 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 2558 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 2559 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 2560 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 2561 2562 2563 /* Description TCP_UDP_CHKSUM_FAIL 2564 2565 Passed on from 'RX_ATTENTION' TLV 2566 Indicates that the computed checksum did not match the checksum 2567 in the TCP/UDP header. 2568 <legal all> 2569 */ 2570 2571 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 2572 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 2573 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 2574 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 2575 2576 2577 /* Description IP_CHKSUM_FAIL 2578 2579 Passed on from 'RX_ATTENTION' TLV 2580 Indicates that the computed checksum did not match the checksum 2581 in the IP header. 2582 <legal all> 2583 */ 2584 2585 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 2586 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 2587 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 2588 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 2589 2590 2591 /* Description FR_DS 2592 2593 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 2594 TLV 2595 Set if the 'from DS' bit is set in the frame control. 2596 <legal all> 2597 */ 2598 2599 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 2600 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 2601 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 2602 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 2603 2604 2605 /* Description TO_DS 2606 2607 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 2608 TLV 2609 Set if the 'to DS' bit is set in the frame control. 2610 <legal all> 2611 */ 2612 2613 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 2614 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 2615 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 2616 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 2617 2618 2619 /* Description INTRA_BSS 2620 2621 This packet needs intra-BSS routing by SW as the 'vdev_id' 2622 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 2623 that this MSDU was got in. 2624 2625 <legal all> 2626 */ 2627 2628 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 2629 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 2630 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 2631 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 2632 2633 2634 /* Description DEST_CHIP_ID 2635 2636 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2637 to support intra-BSS routing with multi-chip multi-link 2638 operation. 2639 2640 This indicates into which chip's TCL the packet should be 2641 queued. 2642 2643 <legal all> 2644 */ 2645 2646 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 2647 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 2648 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 2649 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 2650 2651 2652 /* Description DECAP_FORMAT 2653 2654 Indicates the format after decapsulation: 2655 2656 <enum 0 RAW> No encapsulation 2657 <enum 1 Native_WiFi> 2658 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 2659 2660 <enum 3 802_3> Indicate Ethernet 2661 2662 <legal all> 2663 */ 2664 2665 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 2666 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 2667 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 2668 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 2669 2670 2671 /* Description DEST_CHIP_PMAC_ID 2672 2673 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2674 to support intra-BSS routing with multi-chip multi-link 2675 operation. 2676 2677 This indicates into which link/'vdev' the packet should 2678 be queued in TCL. 2679 2680 <legal all> 2681 */ 2682 2683 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000058 2684 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 2685 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 2686 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 2687 2688 2689 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 2690 2691 Consumer: REO/SW 2692 Producer: RXDMA 2693 2694 Extended information related to the MSDU that is passed 2695 on from RXDMA to REO but not part of the REO destination 2696 ring. Some fields are passed on to PPE. 2697 */ 2698 2699 2700 /* Description REO_DESTINATION_INDICATION 2701 2702 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2703 multiple buffers, this field will be valid in the Last 2704 buffer used by the MSDU 2705 2706 The ID of the REO exit ring where the MSDU frame shall push 2707 after (MPDU level) reordering has finished. 2708 2709 <enum 0 reo_destination_sw0> Reo will push the frame into 2710 the REO2SW0 ring 2711 <enum 1 reo_destination_sw1> Reo will push the frame into 2712 the REO2SW1 ring 2713 <enum 2 reo_destination_sw2> Reo will push the frame into 2714 the REO2SW2 ring 2715 <enum 3 reo_destination_sw3> Reo will push the frame into 2716 the REO2SW3 ring 2717 <enum 4 reo_destination_sw4> Reo will push the frame into 2718 the REO2SW4 ring 2719 <enum 5 reo_destination_release> Reo will push the frame 2720 into the REO_release ring 2721 <enum 6 reo_destination_fw> Reo will push the frame into 2722 the REO2FW ring 2723 <enum 7 reo_destination_sw5> Reo will push the frame into 2724 the REO2SW5 ring (REO remaps this in chips without REO2SW5 2725 ring, e.g. Pine) 2726 <enum 8 reo_destination_sw6> Reo will push the frame into 2727 the REO2SW6 ring (REO remaps this in chips without REO2SW6 2728 ring, e.g. Pine) 2729 <enum 9 reo_destination_sw7> Reo will push the frame into 2730 the REO2SW7 ring (REO remaps this in chips without REO2SW7 2731 ring) 2732 <enum 10 reo_destination_sw8> Reo will push the frame into 2733 the REO2SW8 ring (REO remaps this in chips without REO2SW8 2734 ring) 2735 <enum 11 reo_destination_11> REO remaps this 2736 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 2737 REO remaps this 2738 <enum 14 reo_destination_14> REO remaps this 2739 <enum 15 reo_destination_15> REO remaps this 2740 <enum 16 reo_destination_16> REO remaps this 2741 <enum 17 reo_destination_17> REO remaps this 2742 <enum 18 reo_destination_18> REO remaps this 2743 <enum 19 reo_destination_19> REO remaps this 2744 <enum 20 reo_destination_20> REO remaps this 2745 <enum 21 reo_destination_21> REO remaps this 2746 <enum 22 reo_destination_22> REO remaps this 2747 <enum 23 reo_destination_23> REO remaps this 2748 <enum 24 reo_destination_24> REO remaps this 2749 <enum 25 reo_destination_25> REO remaps this 2750 <enum 26 reo_destination_26> REO remaps this 2751 <enum 27 reo_destination_27> REO remaps this 2752 <enum 28 reo_destination_28> REO remaps this 2753 <enum 29 reo_destination_29> REO remaps this 2754 <enum 30 reo_destination_30> REO remaps this 2755 <enum 31 reo_destination_31> REO remaps this 2756 2757 <legal all> 2758 */ 2759 2760 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c 2761 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 2762 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 2763 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 2764 2765 2766 /* Description SERVICE_CODE 2767 2768 Opaque service code between PPE and Wi-Fi 2769 2770 This field gets passed on by REO to PPE in the EDMA descriptor 2771 ('REO_TO_PPE_RING'). 2772 2773 <legal all> 2774 */ 2775 2776 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c 2777 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 2778 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 2779 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 2780 2781 2782 /* Description PRIORITY_VALID 2783 2784 This field gets passed on by REO to PPE in the EDMA descriptor 2785 ('REO_TO_PPE_RING'). 2786 2787 <legal all> 2788 */ 2789 2790 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c 2791 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 2792 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 2793 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 2794 2795 2796 /* Description DATA_OFFSET 2797 2798 The offset to Rx packet data within the buffer (including 2799 Rx DMA offset programming and L3 header padding inserted 2800 by Rx OLE). 2801 2802 This field gets passed on by REO to PPE in the EDMA descriptor 2803 ('REO_TO_PPE_RING'). 2804 2805 <legal all> 2806 */ 2807 2808 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c 2809 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 2810 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 2811 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 2812 2813 2814 /* Description SRC_LINK_ID 2815 2816 Consumer: SW 2817 Producer: RXDMA 2818 2819 Set to the link ID of the PMAC that received the frame 2820 <legal all> 2821 */ 2822 2823 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c 2824 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 2825 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 2826 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 2827 2828 2829 /* Description RESERVED_0A 2830 2831 <legal 0> 2832 */ 2833 2834 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c 2835 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 2836 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 2837 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 2838 2839 2840 /* Description MSDU_4 2841 2842 Details of next MSDU in this (MSDU flow) linked list 2843 */ 2844 2845 2846 /* Description BUFFER_ADDR_INFO_DETAILS 2847 2848 Consumer: REO/SW 2849 Producer: RXDMA 2850 2851 Details of the physical address of the buffer containing 2852 an MSDU (or entire MPDU) 2853 */ 2854 2855 2856 /* Description BUFFER_ADDR_31_0 2857 2858 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2859 descriptor OR Link Descriptor 2860 2861 In case of 'NULL' pointer, this field is set to 0 2862 <legal all> 2863 */ 2864 2865 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 2866 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2867 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 2868 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2869 2870 2871 /* Description BUFFER_ADDR_39_32 2872 2873 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2874 descriptor OR Link Descriptor 2875 2876 In case of 'NULL' pointer, this field is set to 0 2877 <legal all> 2878 */ 2879 2880 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 2881 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2882 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 2883 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2884 2885 2886 /* Description RETURN_BUFFER_MANAGER 2887 2888 Consumer: WBM 2889 Producer: SW/FW 2890 2891 In case of 'NULL' pointer, this field is set to 0 2892 2893 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2894 descriptor OR link descriptor that is being pointed to 2895 shall be returned after the frame has been processed. It 2896 is used by WBM for routing purposes. 2897 2898 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2899 to the WMB buffer idle list 2900 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2901 to the WBM idle link descriptor idle list, where the chip 2902 0 WBM is chosen in case of a multi-chip config 2903 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2904 to the chip 1 WBM idle link descriptor idle list 2905 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2906 to the chip 2 WBM idle link descriptor idle list 2907 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2908 returned to chip 3 WBM idle link descriptor idle list 2909 <enum 4 FW_BM> This buffer shall be returned to the FW 2910 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2911 ring 0 2912 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2913 ring 1 2914 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2915 ring 2 2916 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2917 ring 3 2918 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2919 ring 4 2920 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2921 ring 5 2922 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2923 ring 6 2924 2925 <legal 0-12> 2926 */ 2927 2928 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2929 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2930 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 2931 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2932 2933 2934 /* Description SW_BUFFER_COOKIE 2935 2936 Cookie field exclusively used by SW. 2937 2938 In case of 'NULL' pointer, this field is set to 0 2939 2940 HW ignores the contents, accept that it passes the programmed 2941 value on to other descriptors together with the physical 2942 address 2943 2944 Field can be used by SW to for example associate the buffers 2945 physical address with the virtual address 2946 The bit definitions as used by SW are within SW HLD specification 2947 2948 2949 NOTE1: 2950 The three most significant bits can have a special meaning 2951 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2952 and field transmit_bw_restriction is set 2953 2954 In case of NON punctured transmission: 2955 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2956 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2957 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2958 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2959 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2960 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2961 Sw_buffer_cookie[19:18] = 2'b11: reserved 2962 2963 In case of punctured transmission: 2964 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2965 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2966 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2967 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2968 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2969 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2970 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2971 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2972 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2973 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2974 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2975 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2976 Sw_buffer_cookie[19:18] = 2'b11: reserved 2977 2978 Note: a punctured transmission is indicated by the presence 2979 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2980 2981 <legal all> 2982 */ 2983 2984 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 2985 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 2986 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 2987 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 2988 2989 2990 /* Description RX_MSDU_DESC_INFO_DETAILS 2991 2992 Consumer: REO/SW 2993 Producer: RXDMA 2994 2995 General information related to the MSDU that should be passed 2996 on from RXDMA all the way to to the REO destination ring. 2997 2998 */ 2999 3000 3001 /* Description FIRST_MSDU_IN_MPDU_FLAG 3002 3003 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3004 multiple buffers, this field will be valid in the Last 3005 buffer used by the MSDU 3006 3007 <enum 0 Not_first_msdu> This is not the first MSDU in the 3008 MPDU. 3009 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 3010 3011 3012 <legal all> 3013 */ 3014 3015 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 3016 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3017 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 3018 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3019 3020 3021 /* Description LAST_MSDU_IN_MPDU_FLAG 3022 3023 Consumer: WBM/REO/SW/FW 3024 Producer: RXDMA 3025 3026 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3027 multiple buffers, this field will be valid in the Last 3028 buffer used by the MSDU 3029 3030 <enum 0 Not_last_msdu> There are more MSDUs linked to this 3031 MSDU that belongs to this MPDU 3032 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 3033 This setting is only allowed in combination with 'Msdu_continuation' 3034 set to 0. This implies that when an msdu is spread out over 3035 multiple buffers and thus msdu_continuation is set, only 3036 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 3037 be set. 3038 3039 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 3040 are set, the MPDU that this MSDU belongs to only contains 3041 a single MSDU. 3042 3043 3044 <legal all> 3045 */ 3046 3047 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 3048 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3049 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 3050 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3051 3052 3053 /* Description MSDU_CONTINUATION 3054 3055 When set, this MSDU buffer was not able to hold the entire 3056 MSDU. The next buffer will therefor contain additional 3057 information related to this MSDU. 3058 3059 <legal all> 3060 */ 3061 3062 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 3063 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3064 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 3065 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3066 3067 3068 /* Description MSDU_LENGTH 3069 3070 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 3071 multiple buffers, this field will be valid in the First 3072 buffer used by MSDU. 3073 3074 Full MSDU length in bytes after decapsulation. 3075 3076 This field is still valid for MPDU frames without A-MSDU. 3077 It still represents MSDU length after decapsulation 3078 3079 Or in case of RAW MPDUs, it indicates the length of the 3080 entire MPDU (without FCS field) 3081 <legal all> 3082 */ 3083 3084 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 3085 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3086 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 3087 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3088 3089 3090 /* Description MSDU_DROP 3091 3092 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3093 multiple buffers, this field will be valid in the Last 3094 buffer used by the MSDU 3095 3096 When set, REO shall drop this MSDU and not forward it to 3097 any other ring... 3098 <legal all> 3099 */ 3100 3101 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 3102 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 3103 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 3104 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 3105 3106 3107 /* Description SA_IS_VALID 3108 3109 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3110 multiple buffers, this field will be valid in the Last 3111 buffer used by the MSDU 3112 3113 Indicates that OLE found a valid SA entry for this MSDU 3114 <legal all> 3115 */ 3116 3117 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 3118 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 3119 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 3120 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 3121 3122 3123 /* Description DA_IS_VALID 3124 3125 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3126 multiple buffers, this field will be valid in the Last 3127 buffer used by the MSDU 3128 3129 Indicates that OLE found a valid DA entry for this MSDU 3130 <legal all> 3131 */ 3132 3133 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 3134 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 3135 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 3136 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 3137 3138 3139 /* Description DA_IS_MCBC 3140 3141 Field Only valid if "da_is_valid" is set 3142 3143 Indicates the DA address was a Multicast of Broadcast address 3144 for this MSDU 3145 <legal all> 3146 */ 3147 3148 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 3149 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 3150 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 3151 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 3152 3153 3154 /* Description L3_HEADER_PADDING_MSB 3155 3156 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 3157 as the LSB is always zero) 3158 Number of bytes padded to make sure that the L3 header will 3159 always start of a Dword boundary 3160 <legal all> 3161 */ 3162 3163 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 3164 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 3165 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 3166 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 3167 3168 3169 /* Description TCP_UDP_CHKSUM_FAIL 3170 3171 Passed on from 'RX_ATTENTION' TLV 3172 Indicates that the computed checksum did not match the checksum 3173 in the TCP/UDP header. 3174 <legal all> 3175 */ 3176 3177 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 3178 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 3179 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 3180 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 3181 3182 3183 /* Description IP_CHKSUM_FAIL 3184 3185 Passed on from 'RX_ATTENTION' TLV 3186 Indicates that the computed checksum did not match the checksum 3187 in the IP header. 3188 <legal all> 3189 */ 3190 3191 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 3192 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 3193 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 3194 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 3195 3196 3197 /* Description FR_DS 3198 3199 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3200 TLV 3201 Set if the 'from DS' bit is set in the frame control. 3202 <legal all> 3203 */ 3204 3205 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 3206 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 3207 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 3208 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 3209 3210 3211 /* Description TO_DS 3212 3213 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3214 TLV 3215 Set if the 'to DS' bit is set in the frame control. 3216 <legal all> 3217 */ 3218 3219 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 3220 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 3221 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 3222 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 3223 3224 3225 /* Description INTRA_BSS 3226 3227 This packet needs intra-BSS routing by SW as the 'vdev_id' 3228 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 3229 that this MSDU was got in. 3230 3231 <legal all> 3232 */ 3233 3234 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 3235 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 3236 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 3237 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 3238 3239 3240 /* Description DEST_CHIP_ID 3241 3242 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3243 to support intra-BSS routing with multi-chip multi-link 3244 operation. 3245 3246 This indicates into which chip's TCL the packet should be 3247 queued. 3248 3249 <legal all> 3250 */ 3251 3252 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 3253 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 3254 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 3255 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 3256 3257 3258 /* Description DECAP_FORMAT 3259 3260 Indicates the format after decapsulation: 3261 3262 <enum 0 RAW> No encapsulation 3263 <enum 1 Native_WiFi> 3264 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 3265 3266 <enum 3 802_3> Indicate Ethernet 3267 3268 <legal all> 3269 */ 3270 3271 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 3272 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 3273 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 3274 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 3275 3276 3277 /* Description DEST_CHIP_PMAC_ID 3278 3279 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3280 to support intra-BSS routing with multi-chip multi-link 3281 operation. 3282 3283 This indicates into which link/'vdev' the packet should 3284 be queued in TCL. 3285 3286 <legal all> 3287 */ 3288 3289 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000068 3290 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 3291 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 3292 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 3293 3294 3295 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 3296 3297 Consumer: REO/SW 3298 Producer: RXDMA 3299 3300 Extended information related to the MSDU that is passed 3301 on from RXDMA to REO but not part of the REO destination 3302 ring. Some fields are passed on to PPE. 3303 */ 3304 3305 3306 /* Description REO_DESTINATION_INDICATION 3307 3308 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3309 multiple buffers, this field will be valid in the Last 3310 buffer used by the MSDU 3311 3312 The ID of the REO exit ring where the MSDU frame shall push 3313 after (MPDU level) reordering has finished. 3314 3315 <enum 0 reo_destination_sw0> Reo will push the frame into 3316 the REO2SW0 ring 3317 <enum 1 reo_destination_sw1> Reo will push the frame into 3318 the REO2SW1 ring 3319 <enum 2 reo_destination_sw2> Reo will push the frame into 3320 the REO2SW2 ring 3321 <enum 3 reo_destination_sw3> Reo will push the frame into 3322 the REO2SW3 ring 3323 <enum 4 reo_destination_sw4> Reo will push the frame into 3324 the REO2SW4 ring 3325 <enum 5 reo_destination_release> Reo will push the frame 3326 into the REO_release ring 3327 <enum 6 reo_destination_fw> Reo will push the frame into 3328 the REO2FW ring 3329 <enum 7 reo_destination_sw5> Reo will push the frame into 3330 the REO2SW5 ring (REO remaps this in chips without REO2SW5 3331 ring, e.g. Pine) 3332 <enum 8 reo_destination_sw6> Reo will push the frame into 3333 the REO2SW6 ring (REO remaps this in chips without REO2SW6 3334 ring, e.g. Pine) 3335 <enum 9 reo_destination_sw7> Reo will push the frame into 3336 the REO2SW7 ring (REO remaps this in chips without REO2SW7 3337 ring) 3338 <enum 10 reo_destination_sw8> Reo will push the frame into 3339 the REO2SW8 ring (REO remaps this in chips without REO2SW8 3340 ring) 3341 <enum 11 reo_destination_11> REO remaps this 3342 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 3343 REO remaps this 3344 <enum 14 reo_destination_14> REO remaps this 3345 <enum 15 reo_destination_15> REO remaps this 3346 <enum 16 reo_destination_16> REO remaps this 3347 <enum 17 reo_destination_17> REO remaps this 3348 <enum 18 reo_destination_18> REO remaps this 3349 <enum 19 reo_destination_19> REO remaps this 3350 <enum 20 reo_destination_20> REO remaps this 3351 <enum 21 reo_destination_21> REO remaps this 3352 <enum 22 reo_destination_22> REO remaps this 3353 <enum 23 reo_destination_23> REO remaps this 3354 <enum 24 reo_destination_24> REO remaps this 3355 <enum 25 reo_destination_25> REO remaps this 3356 <enum 26 reo_destination_26> REO remaps this 3357 <enum 27 reo_destination_27> REO remaps this 3358 <enum 28 reo_destination_28> REO remaps this 3359 <enum 29 reo_destination_29> REO remaps this 3360 <enum 30 reo_destination_30> REO remaps this 3361 <enum 31 reo_destination_31> REO remaps this 3362 3363 <legal all> 3364 */ 3365 3366 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c 3367 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 3368 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 3369 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 3370 3371 3372 /* Description SERVICE_CODE 3373 3374 Opaque service code between PPE and Wi-Fi 3375 3376 This field gets passed on by REO to PPE in the EDMA descriptor 3377 ('REO_TO_PPE_RING'). 3378 3379 <legal all> 3380 */ 3381 3382 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c 3383 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 3384 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 3385 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 3386 3387 3388 /* Description PRIORITY_VALID 3389 3390 This field gets passed on by REO to PPE in the EDMA descriptor 3391 ('REO_TO_PPE_RING'). 3392 3393 <legal all> 3394 */ 3395 3396 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c 3397 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 3398 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 3399 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 3400 3401 3402 /* Description DATA_OFFSET 3403 3404 The offset to Rx packet data within the buffer (including 3405 Rx DMA offset programming and L3 header padding inserted 3406 by Rx OLE). 3407 3408 This field gets passed on by REO to PPE in the EDMA descriptor 3409 ('REO_TO_PPE_RING'). 3410 3411 <legal all> 3412 */ 3413 3414 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c 3415 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 3416 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 3417 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 3418 3419 3420 /* Description SRC_LINK_ID 3421 3422 Consumer: SW 3423 Producer: RXDMA 3424 3425 Set to the link ID of the PMAC that received the frame 3426 <legal all> 3427 */ 3428 3429 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c 3430 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 3431 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 3432 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 3433 3434 3435 /* Description RESERVED_0A 3436 3437 <legal 0> 3438 */ 3439 3440 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c 3441 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 3442 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 3443 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 3444 3445 3446 /* Description MSDU_5 3447 3448 Details of next MSDU in this (MSDU flow) linked list 3449 */ 3450 3451 3452 /* Description BUFFER_ADDR_INFO_DETAILS 3453 3454 Consumer: REO/SW 3455 Producer: RXDMA 3456 3457 Details of the physical address of the buffer containing 3458 an MSDU (or entire MPDU) 3459 */ 3460 3461 3462 /* Description BUFFER_ADDR_31_0 3463 3464 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 3465 descriptor OR Link Descriptor 3466 3467 In case of 'NULL' pointer, this field is set to 0 3468 <legal all> 3469 */ 3470 3471 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 3472 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 3473 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 3474 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 3475 3476 3477 /* Description BUFFER_ADDR_39_32 3478 3479 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 3480 descriptor OR Link Descriptor 3481 3482 In case of 'NULL' pointer, this field is set to 0 3483 <legal all> 3484 */ 3485 3486 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 3487 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 3488 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 3489 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 3490 3491 3492 /* Description RETURN_BUFFER_MANAGER 3493 3494 Consumer: WBM 3495 Producer: SW/FW 3496 3497 In case of 'NULL' pointer, this field is set to 0 3498 3499 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 3500 descriptor OR link descriptor that is being pointed to 3501 shall be returned after the frame has been processed. It 3502 is used by WBM for routing purposes. 3503 3504 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 3505 to the WMB buffer idle list 3506 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 3507 to the WBM idle link descriptor idle list, where the chip 3508 0 WBM is chosen in case of a multi-chip config 3509 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 3510 to the chip 1 WBM idle link descriptor idle list 3511 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 3512 to the chip 2 WBM idle link descriptor idle list 3513 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 3514 returned to chip 3 WBM idle link descriptor idle list 3515 <enum 4 FW_BM> This buffer shall be returned to the FW 3516 <enum 5 SW0_BM> This buffer shall be returned to the SW, 3517 ring 0 3518 <enum 6 SW1_BM> This buffer shall be returned to the SW, 3519 ring 1 3520 <enum 7 SW2_BM> This buffer shall be returned to the SW, 3521 ring 2 3522 <enum 8 SW3_BM> This buffer shall be returned to the SW, 3523 ring 3 3524 <enum 9 SW4_BM> This buffer shall be returned to the SW, 3525 ring 4 3526 <enum 10 SW5_BM> This buffer shall be returned to the SW, 3527 ring 5 3528 <enum 11 SW6_BM> This buffer shall be returned to the SW, 3529 ring 6 3530 3531 <legal 0-12> 3532 */ 3533 3534 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 3535 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 3536 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 3537 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 3538 3539 3540 /* Description SW_BUFFER_COOKIE 3541 3542 Cookie field exclusively used by SW. 3543 3544 In case of 'NULL' pointer, this field is set to 0 3545 3546 HW ignores the contents, accept that it passes the programmed 3547 value on to other descriptors together with the physical 3548 address 3549 3550 Field can be used by SW to for example associate the buffers 3551 physical address with the virtual address 3552 The bit definitions as used by SW are within SW HLD specification 3553 3554 3555 NOTE1: 3556 The three most significant bits can have a special meaning 3557 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 3558 and field transmit_bw_restriction is set 3559 3560 In case of NON punctured transmission: 3561 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 3562 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 3563 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 3564 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 3565 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 3566 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 3567 Sw_buffer_cookie[19:18] = 2'b11: reserved 3568 3569 In case of punctured transmission: 3570 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 3571 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 3572 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 3573 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 3574 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 3575 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 3576 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 3577 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 3578 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 3579 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 3580 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 3581 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 3582 Sw_buffer_cookie[19:18] = 2'b11: reserved 3583 3584 Note: a punctured transmission is indicated by the presence 3585 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 3586 3587 <legal all> 3588 */ 3589 3590 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 3591 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 3592 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 3593 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 3594 3595 3596 /* Description RX_MSDU_DESC_INFO_DETAILS 3597 3598 Consumer: REO/SW 3599 Producer: RXDMA 3600 3601 General information related to the MSDU that should be passed 3602 on from RXDMA all the way to to the REO destination ring. 3603 3604 */ 3605 3606 3607 /* Description FIRST_MSDU_IN_MPDU_FLAG 3608 3609 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3610 multiple buffers, this field will be valid in the Last 3611 buffer used by the MSDU 3612 3613 <enum 0 Not_first_msdu> This is not the first MSDU in the 3614 MPDU. 3615 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 3616 3617 3618 <legal all> 3619 */ 3620 3621 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3622 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3623 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 3624 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3625 3626 3627 /* Description LAST_MSDU_IN_MPDU_FLAG 3628 3629 Consumer: WBM/REO/SW/FW 3630 Producer: RXDMA 3631 3632 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3633 multiple buffers, this field will be valid in the Last 3634 buffer used by the MSDU 3635 3636 <enum 0 Not_last_msdu> There are more MSDUs linked to this 3637 MSDU that belongs to this MPDU 3638 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 3639 This setting is only allowed in combination with 'Msdu_continuation' 3640 set to 0. This implies that when an msdu is spread out over 3641 multiple buffers and thus msdu_continuation is set, only 3642 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 3643 be set. 3644 3645 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 3646 are set, the MPDU that this MSDU belongs to only contains 3647 a single MSDU. 3648 3649 3650 <legal all> 3651 */ 3652 3653 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3654 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3655 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 3656 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3657 3658 3659 /* Description MSDU_CONTINUATION 3660 3661 When set, this MSDU buffer was not able to hold the entire 3662 MSDU. The next buffer will therefor contain additional 3663 information related to this MSDU. 3664 3665 <legal all> 3666 */ 3667 3668 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 3669 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3670 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 3671 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3672 3673 3674 /* Description MSDU_LENGTH 3675 3676 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 3677 multiple buffers, this field will be valid in the First 3678 buffer used by MSDU. 3679 3680 Full MSDU length in bytes after decapsulation. 3681 3682 This field is still valid for MPDU frames without A-MSDU. 3683 It still represents MSDU length after decapsulation 3684 3685 Or in case of RAW MPDUs, it indicates the length of the 3686 entire MPDU (without FCS field) 3687 <legal all> 3688 */ 3689 3690 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 3691 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3692 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 3693 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3694 3695 3696 /* Description MSDU_DROP 3697 3698 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3699 multiple buffers, this field will be valid in the Last 3700 buffer used by the MSDU 3701 3702 When set, REO shall drop this MSDU and not forward it to 3703 any other ring... 3704 <legal all> 3705 */ 3706 3707 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 3708 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 3709 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 3710 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 3711 3712 3713 /* Description SA_IS_VALID 3714 3715 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3716 multiple buffers, this field will be valid in the Last 3717 buffer used by the MSDU 3718 3719 Indicates that OLE found a valid SA entry for this MSDU 3720 <legal all> 3721 */ 3722 3723 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 3724 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 3725 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 3726 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 3727 3728 3729 /* Description DA_IS_VALID 3730 3731 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3732 multiple buffers, this field will be valid in the Last 3733 buffer used by the MSDU 3734 3735 Indicates that OLE found a valid DA entry for this MSDU 3736 <legal all> 3737 */ 3738 3739 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 3740 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 3741 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 3742 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 3743 3744 3745 /* Description DA_IS_MCBC 3746 3747 Field Only valid if "da_is_valid" is set 3748 3749 Indicates the DA address was a Multicast of Broadcast address 3750 for this MSDU 3751 <legal all> 3752 */ 3753 3754 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 3755 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 3756 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 3757 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 3758 3759 3760 /* Description L3_HEADER_PADDING_MSB 3761 3762 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 3763 as the LSB is always zero) 3764 Number of bytes padded to make sure that the L3 header will 3765 always start of a Dword boundary 3766 <legal all> 3767 */ 3768 3769 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 3770 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 3771 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 3772 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 3773 3774 3775 /* Description TCP_UDP_CHKSUM_FAIL 3776 3777 Passed on from 'RX_ATTENTION' TLV 3778 Indicates that the computed checksum did not match the checksum 3779 in the TCP/UDP header. 3780 <legal all> 3781 */ 3782 3783 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 3784 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 3785 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 3786 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 3787 3788 3789 /* Description IP_CHKSUM_FAIL 3790 3791 Passed on from 'RX_ATTENTION' TLV 3792 Indicates that the computed checksum did not match the checksum 3793 in the IP header. 3794 <legal all> 3795 */ 3796 3797 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 3798 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 3799 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 3800 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 3801 3802 3803 /* Description FR_DS 3804 3805 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3806 TLV 3807 Set if the 'from DS' bit is set in the frame control. 3808 <legal all> 3809 */ 3810 3811 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 3812 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 3813 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 3814 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 3815 3816 3817 /* Description TO_DS 3818 3819 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3820 TLV 3821 Set if the 'to DS' bit is set in the frame control. 3822 <legal all> 3823 */ 3824 3825 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 3826 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 3827 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 3828 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 3829 3830 3831 /* Description INTRA_BSS 3832 3833 This packet needs intra-BSS routing by SW as the 'vdev_id' 3834 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 3835 that this MSDU was got in. 3836 3837 <legal all> 3838 */ 3839 3840 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 3841 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 3842 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 3843 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 3844 3845 3846 /* Description DEST_CHIP_ID 3847 3848 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3849 to support intra-BSS routing with multi-chip multi-link 3850 operation. 3851 3852 This indicates into which chip's TCL the packet should be 3853 queued. 3854 3855 <legal all> 3856 */ 3857 3858 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 3859 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 3860 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 3861 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 3862 3863 3864 /* Description DECAP_FORMAT 3865 3866 Indicates the format after decapsulation: 3867 3868 <enum 0 RAW> No encapsulation 3869 <enum 1 Native_WiFi> 3870 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 3871 3872 <enum 3 802_3> Indicate Ethernet 3873 3874 <legal all> 3875 */ 3876 3877 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 3878 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 3879 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 3880 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 3881 3882 3883 /* Description DEST_CHIP_PMAC_ID 3884 3885 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3886 to support intra-BSS routing with multi-chip multi-link 3887 operation. 3888 3889 This indicates into which link/'vdev' the packet should 3890 be queued in TCL. 3891 3892 <legal all> 3893 */ 3894 3895 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000078 3896 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 3897 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 3898 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 3899 3900 3901 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 3902 3903 Consumer: REO/SW 3904 Producer: RXDMA 3905 3906 Extended information related to the MSDU that is passed 3907 on from RXDMA to REO but not part of the REO destination 3908 ring. Some fields are passed on to PPE. 3909 */ 3910 3911 3912 /* Description REO_DESTINATION_INDICATION 3913 3914 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3915 multiple buffers, this field will be valid in the Last 3916 buffer used by the MSDU 3917 3918 The ID of the REO exit ring where the MSDU frame shall push 3919 after (MPDU level) reordering has finished. 3920 3921 <enum 0 reo_destination_sw0> Reo will push the frame into 3922 the REO2SW0 ring 3923 <enum 1 reo_destination_sw1> Reo will push the frame into 3924 the REO2SW1 ring 3925 <enum 2 reo_destination_sw2> Reo will push the frame into 3926 the REO2SW2 ring 3927 <enum 3 reo_destination_sw3> Reo will push the frame into 3928 the REO2SW3 ring 3929 <enum 4 reo_destination_sw4> Reo will push the frame into 3930 the REO2SW4 ring 3931 <enum 5 reo_destination_release> Reo will push the frame 3932 into the REO_release ring 3933 <enum 6 reo_destination_fw> Reo will push the frame into 3934 the REO2FW ring 3935 <enum 7 reo_destination_sw5> Reo will push the frame into 3936 the REO2SW5 ring (REO remaps this in chips without REO2SW5 3937 ring, e.g. Pine) 3938 <enum 8 reo_destination_sw6> Reo will push the frame into 3939 the REO2SW6 ring (REO remaps this in chips without REO2SW6 3940 ring, e.g. Pine) 3941 <enum 9 reo_destination_sw7> Reo will push the frame into 3942 the REO2SW7 ring (REO remaps this in chips without REO2SW7 3943 ring) 3944 <enum 10 reo_destination_sw8> Reo will push the frame into 3945 the REO2SW8 ring (REO remaps this in chips without REO2SW8 3946 ring) 3947 <enum 11 reo_destination_11> REO remaps this 3948 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 3949 REO remaps this 3950 <enum 14 reo_destination_14> REO remaps this 3951 <enum 15 reo_destination_15> REO remaps this 3952 <enum 16 reo_destination_16> REO remaps this 3953 <enum 17 reo_destination_17> REO remaps this 3954 <enum 18 reo_destination_18> REO remaps this 3955 <enum 19 reo_destination_19> REO remaps this 3956 <enum 20 reo_destination_20> REO remaps this 3957 <enum 21 reo_destination_21> REO remaps this 3958 <enum 22 reo_destination_22> REO remaps this 3959 <enum 23 reo_destination_23> REO remaps this 3960 <enum 24 reo_destination_24> REO remaps this 3961 <enum 25 reo_destination_25> REO remaps this 3962 <enum 26 reo_destination_26> REO remaps this 3963 <enum 27 reo_destination_27> REO remaps this 3964 <enum 28 reo_destination_28> REO remaps this 3965 <enum 29 reo_destination_29> REO remaps this 3966 <enum 30 reo_destination_30> REO remaps this 3967 <enum 31 reo_destination_31> REO remaps this 3968 3969 <legal all> 3970 */ 3971 3972 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c 3973 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 3974 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 3975 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 3976 3977 3978 /* Description SERVICE_CODE 3979 3980 Opaque service code between PPE and Wi-Fi 3981 3982 This field gets passed on by REO to PPE in the EDMA descriptor 3983 ('REO_TO_PPE_RING'). 3984 3985 <legal all> 3986 */ 3987 3988 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c 3989 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 3990 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 3991 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 3992 3993 3994 /* Description PRIORITY_VALID 3995 3996 This field gets passed on by REO to PPE in the EDMA descriptor 3997 ('REO_TO_PPE_RING'). 3998 3999 <legal all> 4000 */ 4001 4002 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c 4003 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 4004 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 4005 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 4006 4007 4008 /* Description DATA_OFFSET 4009 4010 The offset to Rx packet data within the buffer (including 4011 Rx DMA offset programming and L3 header padding inserted 4012 by Rx OLE). 4013 4014 This field gets passed on by REO to PPE in the EDMA descriptor 4015 ('REO_TO_PPE_RING'). 4016 4017 <legal all> 4018 */ 4019 4020 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c 4021 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 4022 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 4023 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 4024 4025 4026 /* Description SRC_LINK_ID 4027 4028 Consumer: SW 4029 Producer: RXDMA 4030 4031 Set to the link ID of the PMAC that received the frame 4032 <legal all> 4033 */ 4034 4035 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c 4036 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 4037 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 4038 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 4039 4040 4041 /* Description RESERVED_0A 4042 4043 <legal 0> 4044 */ 4045 4046 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c 4047 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 4048 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 4049 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 4050 4051 4052 4053 #endif // RX_MSDU_LINK 4054