1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MPDU_START_H_ 27 #define _RX_MPDU_START_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_mpdu_info.h" 32 #define NUM_OF_DWORDS_RX_MPDU_START 30 33 34 #define NUM_OF_QWORDS_RX_MPDU_START 15 35 36 37 struct rx_mpdu_start { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct rx_mpdu_info rx_mpdu_info_details; 40 #else 41 struct rx_mpdu_info rx_mpdu_info_details; 42 #endif 43 }; 44 45 46 /* Description RX_MPDU_INFO_DETAILS 47 48 Structure containing all the MPDU header details that might 49 be needed for other modules further down the received path 50 51 */ 52 53 54 /* Description RXPT_CLASSIFY_INFO_DETAILS 55 56 In case of ndp or phy_err or AST_based_lookup_valid == 0, 57 this field will be set to 0 58 59 RXOLE related classification info 60 <legal all 61 */ 62 63 64 /* Description REO_DESTINATION_INDICATION 65 66 The ID of the REO exit ring where the MSDU frame shall push 67 after (MPDU level) reordering has finished. 68 69 <enum 0 reo_destination_sw0> Reo will push the frame into 70 the REO2SW0 ring 71 <enum 1 reo_destination_sw1> Reo will push the frame into 72 the REO2SW1 ring 73 <enum 2 reo_destination_sw2> Reo will push the frame into 74 the REO2SW2 ring 75 <enum 3 reo_destination_sw3> Reo will push the frame into 76 the REO2SW3 ring 77 <enum 4 reo_destination_sw4> Reo will push the frame into 78 the REO2SW4 ring 79 <enum 5 reo_destination_release> Reo will push the frame 80 into the REO_release ring 81 <enum 6 reo_destination_fw> Reo will push the frame into 82 the REO2FW ring 83 <enum 7 reo_destination_sw5> Reo will push the frame into 84 the REO2SW5 ring (REO remaps this in chips without REO2SW5 85 ring, e.g. Pine) 86 <enum 8 reo_destination_sw6> Reo will push the frame into 87 the REO2SW6 ring (REO remaps this in chips without REO2SW6 88 ring, e.g. Pine) 89 <enum 9 reo_destination_sw7> Reo will push the frame into 90 the REO2SW7 ring (REO remaps this in chips without REO2SW7 91 ring) 92 <enum 10 reo_destination_sw8> Reo will push the frame into 93 the REO2SW8 ring (REO remaps this in chips without REO2SW8 94 ring) 95 <enum 11 reo_destination_11> REO remaps this 96 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 97 REO remaps this 98 <enum 14 reo_destination_14> REO remaps this 99 <enum 15 reo_destination_15> REO remaps this 100 <enum 16 reo_destination_16> REO remaps this 101 <enum 17 reo_destination_17> REO remaps this 102 <enum 18 reo_destination_18> REO remaps this 103 <enum 19 reo_destination_19> REO remaps this 104 <enum 20 reo_destination_20> REO remaps this 105 <enum 21 reo_destination_21> REO remaps this 106 <enum 22 reo_destination_22> REO remaps this 107 <enum 23 reo_destination_23> REO remaps this 108 <enum 24 reo_destination_24> REO remaps this 109 <enum 25 reo_destination_25> REO remaps this 110 <enum 26 reo_destination_26> REO remaps this 111 <enum 27 reo_destination_27> REO remaps this 112 <enum 28 reo_destination_28> REO remaps this 113 <enum 29 reo_destination_29> REO remaps this 114 <enum 30 reo_destination_30> REO remaps this 115 <enum 31 reo_destination_31> REO remaps this 116 117 <legal all> 118 */ 119 120 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 121 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 122 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 123 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f 124 125 126 /* Description LMAC_PEER_ID_MSB 127 128 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 129 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 130 hash[3:0]} using the chosen Toeplitz hash from Common Parser 131 if flow search fails. 132 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 133 's not 2'b00, Rx OLE uses a REO desination indication of 134 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz 135 hash from Common Parser if flow search fails. 136 This LMAC/peer-based routing is not supported in Hastings80 137 and HastingsPrime. 138 <legal all> 139 */ 140 141 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 142 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 143 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 144 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 145 146 147 /* Description USE_FLOW_ID_TOEPLITZ_CLFY 148 149 Indication to Rx OLE to enable REO destination routing based 150 on the chosen Toeplitz hash from Common Parser, in case 151 flow search fails 152 <legal all> 153 */ 154 155 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 156 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 157 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 158 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 159 160 161 /* Description PKT_SELECTION_FP_UCAST_DATA 162 163 Filter pass Unicast data frame (matching rxpcu_filter_pass 164 and sw_frame_group_Unicast_data) routing selection 165 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 166 167 1'b0: source and destination rings are selected from the 168 RxOLE register settings for the packet type 169 170 1'b1: source ring and destination ring is selected from 171 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 172 fields in this STRUCT 173 <legal all> 174 */ 175 176 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 177 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 178 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 179 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 180 181 182 /* Description PKT_SELECTION_FP_MCAST_DATA 183 184 Filter pass Multicast data frame (matching rxpcu_filter_pass 185 and sw_frame_group_Multicast_data) routing selection 186 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 187 188 1'b0: source and destination rings are selected from the 189 RxOLE register settings for the packet type 190 191 1'b1: source ring and destination ring is selected from 192 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 193 fields in this STRUCT 194 <legal all> 195 */ 196 197 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 198 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 199 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 200 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 201 202 203 /* Description PKT_SELECTION_FP_1000 204 205 Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) 206 routing selection 207 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 208 209 1'b0: source and destination rings are selected from the 210 RxOLE register settings for the packet type 211 212 1'b1: source ring and destination ring is selected from 213 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 214 fields in this STRUCT 215 <legal all> 216 */ 217 218 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 219 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 220 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 221 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 222 223 224 /* Description RXDMA0_SOURCE_RING_SELECTION 225 226 Field only valid when for the received frame type the corresponding 227 pkt_selection_fp_... bit is set 228 229 <enum 0 sw2rxdma0_0_buf_source_ring> The data buffer for 230 this frame shall be sourced by sw2rxdma0 buffer source 231 ring. 232 <enum 1 fw2rxdma0_pmac0_buf_source_ring> The data buffer 233 for this frame shall be sourced by fw2rxdma buffer source 234 ring for PMAC0. 235 <enum 2 sw2rxdma0_1_buf_source_ring> The data buffer for 236 this frame shall be sourced by sw2rxdma1 buffer source 237 ring. 238 <enum 3 no_buffer_rxdma0_ring> The frame shall not be written 239 to any data buffer. 240 <enum 4 sw2rxdma0_exception_buf_source_ring> The data buffer 241 for this frame shall be sourced by sw2rxdma_exception buffer 242 source ring. 243 <enum 5 fw2rxdma0_pmac1_buf_source_ring> The data buffer 244 for this frame shall be sourced by fw2rxdma buffer source 245 ring for PMAC1. 246 247 <legal 0-5> 248 */ 249 250 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 251 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 252 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 253 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 254 255 256 /* Description RXDMA0_DESTINATION_RING_SELECTION 257 258 Field only valid when for the received frame type the corresponding 259 pkt_selection_fp_... bit is set 260 261 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 262 to the Release ring. Effectively this means the frame needs 263 to be dropped. 264 <enum 1 rxdma2fw_pmac0_ring> RXDMA0 shall push the frame 265 to the FW ring for PMAC0. 266 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to the 267 SW ring. 268 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 269 the REO entrance ring. 270 <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 271 to the FW ring for PMAC1. 272 <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 273 to the first MLO REO entrance ring. 274 <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 275 to the second MLO REO entrance ring. 276 277 <legal 0-6> 278 */ 279 280 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 281 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 282 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 283 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 284 285 286 /* Description MCAST_ECHO_DROP_ENABLE 287 288 If set, for multicast packets, multicast echo check (i.e. 289 SA search with mcast_echo_check = 1) shall be performed 290 by RXOLE, and any multicast echo packets should be indicated 291 to RXDMA for release to WBM 292 293 <legal all> 294 */ 295 296 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 297 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 298 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 299 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 300 301 302 /* Description WDS_LEARNING_DETECT_EN 303 304 If set, WDS learning detection based on SA search and notification 305 to FW (using RXDMA0 status ring) is enabled and the "timestamp" 306 field in address search failure cache-only entry should 307 be used to avoid multiple WDS learning notifications. 308 309 <legal all> 310 */ 311 312 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 313 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 314 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 315 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 316 317 318 /* Description INTRABSS_CHECK_EN 319 320 If set, intra-BSS routing detection is enabled 321 322 <legal all> 323 */ 324 325 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 326 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 327 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 328 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 329 330 331 /* Description USE_PPE 332 333 Indicates to RXDMA to ignore the REO_destination_indication 334 and use a programmed value corresponding to the REO2PPE 335 ring 336 337 This override to REO2PPE for packets requiring multiple 338 buffers shall be disabled based on an RXDMA configuration, 339 as PPE may not support such packets. 340 341 Supported only in full AP chips like Waikiki, not in client/soft 342 AP chips like Hamilton 343 <legal all> 344 */ 345 346 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 347 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 348 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 349 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 350 351 352 /* Description PPE_ROUTING_ENABLE 353 354 Global enable/disable bit for routing to PPE, used to disable 355 PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' 356 357 358 This is set by SW for peers which are being handled by a 359 host SW/accelerator subsystem that also handles packet 360 buffer management for WiFi-to-PPE routing. 361 362 This is cleared by SW for peers which are being handled 363 by a different subsystem, completely disabling WiFi-to-PPE 364 routing for such peers. 365 366 <legal all> 367 */ 368 369 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 370 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 371 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 372 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 373 374 375 /* Description RESERVED_0B 376 377 <legal 0> 378 */ 379 380 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 381 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 382 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 383 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000 384 385 386 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 387 388 In case of ndp or phy_err or AST_based_lookup_valid == 0, 389 this field will be set to 0 390 391 Address (lower 32 bits) of the REO queue descriptor. 392 393 If no Peer entry lookup happened for this frame, the value 394 wil be set to 0, and the frame shall never be pushed to 395 REO entrance ring. 396 <legal all> 397 */ 398 399 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 400 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 401 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 402 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 403 404 405 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 406 407 In case of ndp or phy_err or AST_based_lookup_valid == 0, 408 this field will be set to 0 409 410 Address (upper 8 bits) of the REO queue descriptor. 411 412 If no Peer entry lookup happened for this frame, the value 413 wil be set to 0, and the frame shall never be pushed to 414 REO entrance ring. 415 <legal all> 416 */ 417 418 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 419 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 420 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 421 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 422 423 424 /* Description RECEIVE_QUEUE_NUMBER 425 426 In case of ndp or phy_err or AST_based_lookup_valid == 0, 427 this field will be set to 0 428 429 Indicates the MPDU queue ID to which this MPDU link descriptor 430 belongs 431 Used for tracking and debugging 432 <legal all> 433 */ 434 435 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 436 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 437 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 438 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00 439 440 441 /* Description PRE_DELIM_ERR_WARNING 442 443 Indicates that a delimiter FCS error was found in between 444 the Previous MPDU and this MPDU. 445 446 Note that this is just a warning, and does not mean that 447 this MPDU is corrupted in any way. If it is, there will 448 be other errors indicated such as FCS or decrypt errors 449 450 451 In case of ndp or phy_err, this field will indicate at least 452 one of delimiters located after the last MPDU in the previous 453 PPDU has been corrupted. 454 */ 455 456 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 457 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 458 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 459 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000 460 461 462 /* Description FIRST_DELIM_ERR 463 464 Indicates that the first delimiter had a FCS failure. Only 465 valid when first_mpdu and first_msdu are set. 466 467 In case of ndp or phy_err, this field will never be set. 468 469 */ 470 471 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 472 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 473 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 474 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000 475 476 477 /* Description RESERVED_2A 478 479 <legal 0> 480 */ 481 482 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 483 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 484 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 485 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000 486 487 488 /* Description PN_31_0 489 490 Field only valid when Frame_encryption_info_valid is set 491 492 493 Bits [31:0] of the PN number extracted from the IV field 494 495 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 496 is valid. 497 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], 498 pn1}. Only pn[47:0] is valid. 499 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 500 pn0}. Only pn[47:0] is valid. 501 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 502 pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 503 pn[127:0] are valid. 504 505 In case of ndp or phy_err, this field will never be set. 506 507 */ 508 509 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008 510 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32 511 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63 512 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000 513 514 515 /* Description PN_63_32 516 517 Field only valid when Frame_encryption_info_valid is set 518 519 520 Bits [63:32] of the PN number. See description for pn_31_0. 521 522 523 In case of ndp or phy_err, this field will never be set. 524 525 */ 526 527 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 528 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 529 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 530 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff 531 532 533 /* Description PN_95_64 534 535 Field only valid when Frame_encryption_info_valid is set 536 537 538 Bits [95:64] of the PN number. See description for pn_31_0. 539 540 541 In case of ndp or phy_err, this field will never be set. 542 543 */ 544 545 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010 546 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32 547 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63 548 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000 549 550 551 /* Description PN_127_96 552 553 Field only valid when Frame_encryption_info_valid is set 554 555 556 Bits [127:96] of the PN number. See description for pn_31_0. 557 558 559 In case of ndp or phy_err, this field will never be set. 560 561 */ 562 563 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 564 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 565 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 566 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff 567 568 569 /* Description EPD_EN 570 571 Field only valid when AST_based_lookup_valid == 1. 572 573 574 In case of ndp or phy_err or AST_based_lookup_valid == 0, 575 this field will be set to 0 576 577 If set to one use EPD instead of LPD 578 579 In case of ndp or phy_err, this field will never be set. 580 581 <legal all> 582 */ 583 584 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018 585 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 586 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 587 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 588 589 590 /* Description ALL_FRAMES_SHALL_BE_ENCRYPTED 591 592 In case of ndp or phy_err or AST_based_lookup_valid == 0, 593 this field will be set to 0 594 595 When set, all frames (data only ?) shall be encrypted. If 596 not, RX CRYPTO shall set an error flag. 597 <legal all> 598 */ 599 600 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018 601 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 602 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 603 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 604 605 606 /* Description ENCRYPT_TYPE 607 608 In case of ndp or phy_err or AST_based_lookup_valid == 0, 609 this field will be set to 0 610 611 Indicates type of decrypt cipher used (as defined in the 612 peer entry) 613 614 <enum 0 wep_40> WEP 40-bit 615 <enum 1 wep_104> WEP 104-bit 616 <enum 2 tkip_no_mic> TKIP without MIC 617 <enum 3 wep_128> WEP 128-bit 618 <enum 4 tkip_with_mic> TKIP with MIC 619 <enum 5 wapi> WAPI 620 <enum 6 aes_ccmp_128> AES CCMP 128 621 <enum 7 no_cipher> No crypto 622 <enum 8 aes_ccmp_256> AES CCMP 256 623 <enum 9 aes_gcmp_128> AES CCMP 128 624 <enum 10 aes_gcmp_256> AES CCMP 256 625 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 626 627 <enum 12 wep_varied_width> WEP encryption. As for WEP per 628 keyid the key bit width can vary, the key bit width for 629 this MPDU will be indicated in field wep_key_width_for_variable 630 key 631 <legal 0-12> 632 */ 633 634 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018 635 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 636 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 637 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 638 639 640 /* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY 641 642 Field only valid when key_type is set to wep_varied_width. 643 644 645 This field indicates the size of the wep key for this MPDU. 646 647 648 <enum 0 wep_varied_width_40> WEP 40-bit 649 <enum 1 wep_varied_width_104> WEP 104-bit 650 <enum 2 wep_varied_width_128> WEP 128-bit 651 652 <legal 0-2> 653 */ 654 655 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018 656 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 657 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 658 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 659 660 661 /* Description MESH_STA 662 663 In case of ndp or phy_err or AST_based_lookup_valid == 0, 664 this field will be set to 0 665 666 When set, this is a Mesh (11s) STA. 667 668 The interpretation of the A-MSDU 'Length' field in the MPDU 669 (if any) is decided by the e-numerations below. 670 671 <enum 0 MESH_DISABLE> 672 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes 673 the length of Mesh Control. 674 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes 675 the length of Mesh Control. 676 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and 677 excludes the length of Mesh Control. This is 802.11s-compliant. 678 679 <legal all> 680 */ 681 682 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000000000018 683 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 40 684 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MSB 41 685 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x0000030000000000 686 687 688 /* Description BSSID_HIT 689 690 In case of ndp or phy_err or AST_based_lookup_valid == 0, 691 this field will be set to 0 692 693 When set, the BSSID of the incoming frame matched one of 694 the 8 BSSID register values 695 696 <legal all> 697 */ 698 699 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018 700 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 701 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 702 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 703 704 705 /* Description BSSID_NUMBER 706 707 Field only valid when bssid_hit is set. 708 709 This number indicates which one out of the 8 BSSID register 710 values matched the incoming frame 711 <legal all> 712 */ 713 714 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018 715 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 716 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 717 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 718 719 720 /* Description TID 721 722 Field only valid when mpdu_qos_control_valid is set 723 724 The TID field in the QoS control field 725 <legal all> 726 */ 727 728 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018 729 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 730 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 731 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 732 733 734 /* Description RESERVED_7A 735 736 <legal 0> 737 */ 738 739 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018 740 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 741 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 742 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 743 744 745 /* Description PEER_META_DATA 746 747 In case of ndp or phy_err or AST_based_lookup_valid == 0, 748 this field will be set to 0 749 750 Meta data that SW has programmed in the Peer table entry 751 of the transmitting STA. 752 <legal all> 753 */ 754 755 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 756 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 757 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 758 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff 759 760 761 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 762 763 Field indicates what the reason was that this MPDU frame 764 was allowed to come into the receive path by RXPCU 765 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 766 filter programming of rxpcu 767 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 768 regular frame filter and would have been dropped, were 769 it not for the frame fitting into the 'monitor_client' category. 770 771 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 772 regular frame filter and also did not pass the rxpcu_monitor_client 773 filter. It would have been dropped accept that it did pass 774 the 'monitor_other' category. 775 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 776 the normal frame filter programming of RXPCU but additionally 777 fit into the 'monitor_override_client' category. 778 779 Note: for ndp frame, if it was expected because the preceding 780 NDPA was filter_pass, the setting rxpcu_filter_pass will 781 be used. This setting will also be used for every ndp frame 782 in case Promiscuous mode is enabled. 783 784 In case promiscuous is not enabled, and an NDP is not preceded 785 by a NPDA filter pass frame, the only other setting that 786 could appear here for the NDP is rxpcu_monitor_other. 787 (rxpcu has a configuration bit specifically for this scenario) 788 789 790 Note: for 791 <legal 0-3> 792 */ 793 794 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020 795 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 796 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 797 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 798 799 800 /* Description SW_FRAME_GROUP_ID 801 802 SW processes frames based on certain classifications. This 803 field indicates to what sw classification this MPDU is 804 mapped. 805 The classification is given in priority order 806 807 <enum 0 sw_frame_group_NDP_frame> Note: The corresponding 808 Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass 809 or rxpcu_monitor_other 810 811 <enum 1 sw_frame_group_Multicast_data> 812 <enum 2 sw_frame_group_Unicast_data> 813 <enum 3 sw_frame_group_Null_data > This includes mpdus of 814 type Data Null. 815 Hamilton v1 included QoS Data Null as well here. 816 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 817 Null frames except in UL MU or TB PPDUs. 818 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 819 QoS Null frames in UL MU or TB PPDUs. 820 821 <enum 4 sw_frame_group_mgmt_0000 > 822 <enum 5 sw_frame_group_mgmt_0001 > 823 <enum 6 sw_frame_group_mgmt_0010 > 824 <enum 7 sw_frame_group_mgmt_0011 > 825 <enum 8 sw_frame_group_mgmt_0100 > 826 <enum 9 sw_frame_group_mgmt_0101 > 827 <enum 10 sw_frame_group_mgmt_0110 > 828 <enum 11 sw_frame_group_mgmt_0111 > 829 <enum 12 sw_frame_group_mgmt_1000 > 830 <enum 13 sw_frame_group_mgmt_1001 > 831 <enum 14 sw_frame_group_mgmt_1010 > 832 <enum 15 sw_frame_group_mgmt_1011 > 833 <enum 16 sw_frame_group_mgmt_1100 > 834 <enum 17 sw_frame_group_mgmt_1101 > 835 <enum 18 sw_frame_group_mgmt_1110 > 836 <enum 19 sw_frame_group_mgmt_1111 > 837 838 <enum 20 sw_frame_group_ctrl_0000 > 839 <enum 21 sw_frame_group_ctrl_0001 > 840 <enum 22 sw_frame_group_ctrl_0010 > 841 <enum 23 sw_frame_group_ctrl_0011 > 842 <enum 24 sw_frame_group_ctrl_0100 > 843 <enum 25 sw_frame_group_ctrl_0101 > 844 <enum 26 sw_frame_group_ctrl_0110 > 845 <enum 27 sw_frame_group_ctrl_0111 > 846 <enum 28 sw_frame_group_ctrl_1000 > 847 <enum 29 sw_frame_group_ctrl_1001 > 848 <enum 30 sw_frame_group_ctrl_1010 > 849 <enum 31 sw_frame_group_ctrl_1011 > 850 <enum 32 sw_frame_group_ctrl_1100 > 851 <enum 33 sw_frame_group_ctrl_1101 > 852 <enum 34 sw_frame_group_ctrl_1110 > 853 <enum 35 sw_frame_group_ctrl_1111 > 854 855 <enum 36 sw_frame_group_unsupported> This covers type 3 856 and protocol version != 0 857 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 858 only be rxpcu_monitor_other 859 860 <enum 37 sw_frame_group_phy_error> PHY reported an error 861 862 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 863 be rxpcu_filter_pass 864 865 <legal 0-39> 866 */ 867 868 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020 869 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 870 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 871 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 872 873 874 /* Description NDP_FRAME 875 876 When set, the received frame was an NDP frame, and thus 877 there will be no MPDU data. 878 TODO: Should this be extended to 2-bit e-num? 879 <legal all> 880 */ 881 882 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020 883 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 884 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 885 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 886 887 888 /* Description PHY_ERR 889 890 When set, a PHY error was received before MAC received any 891 data, and thus there will be no MPDU data. 892 <legal all> 893 */ 894 895 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020 896 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 897 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 898 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 899 900 901 /* Description PHY_ERR_DURING_MPDU_HEADER 902 903 When set, a PHY error was received before MAC received the 904 complete MPDU header which was needed for proper decoding 905 906 <legal all> 907 */ 908 909 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020 910 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 911 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 912 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 913 914 915 /* Description PROTOCOL_VERSION_ERR 916 917 Set when RXPCU detected a version error in the Frame control 918 field 919 <legal all> 920 */ 921 922 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020 923 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 924 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 925 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 926 927 928 /* Description AST_BASED_LOOKUP_VALID 929 930 When set, AST based lookup for this frame has found a valid 931 result. 932 933 Note that for NDP frame this will never be set 934 <legal all> 935 */ 936 937 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020 938 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 939 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 940 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 941 942 943 /* Description RANGING 944 945 When set, a ranging NDPA or a ranging NDP was received. 946 947 This field is only for FW visibility. HW is not expected 948 to take any action on this. 949 <legal all> 950 */ 951 952 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_OFFSET 0x0000000000000020 953 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_LSB 46 954 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MSB 46 955 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MASK 0x0000400000000000 956 957 958 /* Description RESERVED_9A 959 960 <legal 0> 961 */ 962 963 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020 964 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47 965 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47 966 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000 967 968 969 /* Description PHY_PPDU_ID 970 971 A ppdu counter value that PHY increments for every PPDU 972 received. The counter value wraps around 973 <legal all> 974 */ 975 976 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020 977 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 978 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 979 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 980 981 982 /* Description AST_INDEX 983 984 This field indicates the index of the AST entry corresponding 985 to this MPDU. It is provided by the GSE module instantiated 986 in RXPCU. 987 A value of 0xFFFF indicates an invalid AST index, meaning 988 that No AST entry was found or NO AST search was performed 989 990 991 In case of ndp or phy_err, this field will be set to 0xFFFF 992 993 <legal all> 994 */ 995 996 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 997 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 998 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 999 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff 1000 1001 1002 /* Description SW_PEER_ID 1003 1004 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1005 this field will be set to 0 1006 1007 This field indicates a unique peer identifier. It is set 1008 equal to field 'sw_peer_id' from the AST entry 1009 1010 <legal all> 1011 */ 1012 1013 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 1014 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 1015 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 1016 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 1017 1018 1019 /* Description MPDU_FRAME_CONTROL_VALID 1020 1021 When set, the field Mpdu_Frame_control_field has valid information 1022 1023 1024 In case of ndp or phy_err, this field will never be set. 1025 1026 <legal all> 1027 */ 1028 1029 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028 1030 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32 1031 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32 1032 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000 1033 1034 1035 /* Description MPDU_DURATION_VALID 1036 1037 When set, the field Mpdu_duration_field has valid information 1038 1039 1040 In case of ndp or phy_err, this field will never be set. 1041 1042 <legal all> 1043 */ 1044 1045 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028 1046 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33 1047 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33 1048 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000 1049 1050 1051 /* Description MAC_ADDR_AD1_VALID 1052 1053 When set, the fields mac_addr_ad1_..... have valid information 1054 1055 1056 In case of ndp or phy_err, this field will never be set. 1057 1058 <legal all> 1059 */ 1060 1061 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028 1062 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34 1063 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34 1064 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000 1065 1066 1067 /* Description MAC_ADDR_AD2_VALID 1068 1069 When set, the fields mac_addr_ad2_..... have valid information 1070 1071 1072 For MPDUs without Address 2, this field will not be set. 1073 1074 1075 In case of ndp or phy_err, this field will never be set. 1076 1077 <legal all> 1078 */ 1079 1080 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028 1081 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35 1082 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35 1083 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000 1084 1085 1086 /* Description MAC_ADDR_AD3_VALID 1087 1088 When set, the fields mac_addr_ad3_..... have valid information 1089 1090 1091 For MPDUs without Address 3, this field will not be set. 1092 1093 1094 In case of ndp or phy_err, this field will never be set. 1095 1096 <legal all> 1097 */ 1098 1099 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028 1100 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36 1101 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36 1102 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000 1103 1104 1105 /* Description MAC_ADDR_AD4_VALID 1106 1107 When set, the fields mac_addr_ad4_..... have valid information 1108 1109 1110 For MPDUs without Address 4, this field will not be set. 1111 1112 1113 In case of ndp or phy_err, this field will never be set. 1114 1115 <legal all> 1116 */ 1117 1118 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028 1119 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37 1120 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37 1121 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000 1122 1123 1124 /* Description MPDU_SEQUENCE_CONTROL_VALID 1125 1126 When set, the fields mpdu_sequence_control_field and mpdu_sequence_number 1127 have valid information as well as field 1128 1129 For MPDUs without a sequence control field, this field will 1130 not be set. 1131 1132 In case of ndp or phy_err, this field will never be set. 1133 1134 <legal all> 1135 */ 1136 1137 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028 1138 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38 1139 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38 1140 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000 1141 1142 1143 /* Description MPDU_QOS_CONTROL_VALID 1144 1145 When set, the field mpdu_qos_control_field has valid information 1146 1147 1148 For MPDUs without a QoS control field, this field will not 1149 be set. 1150 1151 In case of ndp or phy_err, this field will never be set. 1152 1153 <legal all> 1154 */ 1155 1156 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 1157 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39 1158 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39 1159 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000 1160 1161 1162 /* Description MPDU_HT_CONTROL_VALID 1163 1164 When set, the field mpdu_HT_control_field has valid information 1165 1166 1167 For MPDUs without a HT control field, this field will not 1168 be set. 1169 1170 In case of ndp or phy_err, this field will never be set. 1171 1172 <legal all> 1173 */ 1174 1175 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028 1176 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40 1177 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40 1178 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000 1179 1180 1181 /* Description FRAME_ENCRYPTION_INFO_VALID 1182 1183 When set, the encryption related info fields, like IV and 1184 PN are valid 1185 1186 For MPDUs that are not encrypted, this will not be set. 1187 1188 In case of ndp or phy_err, this field will never be set. 1189 1190 <legal all> 1191 */ 1192 1193 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028 1194 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41 1195 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41 1196 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000 1197 1198 1199 /* Description MPDU_FRAGMENT_NUMBER 1200 1201 Field only valid when Mpdu_sequence_control_valid is set 1202 AND Fragment_flag is set 1203 1204 The fragment number from the 802.11 header 1205 1206 <legal all> 1207 */ 1208 1209 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028 1210 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42 1211 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45 1212 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000 1213 1214 1215 /* Description MORE_FRAGMENT_FLAG 1216 1217 The More Fragment bit setting from the MPDU header of the 1218 received frame 1219 1220 <legal all> 1221 */ 1222 1223 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028 1224 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46 1225 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46 1226 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000 1227 1228 1229 /* Description RESERVED_11A 1230 1231 <legal 0> 1232 */ 1233 1234 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028 1235 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47 1236 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47 1237 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000 1238 1239 1240 /* Description FR_DS 1241 1242 Field only valid when Mpdu_frame_control_valid is set 1243 1244 Set if the from DS bit is set in the frame control. 1245 <legal all> 1246 */ 1247 1248 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028 1249 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48 1250 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48 1251 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000 1252 1253 1254 /* Description TO_DS 1255 1256 Field only valid when Mpdu_frame_control_valid is set 1257 1258 Set if the to DS bit is set in the frame control. 1259 <legal all> 1260 */ 1261 1262 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028 1263 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49 1264 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49 1265 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000 1266 1267 1268 /* Description ENCRYPTED 1269 1270 Field only valid when Mpdu_frame_control_valid is set. 1271 1272 Protected bit from the frame control. 1273 <legal all> 1274 */ 1275 1276 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028 1277 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50 1278 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50 1279 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000 1280 1281 1282 /* Description MPDU_RETRY 1283 1284 Field only valid when Mpdu_frame_control_valid is set. 1285 1286 Retry bit from the frame control. Only valid when first_msdu 1287 is set. 1288 <legal all> 1289 */ 1290 1291 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028 1292 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51 1293 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51 1294 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000 1295 1296 1297 /* Description MPDU_SEQUENCE_NUMBER 1298 1299 Field only valid when Mpdu_sequence_control_valid is set. 1300 1301 1302 The sequence number from the 802.11 header. 1303 <legal all> 1304 */ 1305 1306 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028 1307 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52 1308 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63 1309 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000 1310 1311 1312 /* Description KEY_ID_OCTET 1313 1314 Field only valid when Frame_encryption_info_valid is set 1315 1316 1317 The key ID octet from the IV. 1318 1319 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1320 this field will be set to 0 1321 <legal all> 1322 */ 1323 1324 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 1325 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 1326 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 1327 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff 1328 1329 1330 /* Description NEW_PEER_ENTRY 1331 1332 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1333 this field will be set to 0 1334 1335 Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 1336 doesn't follow so RX DECRYPTION module either uses old 1337 peer entry or not decrypt. 1338 <legal all> 1339 */ 1340 1341 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 1342 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 1343 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 1344 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 1345 1346 1347 /* Description DECRYPT_NEEDED 1348 1349 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1350 this field will be set to 0 1351 1352 Set if decryption is needed. 1353 1354 Note: 1355 When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', 1356 RXPCU will also ensure that this bit is NOT set 1357 CRYPTO for that reason only needs to evaluate this bit and 1358 non of the other ones. 1359 <legal all> 1360 */ 1361 1362 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 1363 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 1364 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 1365 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 1366 1367 1368 /* Description DECAP_TYPE 1369 1370 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1371 this field will be set to 0 1372 1373 Used by the OLE during decapsulation. 1374 1375 Indicates the decapsulation that HW will perform: 1376 1377 <enum 0 RAW> No encapsulation 1378 <enum 1 Native_WiFi> 1379 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1380 1381 <enum 3 802_3> Indicate Ethernet 1382 1383 <legal all> 1384 */ 1385 1386 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 1387 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 1388 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 1389 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 1390 1391 1392 /* Description RX_INSERT_VLAN_C_TAG_PADDING 1393 1394 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1395 this field will be set to 0 1396 1397 Insert 4 byte of all zeros as VLAN tag if the rx payload 1398 does not have VLAN. Used during decapsulation. 1399 <legal all> 1400 */ 1401 1402 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 1403 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1404 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 1405 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 1406 1407 1408 /* Description RX_INSERT_VLAN_S_TAG_PADDING 1409 1410 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1411 this field will be set to 0 1412 1413 Insert 4 byte of all zeros as double VLAN tag if the rx 1414 payload does not have VLAN. Used during 1415 <legal all> 1416 */ 1417 1418 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 1419 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1420 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 1421 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 1422 1423 1424 /* Description STRIP_VLAN_C_TAG_DECAP 1425 1426 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1427 this field will be set to 0 1428 1429 Strip the VLAN during decapsulation. Used by the OLE. 1430 <legal all> 1431 */ 1432 1433 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 1434 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 1435 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 1436 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 1437 1438 1439 /* Description STRIP_VLAN_S_TAG_DECAP 1440 1441 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1442 this field will be set to 0 1443 1444 Strip the double VLAN during decapsulation. Used by the 1445 OLE. 1446 <legal all> 1447 */ 1448 1449 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 1450 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 1451 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 1452 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 1453 1454 1455 /* Description PRE_DELIM_COUNT 1456 1457 The number of delimiters before this MPDU. 1458 1459 Note that this number is cleared at PPDU start. 1460 1461 If this MPDU is the first received MPDU in the PPDU and 1462 this MPDU gets filtered-in, this field will indicate the 1463 number of delimiters located after the last MPDU in the 1464 previous PPDU. 1465 1466 If this MPDU is located after the first received MPDU in 1467 an PPDU, this field will indicate the number of delimiters 1468 located between the previous MPDU and this MPDU. 1469 1470 In case of ndp or phy_err, this field will indicate the 1471 number of delimiters located after the last MPDU in the 1472 previous PPDU. 1473 <legal all> 1474 */ 1475 1476 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 1477 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 1478 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 1479 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 1480 1481 1482 /* Description AMPDU_FLAG 1483 1484 When set, received frame was part of an A-MPDU. 1485 1486 In case of ndp or phy_err, this field will never be set. 1487 1488 <legal all> 1489 */ 1490 1491 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 1492 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 1493 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 1494 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 1495 1496 1497 /* Description BAR_FRAME 1498 1499 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1500 this field will be set to 0 1501 1502 When set, received frame is a BAR frame 1503 <legal all> 1504 */ 1505 1506 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 1507 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 1508 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 1509 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 1510 1511 1512 /* Description RAW_MPDU 1513 1514 Consumer: SW 1515 Producer: RXOLE 1516 1517 RXPCU sets this field to 0 and RXOLE overwrites it. 1518 1519 Set to 1 by RXOLE when it has not performed any 802.11 to 1520 Ethernet/Natvie WiFi header conversion on this MPDU. 1521 <legal all> 1522 */ 1523 1524 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 1525 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 1526 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 1527 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 1528 1529 1530 /* Description RESERVED_12 1531 1532 <legal 0> 1533 */ 1534 1535 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 1536 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 1537 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 1538 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 1539 1540 1541 /* Description MPDU_LENGTH 1542 1543 In case of ndp or phy_err this field will be set to 0 1544 1545 MPDU length before decapsulation. 1546 <legal all> 1547 */ 1548 1549 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 1550 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 1551 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 1552 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 1553 1554 1555 /* Description FIRST_MPDU 1556 1557 See definition in RX attention descriptor 1558 1559 In case of ndp or phy_err, this field will be set. Note 1560 however that there will not actually be any data contents 1561 in the MPDU. 1562 <legal all> 1563 */ 1564 1565 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 1566 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 1567 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 1568 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 1569 1570 1571 /* Description MCAST_BCAST 1572 1573 In case of ndp or phy_err or Phy_err_during_mpdu_header 1574 this field will be set to 0 1575 1576 See definition in RX attention descriptor 1577 <legal all> 1578 */ 1579 1580 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 1581 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 1582 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 1583 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 1584 1585 1586 /* Description AST_INDEX_NOT_FOUND 1587 1588 In case of ndp or phy_err or Phy_err_during_mpdu_header 1589 this field will be set to 0 1590 1591 See definition in RX attention descriptor 1592 <legal all> 1593 */ 1594 1595 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 1596 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 1597 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 1598 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 1599 1600 1601 /* Description AST_INDEX_TIMEOUT 1602 1603 In case of ndp or phy_err or Phy_err_during_mpdu_header 1604 this field will be set to 0 1605 1606 See definition in RX attention descriptor 1607 <legal all> 1608 */ 1609 1610 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 1611 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 1612 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 1613 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 1614 1615 1616 /* Description POWER_MGMT 1617 1618 In case of ndp or phy_err or Phy_err_during_mpdu_header 1619 this field will be set to 0 1620 1621 See definition in RX attention descriptor 1622 <legal all> 1623 */ 1624 1625 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 1626 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 1627 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 1628 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 1629 1630 1631 /* Description NON_QOS 1632 1633 In case of ndp or phy_err or Phy_err_during_mpdu_header 1634 this field will be set to 1 1635 1636 See definition in RX attention descriptor 1637 <legal all> 1638 */ 1639 1640 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 1641 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 1642 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 1643 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 1644 1645 1646 /* Description NULL_DATA 1647 1648 In case of ndp or phy_err or Phy_err_during_mpdu_header 1649 this field will be set to 0 1650 1651 See definition in RX attention descriptor 1652 <legal all> 1653 */ 1654 1655 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 1656 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 1657 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 1658 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 1659 1660 1661 /* Description MGMT_TYPE 1662 1663 In case of ndp or phy_err or Phy_err_during_mpdu_header 1664 this field will be set to 0 1665 1666 See definition in RX attention descriptor 1667 <legal all> 1668 */ 1669 1670 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 1671 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 1672 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 1673 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 1674 1675 1676 /* Description CTRL_TYPE 1677 1678 In case of ndp or phy_err or Phy_err_during_mpdu_header 1679 this field will be set to 0 1680 1681 See definition in RX attention descriptor 1682 <legal all> 1683 */ 1684 1685 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 1686 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 1687 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 1688 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 1689 1690 1691 /* Description MORE_DATA 1692 1693 In case of ndp or phy_err or Phy_err_during_mpdu_header 1694 this field will be set to 0 1695 1696 See definition in RX attention descriptor 1697 <legal all> 1698 */ 1699 1700 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 1701 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 1702 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 1703 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 1704 1705 1706 /* Description EOSP 1707 1708 In case of ndp or phy_err or Phy_err_during_mpdu_header 1709 this field will be set to 0 1710 1711 See definition in RX attention descriptor 1712 <legal all> 1713 */ 1714 1715 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 1716 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 1717 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 1718 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 1719 1720 1721 /* Description FRAGMENT_FLAG 1722 1723 In case of ndp or phy_err or Phy_err_during_mpdu_header 1724 this field will be set to 0 1725 1726 See definition in RX attention descriptor 1727 <legal all> 1728 */ 1729 1730 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 1731 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 1732 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 1733 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 1734 1735 1736 /* Description ORDER 1737 1738 In case of ndp or phy_err or Phy_err_during_mpdu_header 1739 this field will be set to 0 1740 1741 See definition in RX attention descriptor 1742 1743 <legal all> 1744 */ 1745 1746 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 1747 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 1748 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 1749 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 1750 1751 1752 /* Description U_APSD_TRIGGER 1753 1754 In case of ndp or phy_err or Phy_err_during_mpdu_header 1755 this field will be set to 0 1756 1757 See definition in RX attention descriptor 1758 <legal all> 1759 */ 1760 1761 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 1762 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 1763 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 1764 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 1765 1766 1767 /* Description ENCRYPT_REQUIRED 1768 1769 In case of ndp or phy_err or Phy_err_during_mpdu_header 1770 this field will be set to 0 1771 1772 See definition in RX attention descriptor 1773 <legal all> 1774 */ 1775 1776 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 1777 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 1778 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 1779 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 1780 1781 1782 /* Description DIRECTED 1783 1784 In case of ndp or phy_err or Phy_err_during_mpdu_header 1785 this field will be set to 0 1786 1787 See definition in RX attention descriptor 1788 <legal all> 1789 */ 1790 1791 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 1792 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 1793 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 1794 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 1795 1796 1797 /* Description AMSDU_PRESENT 1798 1799 Field only valid when Mpdu_qos_control_valid is set 1800 1801 The 'amsdu_present' bit within the QoS control field of 1802 the MPDU 1803 <legal all> 1804 */ 1805 1806 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 1807 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 1808 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 1809 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 1810 1811 1812 /* Description RESERVED_13 1813 1814 Field only valid when Mpdu_qos_control_valid is set 1815 1816 This indicates whether the 'Ack policy' field within the 1817 QoS control field of the MPDU indicates 'no-Ack.' 1818 <legal all> 1819 */ 1820 1821 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 1822 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 1823 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 1824 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 1825 1826 1827 /* Description MPDU_FRAME_CONTROL_FIELD 1828 1829 Field only valid when Mpdu_frame_control_valid is set 1830 1831 The frame control field of this received MPDU. 1832 1833 Field only valid when Ndp_frame and phy_err are NOT set 1834 1835 Bytes 0 + 1 of the received MPDU 1836 <legal all> 1837 */ 1838 1839 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 1840 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 1841 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 1842 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff 1843 1844 1845 /* Description MPDU_DURATION_FIELD 1846 1847 Field only valid when Mpdu_duration_valid is set 1848 1849 The duration field of this received MPDU. 1850 <legal all> 1851 */ 1852 1853 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 1854 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 1855 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 1856 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 1857 1858 1859 /* Description MAC_ADDR_AD1_31_0 1860 1861 Field only valid when mac_addr_ad1_valid is set 1862 1863 The Least Significant 4 bytes of the Received Frames MAC 1864 Address AD1 1865 <legal all> 1866 */ 1867 1868 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 1869 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 1870 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 1871 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 1872 1873 1874 /* Description MAC_ADDR_AD1_47_32 1875 1876 Field only valid when mac_addr_ad1_valid is set 1877 1878 The 2 most significant bytes of the Received Frames MAC 1879 Address AD1 1880 <legal all> 1881 */ 1882 1883 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 1884 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 1885 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 1886 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff 1887 1888 1889 /* Description MAC_ADDR_AD2_15_0 1890 1891 Field only valid when mac_addr_ad2_valid is set 1892 1893 The Least Significant 2 bytes of the Received Frames MAC 1894 Address AD2 1895 <legal all> 1896 */ 1897 1898 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 1899 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 1900 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 1901 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 1902 1903 1904 /* Description MAC_ADDR_AD2_47_16 1905 1906 Field only valid when mac_addr_ad2_valid is set 1907 1908 The 4 most significant bytes of the Received Frames MAC 1909 Address AD2 1910 <legal all> 1911 */ 1912 1913 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 1914 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 1915 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 1916 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 1917 1918 1919 /* Description MAC_ADDR_AD3_31_0 1920 1921 Field only valid when mac_addr_ad3_valid is set 1922 1923 The Least Significant 4 bytes of the Received Frames MAC 1924 Address AD3 1925 <legal all> 1926 */ 1927 1928 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 1929 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 1930 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 1931 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff 1932 1933 1934 /* Description MAC_ADDR_AD3_47_32 1935 1936 Field only valid when mac_addr_ad3_valid is set 1937 1938 The 2 most significant bytes of the Received Frames MAC 1939 Address AD3 1940 <legal all> 1941 */ 1942 1943 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 1944 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 1945 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 1946 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 1947 1948 1949 /* Description MPDU_SEQUENCE_CONTROL_FIELD 1950 1951 Field only valid when mpdu_sequence_control_valid is set 1952 1953 1954 The sequence control field of the MPDU 1955 <legal all> 1956 */ 1957 1958 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 1959 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 1960 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 1961 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 1962 1963 1964 /* Description MAC_ADDR_AD4_31_0 1965 1966 Field only valid when mac_addr_ad4_valid is set 1967 1968 The Least Significant 4 bytes of the Received Frames MAC 1969 Address AD4 1970 <legal all> 1971 */ 1972 1973 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 1974 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 1975 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 1976 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff 1977 1978 1979 /* Description MAC_ADDR_AD4_47_32 1980 1981 Field only valid when mac_addr_ad4_valid is set 1982 1983 The 2 most significant bytes of the Received Frames MAC 1984 Address AD4 1985 <legal all> 1986 */ 1987 1988 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 1989 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 1990 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 1991 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 1992 1993 1994 /* Description MPDU_QOS_CONTROL_FIELD 1995 1996 Field only valid when mpdu_qos_control_valid is set 1997 1998 The sequence control field of the MPDU 1999 <legal all> 2000 */ 2001 2002 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 2003 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 2004 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 2005 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 2006 2007 2008 /* Description MPDU_HT_CONTROL_FIELD 2009 2010 Field only valid when mpdu_qos_control_valid is set 2011 2012 The HT control field of the MPDU 2013 <legal all> 2014 */ 2015 2016 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 2017 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 2018 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 2019 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 2020 2021 2022 /* Description VDEV_ID 2023 2024 Consumer: RXOLE 2025 Producer: FW 2026 2027 Virtual device associated with this peer 2028 2029 RXOLE uses this to determine intra-BSS routing. 2030 2031 <legal all> 2032 */ 2033 2034 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 2035 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 2036 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 2037 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 2038 2039 2040 /* Description SERVICE_CODE 2041 2042 Opaque service code between PPE and Wi-Fi 2043 2044 This field gets passed on by REO to PPE in the EDMA descriptor 2045 ('REO_TO_PPE_RING'). 2046 2047 <legal all> 2048 */ 2049 2050 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 2051 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 2052 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 2053 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 2054 2055 2056 /* Description PRIORITY_VALID 2057 2058 This field gets passed on by REO to PPE in the EDMA descriptor 2059 ('REO_TO_PPE_RING'). 2060 2061 <legal all> 2062 */ 2063 2064 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 2065 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 2066 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 2067 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 2068 2069 2070 /* Description SRC_INFO 2071 2072 Source (virtual) device/interface info. associated with 2073 this peer 2074 2075 This field gets passed on by REO to PPE in the EDMA descriptor 2076 ('REO_TO_PPE_RING'). 2077 2078 <legal all> 2079 */ 2080 2081 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 2082 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 2083 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 2084 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 2085 2086 2087 /* Description RESERVED_23A 2088 2089 <legal 0> 2090 */ 2091 2092 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 2093 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 2094 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 2095 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 2096 2097 2098 /* Description MULTI_LINK_ADDR_AD1_AD2_VALID 2099 2100 If set, Rx OLE shall convert Address1 and Address2 of received 2101 data frames to multi-link addresses during decapsulation 2102 to Ethernet or Native WiFi 2103 <legal all> 2104 */ 2105 2106 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000000000000058 2107 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 63 2108 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 63 2109 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x8000000000000000 2110 2111 2112 /* Description MULTI_LINK_ADDR_AD1_31_0 2113 2114 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2115 2116 2117 Multi-link receiver address (address1), bits [31:0] 2118 */ 2119 2120 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000060 2121 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_LSB 0 2122 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MSB 31 2123 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff 2124 2125 2126 /* Description MULTI_LINK_ADDR_AD1_47_32 2127 2128 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2129 2130 2131 Multi-link receiver address (address1), bits [47:32] 2132 */ 2133 2134 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000060 2135 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_LSB 32 2136 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MSB 47 2137 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 2138 2139 2140 /* Description MULTI_LINK_ADDR_AD2_15_0 2141 2142 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2143 2144 2145 Multi-link transmitter address (address2), bits [15:0] 2146 */ 2147 2148 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000060 2149 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_LSB 48 2150 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MSB 63 2151 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 2152 2153 2154 /* Description MULTI_LINK_ADDR_AD2_47_16 2155 2156 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2157 2158 2159 Multi-link transmitter address (address2), bits [47:16] 2160 */ 2161 2162 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000068 2163 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_LSB 0 2164 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MSB 31 2165 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff 2166 2167 2168 /* Description AUTHORIZED_TO_SEND_WDS 2169 2170 If not set, RXDMA shall perform error-routing for WDS packets 2171 as the sender is not authorized and might misuse WDS frame 2172 format to inject packets with arbitrary DA/SA. 2173 <legal all> 2174 */ 2175 2176 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 2177 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 2178 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 2179 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 2180 2181 2182 /* Description RESERVED_27A 2183 2184 <legal 0> 2185 */ 2186 2187 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 2188 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33 2189 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 2190 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000 2191 2192 2193 /* Description RESERVED_28A 2194 2195 <legal 0> 2196 */ 2197 2198 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070 2199 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 2200 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 2201 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff 2202 2203 2204 /* Description RESERVED_29A 2205 2206 <legal 0> 2207 */ 2208 2209 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 2210 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32 2211 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 2212 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000 2213 2214 2215 2216 #endif // RX_MPDU_START 2217