1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MPDU_INFO_H_ 27 #define _RX_MPDU_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rxpt_classify_info.h" 32 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 33 34 35 struct rx_mpdu_info { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct rxpt_classify_info rxpt_classify_info_details; 38 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 39 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 40 receive_queue_number : 16, // [23:8] 41 pre_delim_err_warning : 1, // [24:24] 42 first_delim_err : 1, // [25:25] 43 reserved_2a : 6; // [31:26] 44 uint32_t pn_31_0 : 32; // [31:0] 45 uint32_t pn_63_32 : 32; // [31:0] 46 uint32_t pn_95_64 : 32; // [31:0] 47 uint32_t pn_127_96 : 32; // [31:0] 48 uint32_t epd_en : 1, // [0:0] 49 all_frames_shall_be_encrypted : 1, // [1:1] 50 encrypt_type : 4, // [5:2] 51 wep_key_width_for_variable_key : 2, // [7:6] 52 mesh_sta : 2, // [9:8] 53 bssid_hit : 1, // [10:10] 54 bssid_number : 4, // [14:11] 55 tid : 4, // [18:15] 56 reserved_7a : 13; // [31:19] 57 uint32_t peer_meta_data : 32; // [31:0] 58 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 59 sw_frame_group_id : 7, // [8:2] 60 ndp_frame : 1, // [9:9] 61 phy_err : 1, // [10:10] 62 phy_err_during_mpdu_header : 1, // [11:11] 63 protocol_version_err : 1, // [12:12] 64 ast_based_lookup_valid : 1, // [13:13] 65 ranging : 1, // [14:14] 66 reserved_9a : 1, // [15:15] 67 phy_ppdu_id : 16; // [31:16] 68 uint32_t ast_index : 16, // [15:0] 69 sw_peer_id : 16; // [31:16] 70 uint32_t mpdu_frame_control_valid : 1, // [0:0] 71 mpdu_duration_valid : 1, // [1:1] 72 mac_addr_ad1_valid : 1, // [2:2] 73 mac_addr_ad2_valid : 1, // [3:3] 74 mac_addr_ad3_valid : 1, // [4:4] 75 mac_addr_ad4_valid : 1, // [5:5] 76 mpdu_sequence_control_valid : 1, // [6:6] 77 mpdu_qos_control_valid : 1, // [7:7] 78 mpdu_ht_control_valid : 1, // [8:8] 79 frame_encryption_info_valid : 1, // [9:9] 80 mpdu_fragment_number : 4, // [13:10] 81 more_fragment_flag : 1, // [14:14] 82 reserved_11a : 1, // [15:15] 83 fr_ds : 1, // [16:16] 84 to_ds : 1, // [17:17] 85 encrypted : 1, // [18:18] 86 mpdu_retry : 1, // [19:19] 87 mpdu_sequence_number : 12; // [31:20] 88 uint32_t key_id_octet : 8, // [7:0] 89 new_peer_entry : 1, // [8:8] 90 decrypt_needed : 1, // [9:9] 91 decap_type : 2, // [11:10] 92 rx_insert_vlan_c_tag_padding : 1, // [12:12] 93 rx_insert_vlan_s_tag_padding : 1, // [13:13] 94 strip_vlan_c_tag_decap : 1, // [14:14] 95 strip_vlan_s_tag_decap : 1, // [15:15] 96 pre_delim_count : 12, // [27:16] 97 ampdu_flag : 1, // [28:28] 98 bar_frame : 1, // [29:29] 99 raw_mpdu : 1, // [30:30] 100 reserved_12 : 1; // [31:31] 101 uint32_t mpdu_length : 14, // [13:0] 102 first_mpdu : 1, // [14:14] 103 mcast_bcast : 1, // [15:15] 104 ast_index_not_found : 1, // [16:16] 105 ast_index_timeout : 1, // [17:17] 106 power_mgmt : 1, // [18:18] 107 non_qos : 1, // [19:19] 108 null_data : 1, // [20:20] 109 mgmt_type : 1, // [21:21] 110 ctrl_type : 1, // [22:22] 111 more_data : 1, // [23:23] 112 eosp : 1, // [24:24] 113 fragment_flag : 1, // [25:25] 114 order : 1, // [26:26] 115 u_apsd_trigger : 1, // [27:27] 116 encrypt_required : 1, // [28:28] 117 directed : 1, // [29:29] 118 amsdu_present : 1, // [30:30] 119 reserved_13 : 1; // [31:31] 120 uint32_t mpdu_frame_control_field : 16, // [15:0] 121 mpdu_duration_field : 16; // [31:16] 122 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 123 uint32_t mac_addr_ad1_47_32 : 16, // [15:0] 124 mac_addr_ad2_15_0 : 16; // [31:16] 125 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 126 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 127 uint32_t mac_addr_ad3_47_32 : 16, // [15:0] 128 mpdu_sequence_control_field : 16; // [31:16] 129 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 130 uint32_t mac_addr_ad4_47_32 : 16, // [15:0] 131 mpdu_qos_control_field : 16; // [31:16] 132 uint32_t mpdu_ht_control_field : 32; // [31:0] 133 uint32_t vdev_id : 8, // [7:0] 134 service_code : 9, // [16:8] 135 priority_valid : 1, // [17:17] 136 src_info : 12, // [29:18] 137 reserved_23a : 1, // [30:30] 138 multi_link_addr_ad1_ad2_valid : 1; // [31:31] 139 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 140 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 141 multi_link_addr_ad2_15_0 : 16; // [31:16] 142 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 143 uint32_t authorized_to_send_wds : 1, // [0:0] 144 reserved_27a : 31; // [31:1] 145 uint32_t reserved_28a : 32; // [31:0] 146 uint32_t reserved_29a : 32; // [31:0] 147 #else 148 struct rxpt_classify_info rxpt_classify_info_details; 149 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 150 uint32_t reserved_2a : 6, // [31:26] 151 first_delim_err : 1, // [25:25] 152 pre_delim_err_warning : 1, // [24:24] 153 receive_queue_number : 16, // [23:8] 154 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 155 uint32_t pn_31_0 : 32; // [31:0] 156 uint32_t pn_63_32 : 32; // [31:0] 157 uint32_t pn_95_64 : 32; // [31:0] 158 uint32_t pn_127_96 : 32; // [31:0] 159 uint32_t reserved_7a : 13, // [31:19] 160 tid : 4, // [18:15] 161 bssid_number : 4, // [14:11] 162 bssid_hit : 1, // [10:10] 163 mesh_sta : 2, // [9:8] 164 wep_key_width_for_variable_key : 2, // [7:6] 165 encrypt_type : 4, // [5:2] 166 all_frames_shall_be_encrypted : 1, // [1:1] 167 epd_en : 1; // [0:0] 168 uint32_t peer_meta_data : 32; // [31:0] 169 uint32_t phy_ppdu_id : 16, // [31:16] 170 reserved_9a : 1, // [15:15] 171 ranging : 1, // [14:14] 172 ast_based_lookup_valid : 1, // [13:13] 173 protocol_version_err : 1, // [12:12] 174 phy_err_during_mpdu_header : 1, // [11:11] 175 phy_err : 1, // [10:10] 176 ndp_frame : 1, // [9:9] 177 sw_frame_group_id : 7, // [8:2] 178 rxpcu_mpdu_filter_in_category : 2; // [1:0] 179 uint32_t sw_peer_id : 16, // [31:16] 180 ast_index : 16; // [15:0] 181 uint32_t mpdu_sequence_number : 12, // [31:20] 182 mpdu_retry : 1, // [19:19] 183 encrypted : 1, // [18:18] 184 to_ds : 1, // [17:17] 185 fr_ds : 1, // [16:16] 186 reserved_11a : 1, // [15:15] 187 more_fragment_flag : 1, // [14:14] 188 mpdu_fragment_number : 4, // [13:10] 189 frame_encryption_info_valid : 1, // [9:9] 190 mpdu_ht_control_valid : 1, // [8:8] 191 mpdu_qos_control_valid : 1, // [7:7] 192 mpdu_sequence_control_valid : 1, // [6:6] 193 mac_addr_ad4_valid : 1, // [5:5] 194 mac_addr_ad3_valid : 1, // [4:4] 195 mac_addr_ad2_valid : 1, // [3:3] 196 mac_addr_ad1_valid : 1, // [2:2] 197 mpdu_duration_valid : 1, // [1:1] 198 mpdu_frame_control_valid : 1; // [0:0] 199 uint32_t reserved_12 : 1, // [31:31] 200 raw_mpdu : 1, // [30:30] 201 bar_frame : 1, // [29:29] 202 ampdu_flag : 1, // [28:28] 203 pre_delim_count : 12, // [27:16] 204 strip_vlan_s_tag_decap : 1, // [15:15] 205 strip_vlan_c_tag_decap : 1, // [14:14] 206 rx_insert_vlan_s_tag_padding : 1, // [13:13] 207 rx_insert_vlan_c_tag_padding : 1, // [12:12] 208 decap_type : 2, // [11:10] 209 decrypt_needed : 1, // [9:9] 210 new_peer_entry : 1, // [8:8] 211 key_id_octet : 8; // [7:0] 212 uint32_t reserved_13 : 1, // [31:31] 213 amsdu_present : 1, // [30:30] 214 directed : 1, // [29:29] 215 encrypt_required : 1, // [28:28] 216 u_apsd_trigger : 1, // [27:27] 217 order : 1, // [26:26] 218 fragment_flag : 1, // [25:25] 219 eosp : 1, // [24:24] 220 more_data : 1, // [23:23] 221 ctrl_type : 1, // [22:22] 222 mgmt_type : 1, // [21:21] 223 null_data : 1, // [20:20] 224 non_qos : 1, // [19:19] 225 power_mgmt : 1, // [18:18] 226 ast_index_timeout : 1, // [17:17] 227 ast_index_not_found : 1, // [16:16] 228 mcast_bcast : 1, // [15:15] 229 first_mpdu : 1, // [14:14] 230 mpdu_length : 14; // [13:0] 231 uint32_t mpdu_duration_field : 16, // [31:16] 232 mpdu_frame_control_field : 16; // [15:0] 233 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 234 uint32_t mac_addr_ad2_15_0 : 16, // [31:16] 235 mac_addr_ad1_47_32 : 16; // [15:0] 236 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 237 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 238 uint32_t mpdu_sequence_control_field : 16, // [31:16] 239 mac_addr_ad3_47_32 : 16; // [15:0] 240 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 241 uint32_t mpdu_qos_control_field : 16, // [31:16] 242 mac_addr_ad4_47_32 : 16; // [15:0] 243 uint32_t mpdu_ht_control_field : 32; // [31:0] 244 uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] 245 reserved_23a : 1, // [30:30] 246 src_info : 12, // [29:18] 247 priority_valid : 1, // [17:17] 248 service_code : 9, // [16:8] 249 vdev_id : 8; // [7:0] 250 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 251 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 252 multi_link_addr_ad1_47_32 : 16; // [15:0] 253 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 254 uint32_t reserved_27a : 31, // [31:1] 255 authorized_to_send_wds : 1; // [0:0] 256 uint32_t reserved_28a : 32; // [31:0] 257 uint32_t reserved_29a : 32; // [31:0] 258 #endif 259 }; 260 261 262 /* Description RXPT_CLASSIFY_INFO_DETAILS 263 264 In case of ndp or phy_err or AST_based_lookup_valid == 0, 265 this field will be set to 0 266 267 RXOLE related classification info 268 <legal all 269 */ 270 271 272 /* Description REO_DESTINATION_INDICATION 273 274 The ID of the REO exit ring where the MSDU frame shall push 275 after (MPDU level) reordering has finished. 276 277 <enum 0 reo_destination_sw0> Reo will push the frame into 278 the REO2SW0 ring 279 <enum 1 reo_destination_sw1> Reo will push the frame into 280 the REO2SW1 ring 281 <enum 2 reo_destination_sw2> Reo will push the frame into 282 the REO2SW2 ring 283 <enum 3 reo_destination_sw3> Reo will push the frame into 284 the REO2SW3 ring 285 <enum 4 reo_destination_sw4> Reo will push the frame into 286 the REO2SW4 ring 287 <enum 5 reo_destination_release> Reo will push the frame 288 into the REO_release ring 289 <enum 6 reo_destination_fw> Reo will push the frame into 290 the REO2FW ring 291 <enum 7 reo_destination_sw5> Reo will push the frame into 292 the REO2SW5 ring (REO remaps this in chips without REO2SW5 293 ring, e.g. Pine) 294 <enum 8 reo_destination_sw6> Reo will push the frame into 295 the REO2SW6 ring (REO remaps this in chips without REO2SW6 296 ring, e.g. Pine) 297 <enum 9 reo_destination_sw7> Reo will push the frame into 298 the REO2SW7 ring (REO remaps this in chips without REO2SW7 299 ring) 300 <enum 10 reo_destination_sw8> Reo will push the frame into 301 the REO2SW8 ring (REO remaps this in chips without REO2SW8 302 ring) 303 <enum 11 reo_destination_11> REO remaps this 304 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 305 REO remaps this 306 <enum 14 reo_destination_14> REO remaps this 307 <enum 15 reo_destination_15> REO remaps this 308 <enum 16 reo_destination_16> REO remaps this 309 <enum 17 reo_destination_17> REO remaps this 310 <enum 18 reo_destination_18> REO remaps this 311 <enum 19 reo_destination_19> REO remaps this 312 <enum 20 reo_destination_20> REO remaps this 313 <enum 21 reo_destination_21> REO remaps this 314 <enum 22 reo_destination_22> REO remaps this 315 <enum 23 reo_destination_23> REO remaps this 316 <enum 24 reo_destination_24> REO remaps this 317 <enum 25 reo_destination_25> REO remaps this 318 <enum 26 reo_destination_26> REO remaps this 319 <enum 27 reo_destination_27> REO remaps this 320 <enum 28 reo_destination_28> REO remaps this 321 <enum 29 reo_destination_29> REO remaps this 322 <enum 30 reo_destination_30> REO remaps this 323 <enum 31 reo_destination_31> REO remaps this 324 325 <legal all> 326 */ 327 328 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 329 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 330 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 331 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 332 333 334 /* Description LMAC_PEER_ID_MSB 335 336 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 337 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 338 hash[3:0]} using the chosen Toeplitz hash from Common Parser 339 if flow search fails. 340 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 341 's not 2'b00, Rx OLE uses a REO desination indication of 342 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz 343 hash from Common Parser if flow search fails. 344 This LMAC/peer-based routing is not supported in Hastings80 345 and HastingsPrime. 346 <legal all> 347 */ 348 349 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 350 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 351 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 352 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 353 354 355 /* Description USE_FLOW_ID_TOEPLITZ_CLFY 356 357 Indication to Rx OLE to enable REO destination routing based 358 on the chosen Toeplitz hash from Common Parser, in case 359 flow search fails 360 <legal all> 361 */ 362 363 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 364 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 365 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 366 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 367 368 369 /* Description PKT_SELECTION_FP_UCAST_DATA 370 371 Filter pass Unicast data frame (matching rxpcu_filter_pass 372 and sw_frame_group_Unicast_data) routing selection 373 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 374 375 1'b0: source and destination rings are selected from the 376 RxOLE register settings for the packet type 377 378 1'b1: source ring and destination ring is selected from 379 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 380 fields in this STRUCT 381 <legal all> 382 */ 383 384 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 385 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 386 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 387 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 388 389 390 /* Description PKT_SELECTION_FP_MCAST_DATA 391 392 Filter pass Multicast data frame (matching rxpcu_filter_pass 393 and sw_frame_group_Multicast_data) routing selection 394 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 395 396 1'b0: source and destination rings are selected from the 397 RxOLE register settings for the packet type 398 399 1'b1: source ring and destination ring is selected from 400 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 401 fields in this STRUCT 402 <legal all> 403 */ 404 405 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 406 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 407 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 408 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 409 410 411 /* Description PKT_SELECTION_FP_1000 412 413 Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) 414 routing selection 415 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 416 417 1'b0: source and destination rings are selected from the 418 RxOLE register settings for the packet type 419 420 1'b1: source ring and destination ring is selected from 421 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 422 fields in this STRUCT 423 <legal all> 424 */ 425 426 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 427 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 428 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 429 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 430 431 432 /* Description RXDMA0_SOURCE_RING_SELECTION 433 434 Field only valid when for the received frame type the corresponding 435 pkt_selection_fp_... bit is set 436 437 <enum 0 sw2rxdma0_0_buf_source_ring> The data buffer for 438 this frame shall be sourced by sw2rxdma0 buffer source 439 ring. 440 <enum 1 fw2rxdma0_pmac0_buf_source_ring> The data buffer 441 for this frame shall be sourced by fw2rxdma buffer source 442 ring for PMAC0. 443 <enum 2 sw2rxdma0_1_buf_source_ring> The data buffer for 444 this frame shall be sourced by sw2rxdma1 buffer source 445 ring. 446 <enum 3 no_buffer_rxdma0_ring> The frame shall not be written 447 to any data buffer. 448 <enum 4 sw2rxdma0_exception_buf_source_ring> The data buffer 449 for this frame shall be sourced by sw2rxdma_exception buffer 450 source ring. 451 <enum 5 fw2rxdma0_pmac1_buf_source_ring> The data buffer 452 for this frame shall be sourced by fw2rxdma buffer source 453 ring for PMAC1. 454 455 <legal 0-5> 456 */ 457 458 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 459 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 460 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 461 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 462 463 464 /* Description RXDMA0_DESTINATION_RING_SELECTION 465 466 Field only valid when for the received frame type the corresponding 467 pkt_selection_fp_... bit is set 468 469 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 470 to the Release ring. Effectively this means the frame needs 471 to be dropped. 472 <enum 1 rxdma2fw_pmac0_ring> RXDMA0 shall push the frame 473 to the FW ring for PMAC0. 474 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to the 475 SW ring. 476 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 477 the REO entrance ring. 478 <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 479 to the FW ring for PMAC1. 480 <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 481 to the first MLO REO entrance ring. 482 <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 483 to the second MLO REO entrance ring. 484 485 <legal 0-6> 486 */ 487 488 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 489 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 490 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 491 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 492 493 494 /* Description MCAST_ECHO_DROP_ENABLE 495 496 If set, for multicast packets, multicast echo check (i.e. 497 SA search with mcast_echo_check = 1) shall be performed 498 by RXOLE, and any multicast echo packets should be indicated 499 to RXDMA for release to WBM 500 501 <legal all> 502 */ 503 504 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 505 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 506 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 507 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 508 509 510 /* Description WDS_LEARNING_DETECT_EN 511 512 If set, WDS learning detection based on SA search and notification 513 to FW (using RXDMA0 status ring) is enabled and the "timestamp" 514 field in address search failure cache-only entry should 515 be used to avoid multiple WDS learning notifications. 516 517 <legal all> 518 */ 519 520 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 521 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 522 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 523 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 524 525 526 /* Description INTRABSS_CHECK_EN 527 528 If set, intra-BSS routing detection is enabled 529 530 <legal all> 531 */ 532 533 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 534 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 535 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 536 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 537 538 539 /* Description USE_PPE 540 541 Indicates to RXDMA to ignore the REO_destination_indication 542 and use a programmed value corresponding to the REO2PPE 543 ring 544 545 This override to REO2PPE for packets requiring multiple 546 buffers shall be disabled based on an RXDMA configuration, 547 as PPE may not support such packets. 548 549 Supported only in full AP chips like Waikiki, not in client/soft 550 AP chips like Hamilton 551 <legal all> 552 */ 553 554 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 555 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 556 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 557 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 558 559 560 /* Description PPE_ROUTING_ENABLE 561 562 Global enable/disable bit for routing to PPE, used to disable 563 PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' 564 565 566 This is set by SW for peers which are being handled by a 567 host SW/accelerator subsystem that also handles packet 568 buffer management for WiFi-to-PPE routing. 569 570 This is cleared by SW for peers which are being handled 571 by a different subsystem, completely disabling WiFi-to-PPE 572 routing for such peers. 573 574 <legal all> 575 */ 576 577 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 578 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 579 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 580 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 581 582 583 /* Description RESERVED_0B 584 585 <legal 0> 586 */ 587 588 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 589 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 590 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 591 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 592 593 594 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 595 596 In case of ndp or phy_err or AST_based_lookup_valid == 0, 597 this field will be set to 0 598 599 Address (lower 32 bits) of the REO queue descriptor. 600 601 If no Peer entry lookup happened for this frame, the value 602 wil be set to 0, and the frame shall never be pushed to 603 REO entrance ring. 604 <legal all> 605 */ 606 607 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 608 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 609 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 610 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 611 612 613 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 614 615 In case of ndp or phy_err or AST_based_lookup_valid == 0, 616 this field will be set to 0 617 618 Address (upper 8 bits) of the REO queue descriptor. 619 620 If no Peer entry lookup happened for this frame, the value 621 wil be set to 0, and the frame shall never be pushed to 622 REO entrance ring. 623 <legal all> 624 */ 625 626 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 627 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 628 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 629 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 630 631 632 /* Description RECEIVE_QUEUE_NUMBER 633 634 In case of ndp or phy_err or AST_based_lookup_valid == 0, 635 this field will be set to 0 636 637 Indicates the MPDU queue ID to which this MPDU link descriptor 638 belongs 639 Used for tracking and debugging 640 <legal all> 641 */ 642 643 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 644 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 645 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 646 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 647 648 649 /* Description PRE_DELIM_ERR_WARNING 650 651 Indicates that a delimiter FCS error was found in between 652 the Previous MPDU and this MPDU. 653 654 Note that this is just a warning, and does not mean that 655 this MPDU is corrupted in any way. If it is, there will 656 be other errors indicated such as FCS or decrypt errors 657 658 659 In case of ndp or phy_err, this field will indicate at least 660 one of delimiters located after the last MPDU in the previous 661 PPDU has been corrupted. 662 */ 663 664 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 665 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 666 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 667 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 668 669 670 /* Description FIRST_DELIM_ERR 671 672 Indicates that the first delimiter had a FCS failure. Only 673 valid when first_mpdu and first_msdu are set. 674 675 In case of ndp or phy_err, this field will never be set. 676 677 */ 678 679 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 680 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 681 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 682 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 683 684 685 /* Description RESERVED_2A 686 687 <legal 0> 688 */ 689 690 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 691 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 692 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 693 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 694 695 696 /* Description PN_31_0 697 698 Field only valid when Frame_encryption_info_valid is set 699 700 701 Bits [31:0] of the PN number extracted from the IV field 702 703 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 704 is valid. 705 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], 706 pn1}. Only pn[47:0] is valid. 707 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 708 pn0}. Only pn[47:0] is valid. 709 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 710 pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 711 pn[127:0] are valid. 712 713 In case of ndp or phy_err, this field will never be set. 714 715 */ 716 717 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c 718 #define RX_MPDU_INFO_PN_31_0_LSB 0 719 #define RX_MPDU_INFO_PN_31_0_MSB 31 720 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 721 722 723 /* Description PN_63_32 724 725 Field only valid when Frame_encryption_info_valid is set 726 727 728 Bits [63:32] of the PN number. See description for pn_31_0. 729 730 731 In case of ndp or phy_err, this field will never be set. 732 733 */ 734 735 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 736 #define RX_MPDU_INFO_PN_63_32_LSB 0 737 #define RX_MPDU_INFO_PN_63_32_MSB 31 738 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 739 740 741 /* Description PN_95_64 742 743 Field only valid when Frame_encryption_info_valid is set 744 745 746 Bits [95:64] of the PN number. See description for pn_31_0. 747 748 749 In case of ndp or phy_err, this field will never be set. 750 751 */ 752 753 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 754 #define RX_MPDU_INFO_PN_95_64_LSB 0 755 #define RX_MPDU_INFO_PN_95_64_MSB 31 756 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 757 758 759 /* Description PN_127_96 760 761 Field only valid when Frame_encryption_info_valid is set 762 763 764 Bits [127:96] of the PN number. See description for pn_31_0. 765 766 767 In case of ndp or phy_err, this field will never be set. 768 769 */ 770 771 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 772 #define RX_MPDU_INFO_PN_127_96_LSB 0 773 #define RX_MPDU_INFO_PN_127_96_MSB 31 774 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 775 776 777 /* Description EPD_EN 778 779 Field only valid when AST_based_lookup_valid == 1. 780 781 782 In case of ndp or phy_err or AST_based_lookup_valid == 0, 783 this field will be set to 0 784 785 If set to one use EPD instead of LPD 786 787 In case of ndp or phy_err, this field will never be set. 788 789 <legal all> 790 */ 791 792 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c 793 #define RX_MPDU_INFO_EPD_EN_LSB 0 794 #define RX_MPDU_INFO_EPD_EN_MSB 0 795 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 796 797 798 /* Description ALL_FRAMES_SHALL_BE_ENCRYPTED 799 800 In case of ndp or phy_err or AST_based_lookup_valid == 0, 801 this field will be set to 0 802 803 When set, all frames (data only ?) shall be encrypted. If 804 not, RX CRYPTO shall set an error flag. 805 <legal all> 806 */ 807 808 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 809 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 810 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 811 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 812 813 814 /* Description ENCRYPT_TYPE 815 816 In case of ndp or phy_err or AST_based_lookup_valid == 0, 817 this field will be set to 0 818 819 Indicates type of decrypt cipher used (as defined in the 820 peer entry) 821 822 <enum 0 wep_40> WEP 40-bit 823 <enum 1 wep_104> WEP 104-bit 824 <enum 2 tkip_no_mic> TKIP without MIC 825 <enum 3 wep_128> WEP 128-bit 826 <enum 4 tkip_with_mic> TKIP with MIC 827 <enum 5 wapi> WAPI 828 <enum 6 aes_ccmp_128> AES CCMP 128 829 <enum 7 no_cipher> No crypto 830 <enum 8 aes_ccmp_256> AES CCMP 256 831 <enum 9 aes_gcmp_128> AES CCMP 128 832 <enum 10 aes_gcmp_256> AES CCMP 256 833 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 834 835 <enum 12 wep_varied_width> WEP encryption. As for WEP per 836 keyid the key bit width can vary, the key bit width for 837 this MPDU will be indicated in field wep_key_width_for_variable 838 key 839 <legal 0-12> 840 */ 841 842 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c 843 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 844 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 845 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 846 847 848 /* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY 849 850 Field only valid when key_type is set to wep_varied_width. 851 852 853 This field indicates the size of the wep key for this MPDU. 854 855 856 <enum 0 wep_varied_width_40> WEP 40-bit 857 <enum 1 wep_varied_width_104> WEP 104-bit 858 <enum 2 wep_varied_width_128> WEP 128-bit 859 860 <legal 0-2> 861 */ 862 863 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 864 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 865 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 866 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 867 868 869 /* Description MESH_STA 870 871 In case of ndp or phy_err or AST_based_lookup_valid == 0, 872 this field will be set to 0 873 874 When set, this is a Mesh (11s) STA. 875 876 The interpretation of the A-MSDU 'Length' field in the MPDU 877 (if any) is decided by the e-numerations below. 878 879 <enum 0 MESH_DISABLE> 880 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes 881 the length of Mesh Control. 882 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes 883 the length of Mesh Control. 884 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and 885 excludes the length of Mesh Control. This is 802.11s-compliant. 886 887 <legal all> 888 */ 889 890 #define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c 891 #define RX_MPDU_INFO_MESH_STA_LSB 8 892 #define RX_MPDU_INFO_MESH_STA_MSB 9 893 #define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 894 895 896 /* Description BSSID_HIT 897 898 In case of ndp or phy_err or AST_based_lookup_valid == 0, 899 this field will be set to 0 900 901 When set, the BSSID of the incoming frame matched one of 902 the 8 BSSID register values 903 904 <legal all> 905 */ 906 907 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c 908 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 909 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 910 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 911 912 913 /* Description BSSID_NUMBER 914 915 Field only valid when bssid_hit is set. 916 917 This number indicates which one out of the 8 BSSID register 918 values matched the incoming frame 919 <legal all> 920 */ 921 922 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c 923 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 924 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 925 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 926 927 928 /* Description TID 929 930 Field only valid when mpdu_qos_control_valid is set 931 932 The TID field in the QoS control field 933 <legal all> 934 */ 935 936 #define RX_MPDU_INFO_TID_OFFSET 0x0000001c 937 #define RX_MPDU_INFO_TID_LSB 15 938 #define RX_MPDU_INFO_TID_MSB 18 939 #define RX_MPDU_INFO_TID_MASK 0x00078000 940 941 942 /* Description RESERVED_7A 943 944 <legal 0> 945 */ 946 947 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c 948 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 949 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 950 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 951 952 953 /* Description PEER_META_DATA 954 955 In case of ndp or phy_err or AST_based_lookup_valid == 0, 956 this field will be set to 0 957 958 Meta data that SW has programmed in the Peer table entry 959 of the transmitting STA. 960 <legal all> 961 */ 962 963 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 964 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 965 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 966 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 967 968 969 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 970 971 Field indicates what the reason was that this MPDU frame 972 was allowed to come into the receive path by RXPCU 973 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 974 filter programming of rxpcu 975 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 976 regular frame filter and would have been dropped, were 977 it not for the frame fitting into the 'monitor_client' category. 978 979 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 980 regular frame filter and also did not pass the rxpcu_monitor_client 981 filter. It would have been dropped accept that it did pass 982 the 'monitor_other' category. 983 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 984 the normal frame filter programming of RXPCU but additionally 985 fit into the 'monitor_override_client' category. 986 987 Note: for ndp frame, if it was expected because the preceding 988 NDPA was filter_pass, the setting rxpcu_filter_pass will 989 be used. This setting will also be used for every ndp frame 990 in case Promiscuous mode is enabled. 991 992 In case promiscuous is not enabled, and an NDP is not preceded 993 by a NPDA filter pass frame, the only other setting that 994 could appear here for the NDP is rxpcu_monitor_other. 995 (rxpcu has a configuration bit specifically for this scenario) 996 997 998 Note: for 999 <legal 0-3> 1000 */ 1001 1002 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 1003 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1004 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 1005 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 1006 1007 1008 /* Description SW_FRAME_GROUP_ID 1009 1010 SW processes frames based on certain classifications. This 1011 field indicates to what sw classification this MPDU is 1012 mapped. 1013 The classification is given in priority order 1014 1015 <enum 0 sw_frame_group_NDP_frame> Note: The corresponding 1016 Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass 1017 or rxpcu_monitor_other 1018 1019 <enum 1 sw_frame_group_Multicast_data> 1020 <enum 2 sw_frame_group_Unicast_data> 1021 <enum 3 sw_frame_group_Null_data > This includes mpdus of 1022 type Data Null. 1023 Hamilton v1 included QoS Data Null as well here. 1024 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 1025 Null frames except in UL MU or TB PPDUs. 1026 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 1027 QoS Null frames in UL MU or TB PPDUs. 1028 1029 <enum 4 sw_frame_group_mgmt_0000 > 1030 <enum 5 sw_frame_group_mgmt_0001 > 1031 <enum 6 sw_frame_group_mgmt_0010 > 1032 <enum 7 sw_frame_group_mgmt_0011 > 1033 <enum 8 sw_frame_group_mgmt_0100 > 1034 <enum 9 sw_frame_group_mgmt_0101 > 1035 <enum 10 sw_frame_group_mgmt_0110 > 1036 <enum 11 sw_frame_group_mgmt_0111 > 1037 <enum 12 sw_frame_group_mgmt_1000 > 1038 <enum 13 sw_frame_group_mgmt_1001 > 1039 <enum 14 sw_frame_group_mgmt_1010 > 1040 <enum 15 sw_frame_group_mgmt_1011 > 1041 <enum 16 sw_frame_group_mgmt_1100 > 1042 <enum 17 sw_frame_group_mgmt_1101 > 1043 <enum 18 sw_frame_group_mgmt_1110 > 1044 <enum 19 sw_frame_group_mgmt_1111 > 1045 1046 <enum 20 sw_frame_group_ctrl_0000 > 1047 <enum 21 sw_frame_group_ctrl_0001 > 1048 <enum 22 sw_frame_group_ctrl_0010 > 1049 <enum 23 sw_frame_group_ctrl_0011 > 1050 <enum 24 sw_frame_group_ctrl_0100 > 1051 <enum 25 sw_frame_group_ctrl_0101 > 1052 <enum 26 sw_frame_group_ctrl_0110 > 1053 <enum 27 sw_frame_group_ctrl_0111 > 1054 <enum 28 sw_frame_group_ctrl_1000 > 1055 <enum 29 sw_frame_group_ctrl_1001 > 1056 <enum 30 sw_frame_group_ctrl_1010 > 1057 <enum 31 sw_frame_group_ctrl_1011 > 1058 <enum 32 sw_frame_group_ctrl_1100 > 1059 <enum 33 sw_frame_group_ctrl_1101 > 1060 <enum 34 sw_frame_group_ctrl_1110 > 1061 <enum 35 sw_frame_group_ctrl_1111 > 1062 1063 <enum 36 sw_frame_group_unsupported> This covers type 3 1064 and protocol version != 0 1065 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 1066 only be rxpcu_monitor_other 1067 1068 <enum 37 sw_frame_group_phy_error> PHY reported an error 1069 1070 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 1071 be rxpcu_filter_pass 1072 1073 <legal 0-39> 1074 */ 1075 1076 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 1077 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 1078 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 1079 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 1080 1081 1082 /* Description NDP_FRAME 1083 1084 When set, the received frame was an NDP frame, and thus 1085 there will be no MPDU data. 1086 TODO: Should this be extended to 2-bit e-num? 1087 <legal all> 1088 */ 1089 1090 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 1091 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 1092 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 1093 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 1094 1095 1096 /* Description PHY_ERR 1097 1098 When set, a PHY error was received before MAC received any 1099 data, and thus there will be no MPDU data. 1100 <legal all> 1101 */ 1102 1103 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 1104 #define RX_MPDU_INFO_PHY_ERR_LSB 10 1105 #define RX_MPDU_INFO_PHY_ERR_MSB 10 1106 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 1107 1108 1109 /* Description PHY_ERR_DURING_MPDU_HEADER 1110 1111 When set, a PHY error was received before MAC received the 1112 complete MPDU header which was needed for proper decoding 1113 1114 <legal all> 1115 */ 1116 1117 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 1118 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1119 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 1120 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1121 1122 1123 /* Description PROTOCOL_VERSION_ERR 1124 1125 Set when RXPCU detected a version error in the Frame control 1126 field 1127 <legal all> 1128 */ 1129 1130 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 1131 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 1132 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 1133 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 1134 1135 1136 /* Description AST_BASED_LOOKUP_VALID 1137 1138 When set, AST based lookup for this frame has found a valid 1139 result. 1140 1141 Note that for NDP frame this will never be set 1142 <legal all> 1143 */ 1144 1145 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 1146 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 1147 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 1148 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1149 1150 1151 /* Description RANGING 1152 1153 When set, a ranging NDPA or a ranging NDP was received. 1154 1155 This field is only for FW visibility. HW is not expected 1156 to take any action on this. 1157 <legal all> 1158 */ 1159 1160 #define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 1161 #define RX_MPDU_INFO_RANGING_LSB 14 1162 #define RX_MPDU_INFO_RANGING_MSB 14 1163 #define RX_MPDU_INFO_RANGING_MASK 0x00004000 1164 1165 1166 /* Description RESERVED_9A 1167 1168 <legal 0> 1169 */ 1170 1171 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 1172 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 1173 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 1174 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 1175 1176 1177 /* Description PHY_PPDU_ID 1178 1179 A ppdu counter value that PHY increments for every PPDU 1180 received. The counter value wraps around 1181 <legal all> 1182 */ 1183 1184 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 1185 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 1186 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 1187 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 1188 1189 1190 /* Description AST_INDEX 1191 1192 This field indicates the index of the AST entry corresponding 1193 to this MPDU. It is provided by the GSE module instantiated 1194 in RXPCU. 1195 A value of 0xFFFF indicates an invalid AST index, meaning 1196 that No AST entry was found or NO AST search was performed 1197 1198 1199 In case of ndp or phy_err, this field will be set to 0xFFFF 1200 1201 <legal all> 1202 */ 1203 1204 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 1205 #define RX_MPDU_INFO_AST_INDEX_LSB 0 1206 #define RX_MPDU_INFO_AST_INDEX_MSB 15 1207 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 1208 1209 1210 /* Description SW_PEER_ID 1211 1212 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1213 this field will be set to 0 1214 1215 This field indicates a unique peer identifier. It is set 1216 equal to field 'sw_peer_id' from the AST entry 1217 1218 <legal all> 1219 */ 1220 1221 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 1222 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 1223 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 1224 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 1225 1226 1227 /* Description MPDU_FRAME_CONTROL_VALID 1228 1229 When set, the field Mpdu_Frame_control_field has valid information 1230 1231 1232 In case of ndp or phy_err, this field will never be set. 1233 1234 <legal all> 1235 */ 1236 1237 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 1238 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 1239 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 1240 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1241 1242 1243 /* Description MPDU_DURATION_VALID 1244 1245 When set, the field Mpdu_duration_field has valid information 1246 1247 1248 In case of ndp or phy_err, this field will never be set. 1249 1250 <legal all> 1251 */ 1252 1253 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c 1254 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 1255 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 1256 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 1257 1258 1259 /* Description MAC_ADDR_AD1_VALID 1260 1261 When set, the fields mac_addr_ad1_..... have valid information 1262 1263 1264 In case of ndp or phy_err, this field will never be set. 1265 1266 <legal all> 1267 */ 1268 1269 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 1270 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 1271 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 1272 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 1273 1274 1275 /* Description MAC_ADDR_AD2_VALID 1276 1277 When set, the fields mac_addr_ad2_..... have valid information 1278 1279 1280 For MPDUs without Address 2, this field will not be set. 1281 1282 1283 In case of ndp or phy_err, this field will never be set. 1284 1285 <legal all> 1286 */ 1287 1288 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 1289 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 1290 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 1291 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 1292 1293 1294 /* Description MAC_ADDR_AD3_VALID 1295 1296 When set, the fields mac_addr_ad3_..... have valid information 1297 1298 1299 For MPDUs without Address 3, this field will not be set. 1300 1301 1302 In case of ndp or phy_err, this field will never be set. 1303 1304 <legal all> 1305 */ 1306 1307 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 1308 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 1309 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 1310 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 1311 1312 1313 /* Description MAC_ADDR_AD4_VALID 1314 1315 When set, the fields mac_addr_ad4_..... have valid information 1316 1317 1318 For MPDUs without Address 4, this field will not be set. 1319 1320 1321 In case of ndp or phy_err, this field will never be set. 1322 1323 <legal all> 1324 */ 1325 1326 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 1327 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 1328 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 1329 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 1330 1331 1332 /* Description MPDU_SEQUENCE_CONTROL_VALID 1333 1334 When set, the fields mpdu_sequence_control_field and mpdu_sequence_number 1335 have valid information as well as field 1336 1337 For MPDUs without a sequence control field, this field will 1338 not be set. 1339 1340 In case of ndp or phy_err, this field will never be set. 1341 1342 <legal all> 1343 */ 1344 1345 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 1346 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1347 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 1348 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1349 1350 1351 /* Description MPDU_QOS_CONTROL_VALID 1352 1353 When set, the field mpdu_qos_control_field has valid information 1354 1355 1356 For MPDUs without a QoS control field, this field will not 1357 be set. 1358 1359 In case of ndp or phy_err, this field will never be set. 1360 1361 <legal all> 1362 */ 1363 1364 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 1365 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 1366 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 1367 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1368 1369 1370 /* Description MPDU_HT_CONTROL_VALID 1371 1372 When set, the field mpdu_HT_control_field has valid information 1373 1374 1375 For MPDUs without a HT control field, this field will not 1376 be set. 1377 1378 In case of ndp or phy_err, this field will never be set. 1379 1380 <legal all> 1381 */ 1382 1383 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 1384 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 1385 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 1386 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1387 1388 1389 /* Description FRAME_ENCRYPTION_INFO_VALID 1390 1391 When set, the encryption related info fields, like IV and 1392 PN are valid 1393 1394 For MPDUs that are not encrypted, this will not be set. 1395 1396 In case of ndp or phy_err, this field will never be set. 1397 1398 <legal all> 1399 */ 1400 1401 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 1402 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1403 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 1404 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1405 1406 1407 /* Description MPDU_FRAGMENT_NUMBER 1408 1409 Field only valid when Mpdu_sequence_control_valid is set 1410 AND Fragment_flag is set 1411 1412 The fragment number from the 802.11 header 1413 1414 <legal all> 1415 */ 1416 1417 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 1418 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 1419 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 1420 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 1421 1422 1423 /* Description MORE_FRAGMENT_FLAG 1424 1425 The More Fragment bit setting from the MPDU header of the 1426 received frame 1427 1428 <legal all> 1429 */ 1430 1431 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 1432 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 1433 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 1434 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 1435 1436 1437 /* Description RESERVED_11A 1438 1439 <legal 0> 1440 */ 1441 1442 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c 1443 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 1444 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 1445 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 1446 1447 1448 /* Description FR_DS 1449 1450 Field only valid when Mpdu_frame_control_valid is set 1451 1452 Set if the from DS bit is set in the frame control. 1453 <legal all> 1454 */ 1455 1456 #define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c 1457 #define RX_MPDU_INFO_FR_DS_LSB 16 1458 #define RX_MPDU_INFO_FR_DS_MSB 16 1459 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 1460 1461 1462 /* Description TO_DS 1463 1464 Field only valid when Mpdu_frame_control_valid is set 1465 1466 Set if the to DS bit is set in the frame control. 1467 <legal all> 1468 */ 1469 1470 #define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c 1471 #define RX_MPDU_INFO_TO_DS_LSB 17 1472 #define RX_MPDU_INFO_TO_DS_MSB 17 1473 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 1474 1475 1476 /* Description ENCRYPTED 1477 1478 Field only valid when Mpdu_frame_control_valid is set. 1479 1480 Protected bit from the frame control. 1481 <legal all> 1482 */ 1483 1484 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c 1485 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 1486 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 1487 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 1488 1489 1490 /* Description MPDU_RETRY 1491 1492 Field only valid when Mpdu_frame_control_valid is set. 1493 1494 Retry bit from the frame control. Only valid when first_msdu 1495 is set. 1496 <legal all> 1497 */ 1498 1499 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c 1500 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 1501 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 1502 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 1503 1504 1505 /* Description MPDU_SEQUENCE_NUMBER 1506 1507 Field only valid when Mpdu_sequence_control_valid is set. 1508 1509 1510 The sequence number from the 802.11 header. 1511 <legal all> 1512 */ 1513 1514 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 1515 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 1516 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 1517 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1518 1519 1520 /* Description KEY_ID_OCTET 1521 1522 Field only valid when Frame_encryption_info_valid is set 1523 1524 1525 The key ID octet from the IV. 1526 1527 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1528 this field will be set to 0 1529 <legal all> 1530 */ 1531 1532 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 1533 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 1534 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 1535 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 1536 1537 1538 /* Description NEW_PEER_ENTRY 1539 1540 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1541 this field will be set to 0 1542 1543 Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 1544 doesn't follow so RX DECRYPTION module either uses old 1545 peer entry or not decrypt. 1546 <legal all> 1547 */ 1548 1549 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 1550 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 1551 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 1552 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 1553 1554 1555 /* Description DECRYPT_NEEDED 1556 1557 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1558 this field will be set to 0 1559 1560 Set if decryption is needed. 1561 1562 Note: 1563 When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', 1564 RXPCU will also ensure that this bit is NOT set 1565 CRYPTO for that reason only needs to evaluate this bit and 1566 non of the other ones. 1567 <legal all> 1568 */ 1569 1570 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 1571 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 1572 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 1573 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 1574 1575 1576 /* Description DECAP_TYPE 1577 1578 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1579 this field will be set to 0 1580 1581 Used by the OLE during decapsulation. 1582 1583 Indicates the decapsulation that HW will perform: 1584 1585 <enum 0 RAW> No encapsulation 1586 <enum 1 Native_WiFi> 1587 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1588 1589 <enum 3 802_3> Indicate Ethernet 1590 1591 <legal all> 1592 */ 1593 1594 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 1595 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 1596 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 1597 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 1598 1599 1600 /* Description RX_INSERT_VLAN_C_TAG_PADDING 1601 1602 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1603 this field will be set to 0 1604 1605 Insert 4 byte of all zeros as VLAN tag if the rx payload 1606 does not have VLAN. Used during decapsulation. 1607 <legal all> 1608 */ 1609 1610 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 1611 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1612 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 1613 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 1614 1615 1616 /* Description RX_INSERT_VLAN_S_TAG_PADDING 1617 1618 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1619 this field will be set to 0 1620 1621 Insert 4 byte of all zeros as double VLAN tag if the rx 1622 payload does not have VLAN. Used during 1623 <legal all> 1624 */ 1625 1626 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 1627 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1628 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 1629 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 1630 1631 1632 /* Description STRIP_VLAN_C_TAG_DECAP 1633 1634 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1635 this field will be set to 0 1636 1637 Strip the VLAN during decapsulation. Used by the OLE. 1638 <legal all> 1639 */ 1640 1641 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 1642 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 1643 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 1644 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 1645 1646 1647 /* Description STRIP_VLAN_S_TAG_DECAP 1648 1649 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1650 this field will be set to 0 1651 1652 Strip the double VLAN during decapsulation. Used by the 1653 OLE. 1654 <legal all> 1655 */ 1656 1657 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 1658 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 1659 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 1660 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 1661 1662 1663 /* Description PRE_DELIM_COUNT 1664 1665 The number of delimiters before this MPDU. 1666 1667 Note that this number is cleared at PPDU start. 1668 1669 If this MPDU is the first received MPDU in the PPDU and 1670 this MPDU gets filtered-in, this field will indicate the 1671 number of delimiters located after the last MPDU in the 1672 previous PPDU. 1673 1674 If this MPDU is located after the first received MPDU in 1675 an PPDU, this field will indicate the number of delimiters 1676 located between the previous MPDU and this MPDU. 1677 1678 In case of ndp or phy_err, this field will indicate the 1679 number of delimiters located after the last MPDU in the 1680 previous PPDU. 1681 <legal all> 1682 */ 1683 1684 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 1685 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 1686 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 1687 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 1688 1689 1690 /* Description AMPDU_FLAG 1691 1692 When set, received frame was part of an A-MPDU. 1693 1694 In case of ndp or phy_err, this field will never be set. 1695 1696 <legal all> 1697 */ 1698 1699 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 1700 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 1701 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 1702 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 1703 1704 1705 /* Description BAR_FRAME 1706 1707 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1708 this field will be set to 0 1709 1710 When set, received frame is a BAR frame 1711 <legal all> 1712 */ 1713 1714 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 1715 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 1716 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 1717 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 1718 1719 1720 /* Description RAW_MPDU 1721 1722 Consumer: SW 1723 Producer: RXOLE 1724 1725 RXPCU sets this field to 0 and RXOLE overwrites it. 1726 1727 Set to 1 by RXOLE when it has not performed any 802.11 to 1728 Ethernet/Natvie WiFi header conversion on this MPDU. 1729 <legal all> 1730 */ 1731 1732 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 1733 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 1734 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 1735 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 1736 1737 1738 /* Description RESERVED_12 1739 1740 <legal 0> 1741 */ 1742 1743 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 1744 #define RX_MPDU_INFO_RESERVED_12_LSB 31 1745 #define RX_MPDU_INFO_RESERVED_12_MSB 31 1746 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 1747 1748 1749 /* Description MPDU_LENGTH 1750 1751 In case of ndp or phy_err this field will be set to 0 1752 1753 MPDU length before decapsulation. 1754 <legal all> 1755 */ 1756 1757 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 1758 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 1759 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 1760 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 1761 1762 1763 /* Description FIRST_MPDU 1764 1765 See definition in RX attention descriptor 1766 1767 In case of ndp or phy_err, this field will be set. Note 1768 however that there will not actually be any data contents 1769 in the MPDU. 1770 <legal all> 1771 */ 1772 1773 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 1774 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 1775 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 1776 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 1777 1778 1779 /* Description MCAST_BCAST 1780 1781 In case of ndp or phy_err or Phy_err_during_mpdu_header 1782 this field will be set to 0 1783 1784 See definition in RX attention descriptor 1785 <legal all> 1786 */ 1787 1788 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 1789 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 1790 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 1791 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 1792 1793 1794 /* Description AST_INDEX_NOT_FOUND 1795 1796 In case of ndp or phy_err or Phy_err_during_mpdu_header 1797 this field will be set to 0 1798 1799 See definition in RX attention descriptor 1800 <legal all> 1801 */ 1802 1803 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 1804 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 1805 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 1806 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 1807 1808 1809 /* Description AST_INDEX_TIMEOUT 1810 1811 In case of ndp or phy_err or Phy_err_during_mpdu_header 1812 this field will be set to 0 1813 1814 See definition in RX attention descriptor 1815 <legal all> 1816 */ 1817 1818 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 1819 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 1820 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 1821 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 1822 1823 1824 /* Description POWER_MGMT 1825 1826 In case of ndp or phy_err or Phy_err_during_mpdu_header 1827 this field will be set to 0 1828 1829 See definition in RX attention descriptor 1830 <legal all> 1831 */ 1832 1833 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 1834 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 1835 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 1836 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 1837 1838 1839 /* Description NON_QOS 1840 1841 In case of ndp or phy_err or Phy_err_during_mpdu_header 1842 this field will be set to 1 1843 1844 See definition in RX attention descriptor 1845 <legal all> 1846 */ 1847 1848 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 1849 #define RX_MPDU_INFO_NON_QOS_LSB 19 1850 #define RX_MPDU_INFO_NON_QOS_MSB 19 1851 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 1852 1853 1854 /* Description NULL_DATA 1855 1856 In case of ndp or phy_err or Phy_err_during_mpdu_header 1857 this field will be set to 0 1858 1859 See definition in RX attention descriptor 1860 <legal all> 1861 */ 1862 1863 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 1864 #define RX_MPDU_INFO_NULL_DATA_LSB 20 1865 #define RX_MPDU_INFO_NULL_DATA_MSB 20 1866 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 1867 1868 1869 /* Description MGMT_TYPE 1870 1871 In case of ndp or phy_err or Phy_err_during_mpdu_header 1872 this field will be set to 0 1873 1874 See definition in RX attention descriptor 1875 <legal all> 1876 */ 1877 1878 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 1879 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 1880 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 1881 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 1882 1883 1884 /* Description CTRL_TYPE 1885 1886 In case of ndp or phy_err or Phy_err_during_mpdu_header 1887 this field will be set to 0 1888 1889 See definition in RX attention descriptor 1890 <legal all> 1891 */ 1892 1893 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 1894 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 1895 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 1896 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 1897 1898 1899 /* Description MORE_DATA 1900 1901 In case of ndp or phy_err or Phy_err_during_mpdu_header 1902 this field will be set to 0 1903 1904 See definition in RX attention descriptor 1905 <legal all> 1906 */ 1907 1908 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 1909 #define RX_MPDU_INFO_MORE_DATA_LSB 23 1910 #define RX_MPDU_INFO_MORE_DATA_MSB 23 1911 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 1912 1913 1914 /* Description EOSP 1915 1916 In case of ndp or phy_err or Phy_err_during_mpdu_header 1917 this field will be set to 0 1918 1919 See definition in RX attention descriptor 1920 <legal all> 1921 */ 1922 1923 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 1924 #define RX_MPDU_INFO_EOSP_LSB 24 1925 #define RX_MPDU_INFO_EOSP_MSB 24 1926 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 1927 1928 1929 /* Description FRAGMENT_FLAG 1930 1931 In case of ndp or phy_err or Phy_err_during_mpdu_header 1932 this field will be set to 0 1933 1934 See definition in RX attention descriptor 1935 <legal all> 1936 */ 1937 1938 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 1939 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 1940 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 1941 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 1942 1943 1944 /* Description ORDER 1945 1946 In case of ndp or phy_err or Phy_err_during_mpdu_header 1947 this field will be set to 0 1948 1949 See definition in RX attention descriptor 1950 1951 <legal all> 1952 */ 1953 1954 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 1955 #define RX_MPDU_INFO_ORDER_LSB 26 1956 #define RX_MPDU_INFO_ORDER_MSB 26 1957 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 1958 1959 1960 /* Description U_APSD_TRIGGER 1961 1962 In case of ndp or phy_err or Phy_err_during_mpdu_header 1963 this field will be set to 0 1964 1965 See definition in RX attention descriptor 1966 <legal all> 1967 */ 1968 1969 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 1970 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 1971 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 1972 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 1973 1974 1975 /* Description ENCRYPT_REQUIRED 1976 1977 In case of ndp or phy_err or Phy_err_during_mpdu_header 1978 this field will be set to 0 1979 1980 See definition in RX attention descriptor 1981 <legal all> 1982 */ 1983 1984 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 1985 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 1986 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 1987 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 1988 1989 1990 /* Description DIRECTED 1991 1992 In case of ndp or phy_err or Phy_err_during_mpdu_header 1993 this field will be set to 0 1994 1995 See definition in RX attention descriptor 1996 <legal all> 1997 */ 1998 1999 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 2000 #define RX_MPDU_INFO_DIRECTED_LSB 29 2001 #define RX_MPDU_INFO_DIRECTED_MSB 29 2002 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 2003 2004 2005 /* Description AMSDU_PRESENT 2006 2007 Field only valid when Mpdu_qos_control_valid is set 2008 2009 The 'amsdu_present' bit within the QoS control field of 2010 the MPDU 2011 <legal all> 2012 */ 2013 2014 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 2015 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 2016 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 2017 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 2018 2019 2020 /* Description RESERVED_13 2021 2022 Field only valid when Mpdu_qos_control_valid is set 2023 2024 This indicates whether the 'Ack policy' field within the 2025 QoS control field of the MPDU indicates 'no-Ack.' 2026 <legal all> 2027 */ 2028 2029 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 2030 #define RX_MPDU_INFO_RESERVED_13_LSB 31 2031 #define RX_MPDU_INFO_RESERVED_13_MSB 31 2032 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 2033 2034 2035 /* Description MPDU_FRAME_CONTROL_FIELD 2036 2037 Field only valid when Mpdu_frame_control_valid is set 2038 2039 The frame control field of this received MPDU. 2040 2041 Field only valid when Ndp_frame and phy_err are NOT set 2042 2043 Bytes 0 + 1 of the received MPDU 2044 <legal all> 2045 */ 2046 2047 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2048 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 2049 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 2050 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2051 2052 2053 /* Description MPDU_DURATION_FIELD 2054 2055 Field only valid when Mpdu_duration_valid is set 2056 2057 The duration field of this received MPDU. 2058 <legal all> 2059 */ 2060 2061 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 2062 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 2063 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 2064 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 2065 2066 2067 /* Description MAC_ADDR_AD1_31_0 2068 2069 Field only valid when mac_addr_ad1_valid is set 2070 2071 The Least Significant 4 bytes of the Received Frames MAC 2072 Address AD1 2073 <legal all> 2074 */ 2075 2076 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2077 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 2078 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 2079 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2080 2081 2082 /* Description MAC_ADDR_AD1_47_32 2083 2084 Field only valid when mac_addr_ad1_valid is set 2085 2086 The 2 most significant bytes of the Received Frames MAC 2087 Address AD1 2088 <legal all> 2089 */ 2090 2091 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2092 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 2093 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 2094 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2095 2096 2097 /* Description MAC_ADDR_AD2_15_0 2098 2099 Field only valid when mac_addr_ad2_valid is set 2100 2101 The Least Significant 2 bytes of the Received Frames MAC 2102 Address AD2 2103 <legal all> 2104 */ 2105 2106 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2107 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 2108 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 2109 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2110 2111 2112 /* Description MAC_ADDR_AD2_47_16 2113 2114 Field only valid when mac_addr_ad2_valid is set 2115 2116 The 4 most significant bytes of the Received Frames MAC 2117 Address AD2 2118 <legal all> 2119 */ 2120 2121 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2122 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 2123 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 2124 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2125 2126 2127 /* Description MAC_ADDR_AD3_31_0 2128 2129 Field only valid when mac_addr_ad3_valid is set 2130 2131 The Least Significant 4 bytes of the Received Frames MAC 2132 Address AD3 2133 <legal all> 2134 */ 2135 2136 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2137 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 2138 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 2139 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2140 2141 2142 /* Description MAC_ADDR_AD3_47_32 2143 2144 Field only valid when mac_addr_ad3_valid is set 2145 2146 The 2 most significant bytes of the Received Frames MAC 2147 Address AD3 2148 <legal all> 2149 */ 2150 2151 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2152 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 2153 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 2154 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2155 2156 2157 /* Description MPDU_SEQUENCE_CONTROL_FIELD 2158 2159 Field only valid when mpdu_sequence_control_valid is set 2160 2161 2162 The sequence control field of the MPDU 2163 <legal all> 2164 */ 2165 2166 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2167 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2168 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 2169 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2170 2171 2172 /* Description MAC_ADDR_AD4_31_0 2173 2174 Field only valid when mac_addr_ad4_valid is set 2175 2176 The Least Significant 4 bytes of the Received Frames MAC 2177 Address AD4 2178 <legal all> 2179 */ 2180 2181 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 2182 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 2183 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 2184 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 2185 2186 2187 /* Description MAC_ADDR_AD4_47_32 2188 2189 Field only valid when mac_addr_ad4_valid is set 2190 2191 The 2 most significant bytes of the Received Frames MAC 2192 Address AD4 2193 <legal all> 2194 */ 2195 2196 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 2197 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 2198 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 2199 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 2200 2201 2202 /* Description MPDU_QOS_CONTROL_FIELD 2203 2204 Field only valid when mpdu_qos_control_valid is set 2205 2206 The sequence control field of the MPDU 2207 <legal all> 2208 */ 2209 2210 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 2211 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 2212 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 2213 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 2214 2215 2216 /* Description MPDU_HT_CONTROL_FIELD 2217 2218 Field only valid when mpdu_qos_control_valid is set 2219 2220 The HT control field of the MPDU 2221 <legal all> 2222 */ 2223 2224 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 2225 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 2226 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 2227 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 2228 2229 2230 /* Description VDEV_ID 2231 2232 Consumer: RXOLE 2233 Producer: FW 2234 2235 Virtual device associated with this peer 2236 2237 RXOLE uses this to determine intra-BSS routing. 2238 2239 <legal all> 2240 */ 2241 2242 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 2243 #define RX_MPDU_INFO_VDEV_ID_LSB 0 2244 #define RX_MPDU_INFO_VDEV_ID_MSB 7 2245 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 2246 2247 2248 /* Description SERVICE_CODE 2249 2250 Opaque service code between PPE and Wi-Fi 2251 2252 This field gets passed on by REO to PPE in the EDMA descriptor 2253 ('REO_TO_PPE_RING'). 2254 2255 <legal all> 2256 */ 2257 2258 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 2259 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 2260 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 2261 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 2262 2263 2264 /* Description PRIORITY_VALID 2265 2266 This field gets passed on by REO to PPE in the EDMA descriptor 2267 ('REO_TO_PPE_RING'). 2268 2269 <legal all> 2270 */ 2271 2272 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 2273 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 2274 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 2275 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 2276 2277 2278 /* Description SRC_INFO 2279 2280 Source (virtual) device/interface info. associated with 2281 this peer 2282 2283 This field gets passed on by REO to PPE in the EDMA descriptor 2284 ('REO_TO_PPE_RING'). 2285 2286 <legal all> 2287 */ 2288 2289 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 2290 #define RX_MPDU_INFO_SRC_INFO_LSB 18 2291 #define RX_MPDU_INFO_SRC_INFO_MSB 29 2292 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 2293 2294 2295 /* Description RESERVED_23A 2296 2297 <legal 0> 2298 */ 2299 2300 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 2301 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 2302 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 2303 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 2304 2305 2306 /* Description MULTI_LINK_ADDR_AD1_AD2_VALID 2307 2308 If set, Rx OLE shall convert Address1 and Address2 of received 2309 data frames to multi-link addresses during decapsulation 2310 to Ethernet or Native WiFi 2311 <legal all> 2312 */ 2313 2314 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c 2315 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 2316 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 2317 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 2318 2319 2320 /* Description MULTI_LINK_ADDR_AD1_31_0 2321 2322 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2323 2324 2325 Multi-link receiver address (address1), bits [31:0] 2326 */ 2327 2328 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 2329 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 2330 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 2331 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff 2332 2333 2334 /* Description MULTI_LINK_ADDR_AD1_47_32 2335 2336 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2337 2338 2339 Multi-link receiver address (address1), bits [47:32] 2340 */ 2341 2342 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 2343 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 2344 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 2345 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff 2346 2347 2348 /* Description MULTI_LINK_ADDR_AD2_15_0 2349 2350 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2351 2352 2353 Multi-link transmitter address (address2), bits [15:0] 2354 */ 2355 2356 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 2357 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 2358 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 2359 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 2360 2361 2362 /* Description MULTI_LINK_ADDR_AD2_47_16 2363 2364 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2365 2366 2367 Multi-link transmitter address (address2), bits [47:16] 2368 */ 2369 2370 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 2371 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 2372 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 2373 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff 2374 2375 2376 /* Description AUTHORIZED_TO_SEND_WDS 2377 2378 If not set, RXDMA shall perform error-routing for WDS packets 2379 as the sender is not authorized and might misuse WDS frame 2380 format to inject packets with arbitrary DA/SA. 2381 <legal all> 2382 */ 2383 2384 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c 2385 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 2386 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 2387 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 2388 2389 2390 /* Description RESERVED_27A 2391 2392 <legal 0> 2393 */ 2394 2395 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 2396 #define RX_MPDU_INFO_RESERVED_27A_LSB 1 2397 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 2398 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe 2399 2400 2401 /* Description RESERVED_28A 2402 2403 <legal 0> 2404 */ 2405 2406 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 2407 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 2408 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 2409 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 2410 2411 2412 /* Description RESERVED_29A 2413 2414 <legal 0> 2415 */ 2416 2417 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 2418 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 2419 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 2420 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 2421 2422 2423 2424 #endif // RX_MPDU_INFO 2425