1  
2  /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for any
5   * purpose with or without fee is hereby granted, provided that the above
6   * copyright notice and this permission notice appear in all copies.
7   *
8   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9   * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10   * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11   * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12   * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13   * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15   */
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  #ifndef _RX_MPDU_DESC_INFO_H_
27  #define _RX_MPDU_DESC_INFO_H_
28  #if !defined(__ASSEMBLER__)
29  #endif
30  
31  #define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
32  
33  
34  struct rx_mpdu_desc_info {
35  #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36               uint32_t msdu_count                                              :  8, // [7:0]
37                        fragment_flag                                           :  1, // [8:8]
38                        mpdu_retry_bit                                          :  1, // [9:9]
39                        ampdu_flag                                              :  1, // [10:10]
40                        bar_frame                                               :  1, // [11:11]
41                        pn_fields_contain_valid_info                            :  1, // [12:12]
42                        raw_mpdu                                                :  1, // [13:13]
43                        more_fragment_flag                                      :  1, // [14:14]
44                        src_info                                                : 12, // [26:15]
45                        mpdu_qos_control_valid                                  :  1, // [27:27]
46                        tid                                                     :  4; // [31:28]
47               uint32_t peer_meta_data                                          : 32; // [31:0]
48  #else
49               uint32_t tid                                                     :  4, // [31:28]
50                        mpdu_qos_control_valid                                  :  1, // [27:27]
51                        src_info                                                : 12, // [26:15]
52                        more_fragment_flag                                      :  1, // [14:14]
53                        raw_mpdu                                                :  1, // [13:13]
54                        pn_fields_contain_valid_info                            :  1, // [12:12]
55                        bar_frame                                               :  1, // [11:11]
56                        ampdu_flag                                              :  1, // [10:10]
57                        mpdu_retry_bit                                          :  1, // [9:9]
58                        fragment_flag                                           :  1, // [8:8]
59                        msdu_count                                              :  8; // [7:0]
60               uint32_t peer_meta_data                                          : 32; // [31:0]
61  #endif
62  };
63  
64  
65  /* Description		MSDU_COUNT
66  
67  			Consumer: REO/SW/FW
68  			Producer: RXDMA
69  
70  			The number of MSDUs within the MPDU
71  			<legal all>
72  */
73  
74  #define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET                                         0x00000000
75  #define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB                                            0
76  #define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB                                            7
77  #define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK                                           0x000000ff
78  
79  
80  /* Description		FRAGMENT_FLAG
81  
82  			Consumer: REO/SW/FW
83  			Producer: RXDMA
84  
85  			When set, this MPDU is a fragment and REO should forward
86  			 this fragment MPDU to the REO destination ring without
87  			any reorder checks, pn checks or bitmap update. This implies
88  			 that REO is forwarding the pointer to the MSDU link descriptor.
89  			The destination ring is coming from a programmable register
90  			 setting in REO
91  
92  			<legal all>
93  */
94  
95  #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET                                      0x00000000
96  #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB                                         8
97  #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB                                         8
98  #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK                                        0x00000100
99  
100  
101  /* Description		MPDU_RETRY_BIT
102  
103  			Consumer: REO/SW/FW
104  			Producer: RXDMA
105  
106  			The retry bit setting from the MPDU header of the received
107  			 frame
108  			<legal all>
109  */
110  
111  #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET                                     0x00000000
112  #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB                                        9
113  #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB                                        9
114  #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK                                       0x00000200
115  
116  
117  /* Description		AMPDU_FLAG
118  
119  			Consumer: REO/SW/FW
120  			Producer: RXDMA
121  
122  			When set, the MPDU was received as part of an A-MPDU.
123  			<legal all>
124  */
125  
126  #define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET                                         0x00000000
127  #define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB                                            10
128  #define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB                                            10
129  #define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK                                           0x00000400
130  
131  
132  /* Description		BAR_FRAME
133  
134  			Consumer: REO/SW/FW
135  			Producer: RXDMA
136  
137  			When set, the received frame is a BAR frame. After processing,
138  			this frame shall be pushed to SW or deleted.
139  			<legal all>
140  */
141  
142  #define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET                                          0x00000000
143  #define RX_MPDU_DESC_INFO_BAR_FRAME_LSB                                             11
144  #define RX_MPDU_DESC_INFO_BAR_FRAME_MSB                                             11
145  #define RX_MPDU_DESC_INFO_BAR_FRAME_MASK                                            0x00000800
146  
147  
148  /* Description		PN_FIELDS_CONTAIN_VALID_INFO
149  
150  			Consumer: REO/SW/FW
151  			Producer: RXDMA
152  
153  			Copied here by RXDMA from RX_MPDU_END
154  			When not set, REO will Not perform a PN sequence number
155  			check
156  */
157  
158  #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                       0x00000000
159  #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB                          12
160  #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB                          12
161  #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK                         0x00001000
162  
163  
164  /* Description		RAW_MPDU
165  
166  			Field only valid when first_msdu_in_mpdu_flag is set.
167  
168  			When set, the contents in the MSDU buffer contains a 'RAW'
169  			MPDU. This 'RAW' MPDU might be spread out over multiple
170  			MSDU buffers.
171  			<legal all>
172  */
173  
174  #define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET                                           0x00000000
175  #define RX_MPDU_DESC_INFO_RAW_MPDU_LSB                                              13
176  #define RX_MPDU_DESC_INFO_RAW_MPDU_MSB                                              13
177  #define RX_MPDU_DESC_INFO_RAW_MPDU_MASK                                             0x00002000
178  
179  
180  /* Description		MORE_FRAGMENT_FLAG
181  
182  			The More Fragment bit setting from the MPDU header of the
183  			 received frame
184  
185  			<legal all>
186  */
187  
188  #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET                                 0x00000000
189  #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB                                    14
190  #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB                                    14
191  #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK                                   0x00004000
192  
193  
194  /* Description		SRC_INFO
195  
196  			Source (virtual) device/interface info. associated with
197  			this peer
198  
199  			This field gets passed on by REO to PPE in the EDMA descriptor
200  			 ('REO_TO_PPE_RING').
201  
202  			Hamilton v1 used this for 'vdev_id' instead.
203  			<legal all>
204  */
205  
206  #define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET                                           0x00000000
207  #define RX_MPDU_DESC_INFO_SRC_INFO_LSB                                              15
208  #define RX_MPDU_DESC_INFO_SRC_INFO_MSB                                              26
209  #define RX_MPDU_DESC_INFO_SRC_INFO_MASK                                             0x07ff8000
210  
211  
212  /* Description		MPDU_QOS_CONTROL_VALID
213  
214  			When set, the MPDU has a QoS control field.
215  
216  			In case of ndp or phy_err, this field will never be set.
217  
218  			<legal all>
219  */
220  
221  #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                             0x00000000
222  #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB                                27
223  #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB                                27
224  #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK                               0x08000000
225  
226  
227  /* Description		TID
228  
229  			Field only valid when mpdu_qos_control_valid is set
230  
231  			The TID field in the QoS control field
232  			<legal all>
233  */
234  
235  #define RX_MPDU_DESC_INFO_TID_OFFSET                                                0x00000000
236  #define RX_MPDU_DESC_INFO_TID_LSB                                                   28
237  #define RX_MPDU_DESC_INFO_TID_MSB                                                   31
238  #define RX_MPDU_DESC_INFO_TID_MASK                                                  0xf0000000
239  
240  
241  /* Description		PEER_META_DATA
242  
243  			Meta data that SW has programmed in the Peer table entry
244  			 of the transmitting STA.
245  			<legal all>
246  */
247  
248  #define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET                                     0x00000004
249  #define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB                                        0
250  #define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB                                        31
251  #define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK                                       0xffffffff
252  
253  
254  
255  #endif   // RX_MPDU_DESC_INFO
256