1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_UNBLOCK_CACHE_STATUS_H_ 27 #define _REO_UNBLOCK_CACHE_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 35 36 37 struct reo_unblock_cache_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t error_detected : 1, // [0:0] 41 unblock_type : 1, // [1:1] 42 reserved_2a : 30; // [31:2] 43 uint32_t reserved_3a : 32; // [31:0] 44 uint32_t reserved_4a : 32; // [31:0] 45 uint32_t reserved_5a : 32; // [31:0] 46 uint32_t reserved_6a : 32; // [31:0] 47 uint32_t reserved_7a : 32; // [31:0] 48 uint32_t reserved_8a : 32; // [31:0] 49 uint32_t reserved_9a : 32; // [31:0] 50 uint32_t reserved_10a : 32; // [31:0] 51 uint32_t reserved_11a : 32; // [31:0] 52 uint32_t reserved_12a : 32; // [31:0] 53 uint32_t reserved_13a : 32; // [31:0] 54 uint32_t reserved_14a : 32; // [31:0] 55 uint32_t reserved_15a : 32; // [31:0] 56 uint32_t reserved_16a : 32; // [31:0] 57 uint32_t reserved_17a : 32; // [31:0] 58 uint32_t reserved_18a : 32; // [31:0] 59 uint32_t reserved_19a : 32; // [31:0] 60 uint32_t reserved_20a : 32; // [31:0] 61 uint32_t reserved_21a : 32; // [31:0] 62 uint32_t reserved_22a : 32; // [31:0] 63 uint32_t reserved_23a : 32; // [31:0] 64 uint32_t reserved_24a : 32; // [31:0] 65 uint32_t reserved_25a : 28, // [27:0] 66 looping_count : 4; // [31:28] 67 #else 68 struct uniform_reo_status_header status_header; 69 uint32_t reserved_2a : 30, // [31:2] 70 unblock_type : 1, // [1:1] 71 error_detected : 1; // [0:0] 72 uint32_t reserved_3a : 32; // [31:0] 73 uint32_t reserved_4a : 32; // [31:0] 74 uint32_t reserved_5a : 32; // [31:0] 75 uint32_t reserved_6a : 32; // [31:0] 76 uint32_t reserved_7a : 32; // [31:0] 77 uint32_t reserved_8a : 32; // [31:0] 78 uint32_t reserved_9a : 32; // [31:0] 79 uint32_t reserved_10a : 32; // [31:0] 80 uint32_t reserved_11a : 32; // [31:0] 81 uint32_t reserved_12a : 32; // [31:0] 82 uint32_t reserved_13a : 32; // [31:0] 83 uint32_t reserved_14a : 32; // [31:0] 84 uint32_t reserved_15a : 32; // [31:0] 85 uint32_t reserved_16a : 32; // [31:0] 86 uint32_t reserved_17a : 32; // [31:0] 87 uint32_t reserved_18a : 32; // [31:0] 88 uint32_t reserved_19a : 32; // [31:0] 89 uint32_t reserved_20a : 32; // [31:0] 90 uint32_t reserved_21a : 32; // [31:0] 91 uint32_t reserved_22a : 32; // [31:0] 92 uint32_t reserved_23a : 32; // [31:0] 93 uint32_t reserved_24a : 32; // [31:0] 94 uint32_t looping_count : 4, // [31:28] 95 reserved_25a : 28; // [27:0] 96 #endif 97 }; 98 99 100 /* Description STATUS_HEADER 101 102 Consumer: SW 103 Producer: REO 104 105 Details that can link this status with the original command. 106 It also contains info on how long REO took to execute this 107 command. 108 */ 109 110 111 /* Description REO_STATUS_NUMBER 112 113 Consumer: SW , DEBUG 114 Producer: REO 115 116 The value in this field is equal to value of the 'REO_CMD_Number' 117 field the REO command 118 119 This field helps to correlate the statuses with the REO 120 commands. 121 122 <legal all> 123 */ 124 125 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 126 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 127 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 128 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 129 130 131 /* Description CMD_EXECUTION_TIME 132 133 Consumer: DEBUG 134 Producer: REO 135 136 The amount of time REO took to excecute the command. Note 137 that this time does not include the duration of the command 138 waiting in the command ring, before the execution started. 139 140 141 In us. 142 143 <legal all> 144 */ 145 146 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 147 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 148 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 149 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 150 151 152 /* Description REO_CMD_EXECUTION_STATUS 153 154 Consumer: DEBUG 155 Producer: REO 156 157 Execution status of the command. 158 159 <enum 0 reo_successful_execution> Command has successfully 160 be executed 161 <enum 1 reo_blocked_execution> Command could not be executed 162 as the queue or cache was blocked 163 <enum 2 reo_failed_execution> Command has encountered problems 164 when executing, like the queue descriptor not being valid. 165 None of the status fields in the entire STATUS TLV are valid. 166 167 <enum 3 reo_resource_blocked> Command is NOT executed because 168 one or more descriptors were blocked. This is SW programming 169 mistake. 170 None of the status fields in the entire STATUS TLV are valid. 171 172 173 <legal 0-3> 174 */ 175 176 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 177 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 178 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 179 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 180 181 182 /* Description RESERVED_0A 183 184 <legal 0> 185 */ 186 187 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 188 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 189 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 190 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 191 192 193 /* Description TIMESTAMP 194 195 Timestamp at the moment that this status report is written. 196 197 198 <legal all> 199 */ 200 201 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 202 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 203 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 204 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 205 206 207 /* Description ERROR_DETECTED 208 209 Status for blocking resource handling 210 211 0: No error has been detected while executing this command 212 213 1: The blocking resource was not in use, and therefor it 214 could not be 'unblocked' 215 */ 216 217 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 218 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 219 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 220 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 221 222 223 /* Description UNBLOCK_TYPE 224 225 Reference to the type of Unblock command type... 226 227 <enum 0 unblock_resource_index> Unblock a blocking resource 228 229 230 <enum 1 unblock_cache> The entire cache usage is unblock. 231 232 233 <legal all> 234 */ 235 236 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 237 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 238 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 239 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 240 241 242 /* Description RESERVED_2A 243 244 <legal 0> 245 */ 246 247 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 248 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 249 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 250 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 251 252 253 /* Description RESERVED_3A 254 255 <legal 0> 256 */ 257 258 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 259 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 260 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 261 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 262 263 264 /* Description RESERVED_4A 265 266 <legal 0> 267 */ 268 269 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 270 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 271 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 272 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 273 274 275 /* Description RESERVED_5A 276 277 <legal 0> 278 */ 279 280 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 281 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 282 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 283 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 284 285 286 /* Description RESERVED_6A 287 288 <legal 0> 289 */ 290 291 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 292 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 293 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 294 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 295 296 297 /* Description RESERVED_7A 298 299 <legal 0> 300 */ 301 302 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 303 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 304 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 305 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 306 307 308 /* Description RESERVED_8A 309 310 <legal 0> 311 */ 312 313 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 314 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 315 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 316 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 317 318 319 /* Description RESERVED_9A 320 321 <legal 0> 322 */ 323 324 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 325 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 326 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 327 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 328 329 330 /* Description RESERVED_10A 331 332 <legal 0> 333 */ 334 335 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 336 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 337 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 338 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 339 340 341 /* Description RESERVED_11A 342 343 <legal 0> 344 */ 345 346 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 347 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 348 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 349 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 350 351 352 /* Description RESERVED_12A 353 354 <legal 0> 355 */ 356 357 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 358 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 359 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 360 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 361 362 363 /* Description RESERVED_13A 364 365 <legal 0> 366 */ 367 368 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 369 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 370 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 371 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 372 373 374 /* Description RESERVED_14A 375 376 <legal 0> 377 */ 378 379 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 380 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 381 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 382 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 383 384 385 /* Description RESERVED_15A 386 387 <legal 0> 388 */ 389 390 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 391 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 392 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 393 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 394 395 396 /* Description RESERVED_16A 397 398 <legal 0> 399 */ 400 401 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 402 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 403 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 404 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 405 406 407 /* Description RESERVED_17A 408 409 <legal 0> 410 */ 411 412 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 413 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 414 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 415 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 416 417 418 /* Description RESERVED_18A 419 420 <legal 0> 421 */ 422 423 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 424 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 425 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 426 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 427 428 429 /* Description RESERVED_19A 430 431 <legal 0> 432 */ 433 434 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 435 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 436 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 437 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 438 439 440 /* Description RESERVED_20A 441 442 <legal 0> 443 */ 444 445 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 446 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 447 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 448 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 449 450 451 /* Description RESERVED_21A 452 453 <legal 0> 454 */ 455 456 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 457 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 458 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 459 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 460 461 462 /* Description RESERVED_22A 463 464 <legal 0> 465 */ 466 467 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 468 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 469 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 470 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 471 472 473 /* Description RESERVED_23A 474 475 <legal 0> 476 */ 477 478 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 479 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 480 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 481 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 482 483 484 /* Description RESERVED_24A 485 486 <legal 0> 487 */ 488 489 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 490 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 491 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 492 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 493 494 495 /* Description RESERVED_25A 496 497 <legal 0> 498 */ 499 500 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 501 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 502 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 503 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 504 505 506 /* Description LOOPING_COUNT 507 508 A count value that indicates the number of times the producer 509 of entries into this Ring has looped around the ring. 510 At initialization time, this value is set to 0. On the first 511 loop, this value is set to 1. After the max value is reached 512 allowed by the number of bits for this field, the count 513 value continues with 0 again. 514 515 In case SW is the consumer of the ring entries, it can use 516 this field to figure out up to where the producer of entries 517 has created new entries. This eliminates the need to check 518 where the "head pointer' of the ring is located once the 519 SW starts processing an interrupt indicating that new entries 520 have been put into this ring... 521 522 Also note that SW if it wants only needs to look at the 523 LSB bit of this count value. 524 <legal all> 525 */ 526 527 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 528 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 529 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 530 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 531 532 533 534 #endif // REO_UNBLOCK_CACHE_STATUS 535