1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 27 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 35 36 37 struct reo_flush_timeout_list_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t error_detected : 1, // [0:0] 41 timout_list_empty : 1, // [1:1] 42 reserved_2a : 30; // [31:2] 43 uint32_t release_desc_count : 16, // [15:0] 44 forward_buf_count : 16; // [31:16] 45 uint32_t reserved_4a : 32; // [31:0] 46 uint32_t reserved_5a : 32; // [31:0] 47 uint32_t reserved_6a : 32; // [31:0] 48 uint32_t reserved_7a : 32; // [31:0] 49 uint32_t reserved_8a : 32; // [31:0] 50 uint32_t reserved_9a : 32; // [31:0] 51 uint32_t reserved_10a : 32; // [31:0] 52 uint32_t reserved_11a : 32; // [31:0] 53 uint32_t reserved_12a : 32; // [31:0] 54 uint32_t reserved_13a : 32; // [31:0] 55 uint32_t reserved_14a : 32; // [31:0] 56 uint32_t reserved_15a : 32; // [31:0] 57 uint32_t reserved_16a : 32; // [31:0] 58 uint32_t reserved_17a : 32; // [31:0] 59 uint32_t reserved_18a : 32; // [31:0] 60 uint32_t reserved_19a : 32; // [31:0] 61 uint32_t reserved_20a : 32; // [31:0] 62 uint32_t reserved_21a : 32; // [31:0] 63 uint32_t reserved_22a : 32; // [31:0] 64 uint32_t reserved_23a : 32; // [31:0] 65 uint32_t reserved_24a : 32; // [31:0] 66 uint32_t reserved_25a : 28, // [27:0] 67 looping_count : 4; // [31:28] 68 #else 69 struct uniform_reo_status_header status_header; 70 uint32_t reserved_2a : 30, // [31:2] 71 timout_list_empty : 1, // [1:1] 72 error_detected : 1; // [0:0] 73 uint32_t forward_buf_count : 16, // [31:16] 74 release_desc_count : 16; // [15:0] 75 uint32_t reserved_4a : 32; // [31:0] 76 uint32_t reserved_5a : 32; // [31:0] 77 uint32_t reserved_6a : 32; // [31:0] 78 uint32_t reserved_7a : 32; // [31:0] 79 uint32_t reserved_8a : 32; // [31:0] 80 uint32_t reserved_9a : 32; // [31:0] 81 uint32_t reserved_10a : 32; // [31:0] 82 uint32_t reserved_11a : 32; // [31:0] 83 uint32_t reserved_12a : 32; // [31:0] 84 uint32_t reserved_13a : 32; // [31:0] 85 uint32_t reserved_14a : 32; // [31:0] 86 uint32_t reserved_15a : 32; // [31:0] 87 uint32_t reserved_16a : 32; // [31:0] 88 uint32_t reserved_17a : 32; // [31:0] 89 uint32_t reserved_18a : 32; // [31:0] 90 uint32_t reserved_19a : 32; // [31:0] 91 uint32_t reserved_20a : 32; // [31:0] 92 uint32_t reserved_21a : 32; // [31:0] 93 uint32_t reserved_22a : 32; // [31:0] 94 uint32_t reserved_23a : 32; // [31:0] 95 uint32_t reserved_24a : 32; // [31:0] 96 uint32_t looping_count : 4, // [31:28] 97 reserved_25a : 28; // [27:0] 98 #endif 99 }; 100 101 102 /* Description STATUS_HEADER 103 104 Consumer: SW 105 Producer: REO 106 107 Details that can link this status with the original command. 108 It also contains info on how long REO took to execute this 109 command. 110 */ 111 112 113 /* Description REO_STATUS_NUMBER 114 115 Consumer: SW , DEBUG 116 Producer: REO 117 118 The value in this field is equal to value of the 'REO_CMD_Number' 119 field the REO command 120 121 This field helps to correlate the statuses with the REO 122 commands. 123 124 <legal all> 125 */ 126 127 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 128 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 129 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 130 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 131 132 133 /* Description CMD_EXECUTION_TIME 134 135 Consumer: DEBUG 136 Producer: REO 137 138 The amount of time REO took to excecute the command. Note 139 that this time does not include the duration of the command 140 waiting in the command ring, before the execution started. 141 142 143 In us. 144 145 <legal all> 146 */ 147 148 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 149 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 150 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 151 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 152 153 154 /* Description REO_CMD_EXECUTION_STATUS 155 156 Consumer: DEBUG 157 Producer: REO 158 159 Execution status of the command. 160 161 <enum 0 reo_successful_execution> Command has successfully 162 be executed 163 <enum 1 reo_blocked_execution> Command could not be executed 164 as the queue or cache was blocked 165 <enum 2 reo_failed_execution> Command has encountered problems 166 when executing, like the queue descriptor not being valid. 167 None of the status fields in the entire STATUS TLV are valid. 168 169 <enum 3 reo_resource_blocked> Command is NOT executed because 170 one or more descriptors were blocked. This is SW programming 171 mistake. 172 None of the status fields in the entire STATUS TLV are valid. 173 174 175 <legal 0-3> 176 */ 177 178 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 179 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 180 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 181 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 182 183 184 /* Description RESERVED_0A 185 186 <legal 0> 187 */ 188 189 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 190 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 191 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 192 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 193 194 195 /* Description TIMESTAMP 196 197 Timestamp at the moment that this status report is written. 198 199 200 <legal all> 201 */ 202 203 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 204 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 205 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 206 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 207 208 209 /* Description ERROR_DETECTED 210 211 0: No error has been detected while executing this command 212 213 1: command not properly executed and returned with an error 214 215 216 NOTE: Current no error is defined, but field is put in place 217 to avoid data structure changes in future... 218 */ 219 220 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 221 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 222 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 223 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 224 225 226 /* Description TIMOUT_LIST_EMPTY 227 228 When set, REO has depleted the timeout list and all entries 229 are gone. 230 <legal all> 231 */ 232 233 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 234 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 235 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 236 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 237 238 239 /* Description RESERVED_2A 240 241 <legal 0> 242 */ 243 244 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 245 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 246 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 247 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 248 249 250 /* Description RELEASE_DESC_COUNT 251 252 Consumer: REO 253 Producer: SW 254 255 The number of link descriptors released 256 <legal all> 257 */ 258 259 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 260 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 261 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 262 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 263 264 265 /* Description FORWARD_BUF_COUNT 266 267 Consumer: REO 268 Producer: SW 269 270 The number of buffers forwarded to the REO destination rings 271 272 <legal all> 273 */ 274 275 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 276 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 277 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 278 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 279 280 281 /* Description RESERVED_4A 282 283 <legal 0> 284 */ 285 286 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 287 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 288 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 289 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 290 291 292 /* Description RESERVED_5A 293 294 <legal 0> 295 */ 296 297 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 298 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 299 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 300 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 301 302 303 /* Description RESERVED_6A 304 305 <legal 0> 306 */ 307 308 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 309 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 310 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 311 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 312 313 314 /* Description RESERVED_7A 315 316 <legal 0> 317 */ 318 319 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 320 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 321 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 322 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 323 324 325 /* Description RESERVED_8A 326 327 <legal 0> 328 */ 329 330 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 331 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 332 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 333 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 334 335 336 /* Description RESERVED_9A 337 338 <legal 0> 339 */ 340 341 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 342 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 343 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 344 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 345 346 347 /* Description RESERVED_10A 348 349 <legal 0> 350 */ 351 352 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 353 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 354 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 355 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 356 357 358 /* Description RESERVED_11A 359 360 <legal 0> 361 */ 362 363 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 364 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 365 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 366 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 367 368 369 /* Description RESERVED_12A 370 371 <legal 0> 372 */ 373 374 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 375 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 376 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 377 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 378 379 380 /* Description RESERVED_13A 381 382 <legal 0> 383 */ 384 385 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 386 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 387 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 388 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 389 390 391 /* Description RESERVED_14A 392 393 <legal 0> 394 */ 395 396 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 397 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 398 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 399 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 400 401 402 /* Description RESERVED_15A 403 404 <legal 0> 405 */ 406 407 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 408 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 409 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 410 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 411 412 413 /* Description RESERVED_16A 414 415 <legal 0> 416 */ 417 418 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 419 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 420 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 421 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 422 423 424 /* Description RESERVED_17A 425 426 <legal 0> 427 */ 428 429 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 430 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 431 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 432 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 433 434 435 /* Description RESERVED_18A 436 437 <legal 0> 438 */ 439 440 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 441 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 442 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 443 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 444 445 446 /* Description RESERVED_19A 447 448 <legal 0> 449 */ 450 451 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 452 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 453 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 454 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 455 456 457 /* Description RESERVED_20A 458 459 <legal 0> 460 */ 461 462 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 463 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 464 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 465 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 466 467 468 /* Description RESERVED_21A 469 470 <legal 0> 471 */ 472 473 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 474 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 475 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 476 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 477 478 479 /* Description RESERVED_22A 480 481 <legal 0> 482 */ 483 484 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 485 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 486 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 487 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 488 489 490 /* Description RESERVED_23A 491 492 <legal 0> 493 */ 494 495 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 496 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 497 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 498 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 499 500 501 /* Description RESERVED_24A 502 503 <legal 0> 504 */ 505 506 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 507 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 508 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 509 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 510 511 512 /* Description RESERVED_25A 513 514 <legal 0> 515 */ 516 517 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 518 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 519 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 520 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 521 522 523 /* Description LOOPING_COUNT 524 525 A count value that indicates the number of times the producer 526 of entries into this Ring has looped around the ring. 527 At initialization time, this value is set to 0. On the first 528 loop, this value is set to 1. After the max value is reached 529 allowed by the number of bits for this field, the count 530 value continues with 0 again. 531 532 In case SW is the consumer of the ring entries, it can use 533 this field to figure out up to where the producer of entries 534 has created new entries. This eliminates the need to check 535 where the "head pointer' of the ring is located once the 536 SW starts processing an interrupt indicating that new entries 537 have been put into this ring... 538 539 Also note that SW if it wants only needs to look at the 540 LSB bit of this count value. 541 <legal all> 542 */ 543 544 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 545 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 546 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 547 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 548 549 550 551 #endif // REO_FLUSH_TIMEOUT_LIST_STATUS 552