1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
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21 
22 
23 
24 
25 
26 #ifndef _REO_FLUSH_TIMEOUT_LIST_H_
27 #define _REO_FLUSH_TIMEOUT_LIST_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "uniform_reo_cmd_header.h"
32 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
33 
34 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
35 
36 
37 struct reo_flush_timeout_list {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   uniform_reo_cmd_header                                    cmd_header;
40              uint32_t ac_timout_list                                          :  2, // [1:0]
41                       reserved_1                                              : 30; // [31:2]
42              uint32_t minimum_release_desc_count                              : 16, // [15:0]
43                       minimum_forward_buf_count                               : 16; // [31:16]
44              uint32_t reserved_3a                                             : 32; // [31:0]
45              uint32_t reserved_4a                                             : 32; // [31:0]
46              uint32_t reserved_5a                                             : 32; // [31:0]
47              uint32_t reserved_6a                                             : 32; // [31:0]
48              uint32_t reserved_7a                                             : 32; // [31:0]
49              uint32_t reserved_8a                                             : 32; // [31:0]
50              uint32_t tlv64_padding                                           : 32; // [31:0]
51 #else
52              struct   uniform_reo_cmd_header                                    cmd_header;
53              uint32_t reserved_1                                              : 30, // [31:2]
54                       ac_timout_list                                          :  2; // [1:0]
55              uint32_t minimum_forward_buf_count                               : 16, // [31:16]
56                       minimum_release_desc_count                              : 16; // [15:0]
57              uint32_t reserved_3a                                             : 32; // [31:0]
58              uint32_t reserved_4a                                             : 32; // [31:0]
59              uint32_t reserved_5a                                             : 32; // [31:0]
60              uint32_t reserved_6a                                             : 32; // [31:0]
61              uint32_t reserved_7a                                             : 32; // [31:0]
62              uint32_t reserved_8a                                             : 32; // [31:0]
63              uint32_t tlv64_padding                                           : 32; // [31:0]
64 #endif
65 };
66 
67 
68 /* Description		CMD_HEADER
69 
70 			Consumer: REO
71 			Producer: SW
72 
73 			Details for command execution tracking purposes.
74 */
75 
76 
77 /* Description		REO_CMD_NUMBER
78 
79 			Consumer: REO/SW/DEBUG
80 			Producer: SW
81 
82 			This number can be used by SW to track, identify and link
83 			 the created commands with the command statusses
84 
85 
86 			<legal all>
87 */
88 
89 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET                     0x0000000000000000
90 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB                        0
91 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB                        15
92 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK                       0x000000000000ffff
93 
94 
95 /* Description		REO_STATUS_REQUIRED
96 
97 			Consumer: REO
98 			Producer: SW
99 
100 			<enum 0 NoStatus> REO does not need to generate a status
101 			 TLV for the execution of this command
102 			<enum 1 StatusRequired> REO shall generate a status TLV
103 			for the execution of this command
104 
105 			<legal all>
106 */
107 
108 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                0x0000000000000000
109 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB                   16
110 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB                   16
111 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK                  0x0000000000010000
112 
113 
114 /* Description		RESERVED_0A
115 
116 			<legal 0>
117 */
118 
119 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET                        0x0000000000000000
120 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB                           17
121 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB                           31
122 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK                          0x00000000fffe0000
123 
124 
125 /* Description		AC_TIMOUT_LIST
126 
127 			Consumer: REO
128 			Producer: SW
129 
130 			The AC_timeout list to be used for this command
131 			<legal all>
132 */
133 
134 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET                                0x0000000000000000
135 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB                                   32
136 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB                                   33
137 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK                                  0x0000000300000000
138 
139 
140 /* Description		RESERVED_1
141 
142 			<legal 0>
143 */
144 
145 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET                                    0x0000000000000000
146 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB                                       34
147 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB                                       63
148 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK                                      0xfffffffc00000000
149 
150 
151 /* Description		MINIMUM_RELEASE_DESC_COUNT
152 
153 			Consumer: REO
154 			Producer: SW
155 
156 			The minimum number of link descriptors requested to be released.
157 			If set to 0, only buffer release counts seems to be important...
158 			When set to very high value, likely the entire timeout list
159 			 will be exhausted before this count is reached or maybe
160 			 this count will not get reached. REO however will stop
161 			here as it can not do anything else.
162 
163 			When both this field and field Minimum_forward_buf_count
164 			 are > 0, REO needs to meet both requirements. When both
165 			 entries are 0 (which should be a programming error), REO
166 			 does not need to do anything.
167 
168 			Note that this includes counts of MPDU link Desc as well
169 			 as MSDU link Desc. Where the count of MSDU link Desc is
170 			 not known to REO it's approximated by deriving from MSDU
171 			 count
172 			<legal all>
173 */
174 
175 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET                    0x0000000000000008
176 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB                       0
177 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB                       15
178 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK                      0x000000000000ffff
179 
180 
181 /* Description		MINIMUM_FORWARD_BUF_COUNT
182 
183 			Consumer: REO
184 			Producer: SW
185 
186 			The minimum number of buffer descriptors requested to be
187 			 passed on to the REO destination rings.
188 
189 			If set to 0, only descriptor release counts seems to be
190 			important...
191 
192 			When set to very high value, likely the entire timeout list
193 			 will be exhausted before this count is reached or maybe
194 			 this count will not get reached. REO however will stop
195 			here as it can not do anything else.
196 
197 			Note that REO does not know the exact buffer count. This
198 			 can be approximated by using the MSDU_COUNT
199 			<legal all>
200 */
201 
202 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET                     0x0000000000000008
203 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB                        16
204 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB                        31
205 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK                       0x00000000ffff0000
206 
207 
208 /* Description		RESERVED_3A
209 
210 			<legal 0>
211 */
212 
213 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET                                   0x0000000000000008
214 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB                                      32
215 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB                                      63
216 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK                                     0xffffffff00000000
217 
218 
219 /* Description		RESERVED_4A
220 
221 			<legal 0>
222 */
223 
224 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET                                   0x0000000000000010
225 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB                                      0
226 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB                                      31
227 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK                                     0x00000000ffffffff
228 
229 
230 /* Description		RESERVED_5A
231 
232 			<legal 0>
233 */
234 
235 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET                                   0x0000000000000010
236 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB                                      32
237 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB                                      63
238 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK                                     0xffffffff00000000
239 
240 
241 /* Description		RESERVED_6A
242 
243 			<legal 0>
244 */
245 
246 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET                                   0x0000000000000018
247 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB                                      0
248 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB                                      31
249 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK                                     0x00000000ffffffff
250 
251 
252 /* Description		RESERVED_7A
253 
254 			<legal 0>
255 */
256 
257 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET                                   0x0000000000000018
258 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB                                      32
259 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB                                      63
260 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK                                     0xffffffff00000000
261 
262 
263 /* Description		RESERVED_8A
264 
265 			<legal 0>
266 */
267 
268 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET                                   0x0000000000000020
269 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB                                      0
270 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB                                      31
271 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK                                     0x00000000ffffffff
272 
273 
274 /* Description		TLV64_PADDING
275 
276 			Automatic DWORD padding inserted while converting TLV32
277 			to TLV64 for 64 bit ARCH
278 			<legal 0>
279 */
280 
281 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET                                 0x0000000000000020
282 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB                                    32
283 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB                                    63
284 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK                                   0xffffffff00000000
285 
286 
287 
288 #endif   // REO_FLUSH_TIMEOUT_LIST
289