1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 27 #define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_status_header.h" 32 #define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26 33 34 #define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13 35 36 37 struct reo_descriptor_threshold_reached_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_status_header status_header; 40 uint32_t threshold_index : 2, // [1:0] 41 reserved_2 : 30; // [31:2] 42 uint32_t link_descriptor_counter0 : 24, // [23:0] 43 reserved_3 : 8; // [31:24] 44 uint32_t link_descriptor_counter1 : 24, // [23:0] 45 reserved_4 : 8; // [31:24] 46 uint32_t link_descriptor_counter2 : 24, // [23:0] 47 reserved_5 : 8; // [31:24] 48 uint32_t link_descriptor_counter_sum : 26, // [25:0] 49 reserved_6 : 6; // [31:26] 50 uint32_t reserved_7 : 32; // [31:0] 51 uint32_t reserved_8 : 32; // [31:0] 52 uint32_t reserved_9a : 32; // [31:0] 53 uint32_t reserved_10a : 32; // [31:0] 54 uint32_t reserved_11a : 32; // [31:0] 55 uint32_t reserved_12a : 32; // [31:0] 56 uint32_t reserved_13a : 32; // [31:0] 57 uint32_t reserved_14a : 32; // [31:0] 58 uint32_t reserved_15a : 32; // [31:0] 59 uint32_t reserved_16a : 32; // [31:0] 60 uint32_t reserved_17a : 32; // [31:0] 61 uint32_t reserved_18a : 32; // [31:0] 62 uint32_t reserved_19a : 32; // [31:0] 63 uint32_t reserved_20a : 32; // [31:0] 64 uint32_t reserved_21a : 32; // [31:0] 65 uint32_t reserved_22a : 32; // [31:0] 66 uint32_t reserved_23a : 32; // [31:0] 67 uint32_t reserved_24a : 32; // [31:0] 68 uint32_t reserved_25a : 28, // [27:0] 69 looping_count : 4; // [31:28] 70 #else 71 struct uniform_reo_status_header status_header; 72 uint32_t reserved_2 : 30, // [31:2] 73 threshold_index : 2; // [1:0] 74 uint32_t reserved_3 : 8, // [31:24] 75 link_descriptor_counter0 : 24; // [23:0] 76 uint32_t reserved_4 : 8, // [31:24] 77 link_descriptor_counter1 : 24; // [23:0] 78 uint32_t reserved_5 : 8, // [31:24] 79 link_descriptor_counter2 : 24; // [23:0] 80 uint32_t reserved_6 : 6, // [31:26] 81 link_descriptor_counter_sum : 26; // [25:0] 82 uint32_t reserved_7 : 32; // [31:0] 83 uint32_t reserved_8 : 32; // [31:0] 84 uint32_t reserved_9a : 32; // [31:0] 85 uint32_t reserved_10a : 32; // [31:0] 86 uint32_t reserved_11a : 32; // [31:0] 87 uint32_t reserved_12a : 32; // [31:0] 88 uint32_t reserved_13a : 32; // [31:0] 89 uint32_t reserved_14a : 32; // [31:0] 90 uint32_t reserved_15a : 32; // [31:0] 91 uint32_t reserved_16a : 32; // [31:0] 92 uint32_t reserved_17a : 32; // [31:0] 93 uint32_t reserved_18a : 32; // [31:0] 94 uint32_t reserved_19a : 32; // [31:0] 95 uint32_t reserved_20a : 32; // [31:0] 96 uint32_t reserved_21a : 32; // [31:0] 97 uint32_t reserved_22a : 32; // [31:0] 98 uint32_t reserved_23a : 32; // [31:0] 99 uint32_t reserved_24a : 32; // [31:0] 100 uint32_t looping_count : 4, // [31:28] 101 reserved_25a : 28; // [27:0] 102 #endif 103 }; 104 105 106 /* Description STATUS_HEADER 107 108 Consumer: SW 109 Producer: REO 110 111 Details that can link this status with the original command. 112 It also contains info on how long REO took to execute this 113 command. 114 */ 115 116 117 /* Description REO_STATUS_NUMBER 118 119 Consumer: SW , DEBUG 120 Producer: REO 121 122 The value in this field is equal to value of the 'REO_CMD_Number' 123 field the REO command 124 125 This field helps to correlate the statuses with the REO 126 commands. 127 128 <legal all> 129 */ 130 131 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 132 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 133 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 134 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 135 136 137 /* Description CMD_EXECUTION_TIME 138 139 Consumer: DEBUG 140 Producer: REO 141 142 The amount of time REO took to excecute the command. Note 143 that this time does not include the duration of the command 144 waiting in the command ring, before the execution started. 145 146 147 In us. 148 149 <legal all> 150 */ 151 152 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 153 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 154 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 155 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 156 157 158 /* Description REO_CMD_EXECUTION_STATUS 159 160 Consumer: DEBUG 161 Producer: REO 162 163 Execution status of the command. 164 165 <enum 0 reo_successful_execution> Command has successfully 166 be executed 167 <enum 1 reo_blocked_execution> Command could not be executed 168 as the queue or cache was blocked 169 <enum 2 reo_failed_execution> Command has encountered problems 170 when executing, like the queue descriptor not being valid. 171 None of the status fields in the entire STATUS TLV are valid. 172 173 <enum 3 reo_resource_blocked> Command is NOT executed because 174 one or more descriptors were blocked. This is SW programming 175 mistake. 176 None of the status fields in the entire STATUS TLV are valid. 177 178 179 <legal 0-3> 180 */ 181 182 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 183 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 184 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 185 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 186 187 188 /* Description RESERVED_0A 189 190 <legal 0> 191 */ 192 193 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 194 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 195 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 196 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 197 198 199 /* Description TIMESTAMP 200 201 Timestamp at the moment that this status report is written. 202 203 204 <legal all> 205 */ 206 207 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 208 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 209 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 210 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 211 212 213 /* Description THRESHOLD_INDEX 214 215 The index of the threshold register whose value got reached 216 217 218 <enum 0 reo_desc_counter0_threshold> 219 <enum 1 reo_desc_counter1_threshold> 220 <enum 2 reo_desc_counter2_threshold> 221 <enum 3 reo_desc_counter_sum_threshold> 222 223 <legal all> 224 */ 225 226 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008 227 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 228 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 229 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003 230 231 232 /* Description RESERVED_2 233 234 <legal 0> 235 */ 236 237 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008 238 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 239 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 240 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc 241 242 243 /* Description LINK_DESCRIPTOR_COUNTER0 244 245 Value of this counter at generation of this message 246 <legal all> 247 */ 248 249 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008 250 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32 251 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55 252 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000 253 254 255 /* Description RESERVED_3 256 257 <legal 0> 258 */ 259 260 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008 261 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56 262 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63 263 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000 264 265 266 /* Description LINK_DESCRIPTOR_COUNTER1 267 268 Value of this counter at generation of this message 269 <legal all> 270 */ 271 272 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010 273 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 274 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 275 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff 276 277 278 /* Description RESERVED_4 279 280 <legal 0> 281 */ 282 283 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010 284 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 285 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 286 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000 287 288 289 /* Description LINK_DESCRIPTOR_COUNTER2 290 291 Value of this counter at generation of this message 292 <legal all> 293 */ 294 295 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010 296 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32 297 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55 298 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000 299 300 301 /* Description RESERVED_5 302 303 <legal 0> 304 */ 305 306 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010 307 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56 308 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63 309 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000 310 311 312 /* Description LINK_DESCRIPTOR_COUNTER_SUM 313 314 Value of this counter at generation of this message 315 <legal all> 316 */ 317 318 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018 319 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 320 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 321 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff 322 323 324 /* Description RESERVED_6 325 326 <legal 0> 327 */ 328 329 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018 330 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 331 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 332 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000 333 334 335 /* Description RESERVED_7 336 337 <legal 0> 338 */ 339 340 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018 341 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32 342 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63 343 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000 344 345 346 /* Description RESERVED_8 347 348 <legal 0> 349 */ 350 351 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020 352 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 353 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 354 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff 355 356 357 /* Description RESERVED_9A 358 359 <legal 0> 360 */ 361 362 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 363 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32 364 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63 365 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000 366 367 368 /* Description RESERVED_10A 369 370 <legal 0> 371 */ 372 373 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 374 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 375 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 376 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 377 378 379 /* Description RESERVED_11A 380 381 <legal 0> 382 */ 383 384 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 385 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32 386 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63 387 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000 388 389 390 /* Description RESERVED_12A 391 392 <legal 0> 393 */ 394 395 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 396 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 397 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 398 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 399 400 401 /* Description RESERVED_13A 402 403 <legal 0> 404 */ 405 406 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 407 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32 408 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63 409 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000 410 411 412 /* Description RESERVED_14A 413 414 <legal 0> 415 */ 416 417 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 418 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 419 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 420 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 421 422 423 /* Description RESERVED_15A 424 425 <legal 0> 426 */ 427 428 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 429 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32 430 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63 431 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000 432 433 434 /* Description RESERVED_16A 435 436 <legal 0> 437 */ 438 439 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 440 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 441 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 442 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 443 444 445 /* Description RESERVED_17A 446 447 <legal 0> 448 */ 449 450 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 451 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32 452 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63 453 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000 454 455 456 /* Description RESERVED_18A 457 458 <legal 0> 459 */ 460 461 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 462 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 463 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 464 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 465 466 467 /* Description RESERVED_19A 468 469 <legal 0> 470 */ 471 472 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 473 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32 474 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63 475 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000 476 477 478 /* Description RESERVED_20A 479 480 <legal 0> 481 */ 482 483 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 484 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 485 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 486 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 487 488 489 /* Description RESERVED_21A 490 491 <legal 0> 492 */ 493 494 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 495 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32 496 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63 497 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000 498 499 500 /* Description RESERVED_22A 501 502 <legal 0> 503 */ 504 505 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 506 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 507 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 508 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 509 510 511 /* Description RESERVED_23A 512 513 <legal 0> 514 */ 515 516 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 517 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32 518 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63 519 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000 520 521 522 /* Description RESERVED_24A 523 524 <legal 0> 525 */ 526 527 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 528 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 529 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 530 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 531 532 533 /* Description RESERVED_25A 534 535 <legal 0> 536 */ 537 538 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 539 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32 540 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59 541 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 542 543 544 /* Description LOOPING_COUNT 545 546 A count value that indicates the number of times the producer 547 of entries into this Ring has looped around the ring. 548 At initialization time, this value is set to 0. On the first 549 loop, this value is set to 1. After the max value is reached 550 allowed by the number of bits for this field, the count 551 value continues with 0 again. 552 553 In case SW is the consumer of the ring entries, it can use 554 this field to figure out up to where the producer of entries 555 has created new entries. This eliminates the need to check 556 where the "head pointer' of the ring is located once the 557 SW starts processing an interrupt indicating that new entries 558 have been put into this ring... 559 560 Also note that SW if it wants only needs to look at the 561 LSB bit of this count value. 562 <legal all> 563 */ 564 565 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 566 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60 567 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63 568 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 569 570 571 572 #endif // REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 573