1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PHYRX_PKT_END_INFO_H_ 27 #define _PHYRX_PKT_END_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "receive_rssi_info.h" 32 #include "rx_timing_offset_info.h" 33 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 34 35 36 struct phyrx_pkt_end_info { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t phy_internal_nap : 1, // [0:0] 39 location_info_valid : 1, // [1:1] 40 timing_info_valid : 1, // [2:2] 41 rssi_info_valid : 1, // [3:3] 42 reserved_0a : 1, // [4:4] 43 frameless_frame_received : 1, // [5:5] 44 reserved_0b : 2, // [7:6] 45 rssi_comb : 8, // [15:8] 46 reserved_0c : 16; // [31:16] 47 uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] 48 uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] 49 uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] 50 uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] 51 struct rx_timing_offset_info rx_timing_offset_info_details; 52 struct receive_rssi_info post_rssi_info_details; 53 uint32_t phy_sw_status_31_0 : 32; // [31:0] 54 uint32_t phy_sw_status_63_32 : 32; // [31:0] 55 #else 56 uint32_t reserved_0c : 16, // [31:16] 57 rssi_comb : 8, // [15:8] 58 reserved_0b : 2, // [7:6] 59 frameless_frame_received : 1, // [5:5] 60 reserved_0a : 1, // [4:4] 61 rssi_info_valid : 1, // [3:3] 62 timing_info_valid : 1, // [2:2] 63 location_info_valid : 1, // [1:1] 64 phy_internal_nap : 1; // [0:0] 65 uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] 66 uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] 67 uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] 68 uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] 69 struct rx_timing_offset_info rx_timing_offset_info_details; 70 struct receive_rssi_info post_rssi_info_details; 71 uint32_t phy_sw_status_31_0 : 32; // [31:0] 72 uint32_t phy_sw_status_63_32 : 32; // [31:0] 73 #endif 74 }; 75 76 77 /* Description PHY_INTERNAL_NAP 78 79 When set, PHY RX entered an internal NAP state, as PHY determined 80 that this reception was not destined to this device 81 */ 82 83 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000 84 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0 85 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0 86 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001 87 88 89 /* Description LOCATION_INFO_VALID 90 91 Indicates that the RX_LOCATION_INFO structure later on in 92 the TLV contains valid info 93 */ 94 95 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 96 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 97 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 98 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 99 100 101 /* Description TIMING_INFO_VALID 102 103 Indicates that the RX_TIMING_OFFSET_INFO structure later 104 on in the TLV contains valid info 105 */ 106 107 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 108 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 109 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 110 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 111 112 113 /* Description RSSI_INFO_VALID 114 115 Indicates that the RECEIVE_RSSI_INFO structure later on 116 in the TLV contains valid info 117 */ 118 119 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 120 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 121 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 122 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 123 124 125 /* Description RESERVED_0A 126 127 <legal 0> 128 */ 129 130 #define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 131 #define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 132 #define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 133 #define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 134 135 136 /* Description FRAMELESS_FRAME_RECEIVED 137 138 When set, PHY has received the 'frameless frame' . Can be 139 used in the 'MU-RTS -CTS exchange where CTS reception can 140 be problematic. 141 <legal all> 142 */ 143 144 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 145 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 146 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 147 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 148 149 150 /* Description RESERVED_0B 151 152 <legal 0> 153 */ 154 155 #define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 156 #define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 157 #define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 158 #define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 159 160 161 /* Description RSSI_COMB 162 163 Combined rssi of all chains. Based on primary channel RSSI. 164 165 166 This can be used by SW for cases, e.g. Ack/BlockAck responses, 167 where 'PHYRX_RSSI_LEGACY' is not available to SW. 168 169 RSSI is reported as 8b signed values. Nominally value is 170 in dB units above or below the noisefloor(minCCApwr). 171 172 The resolution can be: 173 1dB or 0.5dB. This is statically configured within the PHY 174 and MAC 175 176 In case of 1dB, the Range is: 177 -128dB to 127dB 178 179 In case of 0.5dB, the Range is: 180 -64dB to 63.5dB 181 182 <legal all> 183 */ 184 185 #define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 186 #define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 187 #define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 188 #define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 189 190 191 /* Description RESERVED_0C 192 193 <legal 0> 194 */ 195 196 #define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 197 #define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 198 #define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 199 #define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 200 201 202 /* Description PHY_TIMESTAMP_1_LOWER_32 203 204 TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI 205 of the first rising edge of rx_clear_pri after TX_PHY_DESC. . 206 This field should set to 0 by the PHY and should be updated 207 by the AMPI before being forwarded to the rest of the MAC. 208 This field indicates the lower 32 bits of the timestamp 209 */ 210 211 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 212 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 213 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 214 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 215 216 217 /* Description PHY_TIMESTAMP_1_UPPER_32 218 219 TODO PHY: cleanup description 220 The PHY timestamp in the AMPI of the first rising edge of 221 rx_clear_pri after TX_PHY_DESC. This field should set 222 to 0 by the PHY and should be updated by the AMPI before 223 being forwarded to the rest of the MAC. This field indicates 224 the upper 32 bits of the timestamp 225 */ 226 227 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 228 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 229 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 230 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 231 232 233 /* Description PHY_TIMESTAMP_2_LOWER_32 234 235 TODO PHY: cleanup description 236 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 237 after RX_RSSI_LEGACY. This field should set to 0 by the 238 PHY and should be updated by the AMPI before being forwarded 239 to the rest of the MAC. This field indicates the lower 240 32 bits of the timestamp 241 */ 242 243 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 244 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 245 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 246 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 247 248 249 /* Description PHY_TIMESTAMP_2_UPPER_32 250 251 TODO PHY: cleanup description 252 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 253 after RX_RSSI_LEGACY. This field should set to 0 by the 254 PHY and should be updated by the AMPI before being forwarded 255 to the rest of the MAC. This field indicates the upper 256 32 bits of the timestamp 257 */ 258 259 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 260 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 261 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 262 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 263 264 265 /* Description RX_TIMING_OFFSET_INFO_DETAILS 266 267 Overview of timing offset related info 268 */ 269 270 271 /* Description RESIDUAL_PHASE_OFFSET 272 273 Cumulative reference frequency error at end of RX packet, 274 expressed as the phase offset measured over 0.8us. 275 <legal all> 276 */ 277 278 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 279 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 280 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 281 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 282 283 284 /* Description RESERVED 285 286 <legal 0> 287 */ 288 289 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014 290 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 291 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31 292 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 293 294 295 /* Description POST_RSSI_INFO_DETAILS 296 297 Overview of the post-RSSI values. 298 */ 299 300 301 /* Description RSSI_PRI20_CHAIN0 302 303 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 304 305 Value of 0x80 indicates invalid. 306 */ 307 308 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 309 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 310 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 311 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 312 313 314 /* Description RSSI_EXT20_CHAIN0 315 316 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 317 318 Value of 0x80 indicates invalid. 319 */ 320 321 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 322 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 323 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 324 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 325 326 327 /* Description RSSI_EXT40_LOW20_CHAIN0 328 329 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 330 331 Value of 0x80 indicates invalid. 332 */ 333 334 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 335 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 336 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 337 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 338 339 340 /* Description RSSI_EXT40_HIGH20_CHAIN0 341 342 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 343 bandwidth. 344 Value of 0x80 indicates invalid. 345 */ 346 347 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 348 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 349 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 350 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 351 352 353 /* Description RSSI_EXT80_LOW20_CHAIN0 354 355 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 356 357 Value of 0x80 indicates invalid. 358 */ 359 360 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c 361 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 362 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 363 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 364 365 366 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 367 368 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 369 MHz bandwidth. 370 Value of 0x80 indicates invalid. 371 */ 372 373 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c 374 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 375 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 376 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 377 378 379 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 380 381 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 382 MHz bandwidth. 383 Value of 0x80 indicates invalid. 384 */ 385 386 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c 387 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 388 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 389 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 390 391 392 /* Description RSSI_EXT80_HIGH20_CHAIN0 393 394 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 395 bandwidth. 396 Value of 0x80 indicates invalid. 397 */ 398 399 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c 400 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 401 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 402 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 403 404 405 /* Description RSSI_EXT160_0_CHAIN0 406 407 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 408 bandwidth. 409 Value of 0x80 indicates invalid. 410 */ 411 412 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 413 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 414 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 415 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff 416 417 418 /* Description RSSI_EXT160_1_CHAIN0 419 420 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 421 bandwidth. 422 Value of 0x80 indicates invalid. 423 */ 424 425 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 426 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 427 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 428 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 429 430 431 /* Description RSSI_EXT160_2_CHAIN0 432 433 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 434 bandwidth. 435 Value of 0x80 indicates invalid. 436 */ 437 438 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 439 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 440 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 441 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 442 443 444 /* Description RSSI_EXT160_3_CHAIN0 445 446 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 447 bandwidth. 448 Value of 0x80 indicates invalid. 449 */ 450 451 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 452 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 453 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 454 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 455 456 457 /* Description RSSI_EXT160_4_CHAIN0 458 459 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 460 bandwidth. 461 Value of 0x80 indicates invalid. 462 */ 463 464 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 465 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 466 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 467 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff 468 469 470 /* Description RSSI_EXT160_5_CHAIN0 471 472 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 473 bandwidth. 474 Value of 0x80 indicates invalid. 475 */ 476 477 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 478 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 479 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 480 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 481 482 483 /* Description RSSI_EXT160_6_CHAIN0 484 485 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 486 bandwidth. 487 Value of 0x80 indicates invalid. 488 */ 489 490 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 491 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 492 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 493 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 494 495 496 /* Description RSSI_EXT160_7_CHAIN0 497 498 RSSI of RX PPDU on chain 0 of extension 160, highest 20 499 MHz bandwidth. 500 Value of 0x80 indicates invalid. 501 */ 502 503 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 504 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 505 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 506 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 507 508 509 /* Description RSSI_PRI20_CHAIN1 510 511 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 512 513 Value of 0x80 indicates invalid. 514 */ 515 516 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 517 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 518 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 519 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 520 521 522 /* Description RSSI_EXT20_CHAIN1 523 524 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 525 526 Value of 0x80 indicates invalid. 527 */ 528 529 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 530 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 531 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 532 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 533 534 535 /* Description RSSI_EXT40_LOW20_CHAIN1 536 537 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 538 539 Value of 0x80 indicates invalid. 540 */ 541 542 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 543 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 544 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 545 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 546 547 548 /* Description RSSI_EXT40_HIGH20_CHAIN1 549 550 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 551 bandwidth. 552 Value of 0x80 indicates invalid. 553 */ 554 555 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 556 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 557 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 558 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 559 560 561 /* Description RSSI_EXT80_LOW20_CHAIN1 562 563 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 564 565 Value of 0x80 indicates invalid. 566 */ 567 568 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c 569 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 570 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 571 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 572 573 574 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 575 576 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 577 MHz bandwidth. 578 Value of 0x80 indicates invalid. 579 */ 580 581 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c 582 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 583 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 584 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 585 586 587 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 588 589 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 590 MHz bandwidth. 591 Value of 0x80 indicates invalid. 592 */ 593 594 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c 595 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 596 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 597 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 598 599 600 /* Description RSSI_EXT80_HIGH20_CHAIN1 601 602 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 603 bandwidth. 604 Value of 0x80 indicates invalid. 605 */ 606 607 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c 608 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 609 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 610 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 611 612 613 /* Description RSSI_EXT160_0_CHAIN1 614 615 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 616 bandwidth. 617 Value of 0x80 indicates invalid. 618 */ 619 620 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 621 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 622 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 623 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff 624 625 626 /* Description RSSI_EXT160_1_CHAIN1 627 628 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 629 bandwidth. 630 Value of 0x80 indicates invalid. 631 */ 632 633 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 634 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 635 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 636 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 637 638 639 /* Description RSSI_EXT160_2_CHAIN1 640 641 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 642 bandwidth. 643 Value of 0x80 indicates invalid. 644 */ 645 646 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 647 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 648 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 649 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 650 651 652 /* Description RSSI_EXT160_3_CHAIN1 653 654 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 655 bandwidth. 656 Value of 0x80 indicates invalid. 657 */ 658 659 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 660 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 661 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 662 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 663 664 665 /* Description RSSI_EXT160_4_CHAIN1 666 667 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 668 bandwidth. 669 Value of 0x80 indicates invalid. 670 */ 671 672 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 673 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 674 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 675 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff 676 677 678 /* Description RSSI_EXT160_5_CHAIN1 679 680 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 681 bandwidth. 682 Value of 0x80 indicates invalid. 683 */ 684 685 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 686 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 687 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 688 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 689 690 691 /* Description RSSI_EXT160_6_CHAIN1 692 693 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 694 bandwidth. 695 Value of 0x80 indicates invalid. 696 */ 697 698 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 699 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 700 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 701 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 702 703 704 /* Description RSSI_EXT160_7_CHAIN1 705 706 RSSI of RX PPDU on chain 1 of extension 160, highest 20 707 MHz bandwidth. 708 Value of 0x80 indicates invalid. 709 */ 710 711 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 712 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 713 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 714 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 715 716 717 /* Description RSSI_PRI20_CHAIN2 718 719 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 720 721 Value of 0x80 indicates invalid. 722 */ 723 724 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 725 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 726 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 727 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 728 729 730 /* Description RSSI_EXT20_CHAIN2 731 732 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 733 734 Value of 0x80 indicates invalid. 735 */ 736 737 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 738 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 739 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 740 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 741 742 743 /* Description RSSI_EXT40_LOW20_CHAIN2 744 745 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 746 747 Value of 0x80 indicates invalid. 748 */ 749 750 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 751 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 752 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 753 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 754 755 756 /* Description RSSI_EXT40_HIGH20_CHAIN2 757 758 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 759 bandwidth. 760 Value of 0x80 indicates invalid. 761 */ 762 763 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 764 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 765 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 766 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 767 768 769 /* Description RSSI_EXT80_LOW20_CHAIN2 770 771 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 772 773 Value of 0x80 indicates invalid. 774 */ 775 776 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c 777 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 778 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 779 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 780 781 782 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 783 784 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 785 MHz bandwidth. 786 Value of 0x80 indicates invalid. 787 */ 788 789 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c 790 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 791 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 792 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 793 794 795 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 796 797 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 798 MHz bandwidth. 799 Value of 0x80 indicates invalid. 800 */ 801 802 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c 803 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 804 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 805 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 806 807 808 /* Description RSSI_EXT80_HIGH20_CHAIN2 809 810 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 811 bandwidth. 812 Value of 0x80 indicates invalid. 813 */ 814 815 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c 816 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 817 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 818 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 819 820 821 /* Description RSSI_EXT160_0_CHAIN2 822 823 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 824 bandwidth. 825 Value of 0x80 indicates invalid. 826 */ 827 828 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 829 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 830 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 831 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff 832 833 834 /* Description RSSI_EXT160_1_CHAIN2 835 836 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 837 bandwidth. 838 Value of 0x80 indicates invalid. 839 */ 840 841 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 842 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 843 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 844 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 845 846 847 /* Description RSSI_EXT160_2_CHAIN2 848 849 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 850 bandwidth. 851 Value of 0x80 indicates invalid. 852 */ 853 854 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 855 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 856 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 857 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 858 859 860 /* Description RSSI_EXT160_3_CHAIN2 861 862 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 863 bandwidth. 864 Value of 0x80 indicates invalid. 865 */ 866 867 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 868 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 869 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 870 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 871 872 873 /* Description RSSI_EXT160_4_CHAIN2 874 875 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 876 bandwidth. 877 Value of 0x80 indicates invalid. 878 */ 879 880 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 881 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 882 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 883 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff 884 885 886 /* Description RSSI_EXT160_5_CHAIN2 887 888 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 889 bandwidth. 890 Value of 0x80 indicates invalid. 891 */ 892 893 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 894 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 895 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 896 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 897 898 899 /* Description RSSI_EXT160_6_CHAIN2 900 901 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 902 bandwidth. 903 Value of 0x80 indicates invalid. 904 */ 905 906 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 907 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 908 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 909 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 910 911 912 /* Description RSSI_EXT160_7_CHAIN2 913 914 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 915 bandwidth. 916 Value of 0x80 indicates invalid. 917 */ 918 919 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 920 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 921 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 922 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 923 924 925 /* Description RSSI_PRI20_CHAIN3 926 927 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 928 929 Value of 0x80 indicates invalid. 930 */ 931 932 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 933 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 934 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 935 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 936 937 938 /* Description RSSI_EXT20_CHAIN3 939 940 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 941 942 Value of 0x80 indicates invalid. 943 */ 944 945 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 946 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 947 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 948 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 949 950 951 /* Description RSSI_EXT40_LOW20_CHAIN3 952 953 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 954 955 Value of 0x80 indicates invalid. 956 */ 957 958 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 959 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 960 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 961 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 962 963 964 /* Description RSSI_EXT40_HIGH20_CHAIN3 965 966 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 967 bandwidth. 968 Value of 0x80 indicates invalid. 969 */ 970 971 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 972 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 973 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 974 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 975 976 977 /* Description RSSI_EXT80_LOW20_CHAIN3 978 979 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 980 981 Value of 0x80 indicates invalid. 982 */ 983 984 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c 985 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 986 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 987 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 988 989 990 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 991 992 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 993 MHz bandwidth. 994 Value of 0x80 indicates invalid. 995 */ 996 997 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c 998 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 999 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 1000 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1001 1002 1003 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 1004 1005 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1006 MHz bandwidth. 1007 Value of 0x80 indicates invalid. 1008 */ 1009 1010 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c 1011 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1012 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 1013 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1014 1015 1016 /* Description RSSI_EXT80_HIGH20_CHAIN3 1017 1018 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1019 bandwidth. 1020 Value of 0x80 indicates invalid. 1021 */ 1022 1023 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c 1024 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1025 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 1026 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1027 1028 1029 /* Description RSSI_EXT160_0_CHAIN3 1030 1031 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1032 bandwidth. 1033 Value of 0x80 indicates invalid. 1034 */ 1035 1036 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 1037 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1038 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1039 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff 1040 1041 1042 /* Description RSSI_EXT160_1_CHAIN3 1043 1044 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1045 bandwidth. 1046 Value of 0x80 indicates invalid. 1047 */ 1048 1049 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 1050 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1051 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1052 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 1053 1054 1055 /* Description RSSI_EXT160_2_CHAIN3 1056 1057 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1058 bandwidth. 1059 Value of 0x80 indicates invalid. 1060 */ 1061 1062 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 1063 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1064 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1065 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 1066 1067 1068 /* Description RSSI_EXT160_3_CHAIN3 1069 1070 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1071 bandwidth. 1072 Value of 0x80 indicates invalid. 1073 */ 1074 1075 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 1076 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1077 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1078 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 1079 1080 1081 /* Description RSSI_EXT160_4_CHAIN3 1082 1083 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1084 bandwidth. 1085 Value of 0x80 indicates invalid. 1086 */ 1087 1088 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 1089 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 1090 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 1091 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff 1092 1093 1094 /* Description RSSI_EXT160_5_CHAIN3 1095 1096 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1097 bandwidth. 1098 Value of 0x80 indicates invalid. 1099 */ 1100 1101 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 1102 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 1103 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 1104 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 1105 1106 1107 /* Description RSSI_EXT160_6_CHAIN3 1108 1109 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1110 bandwidth. 1111 Value of 0x80 indicates invalid. 1112 */ 1113 1114 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 1115 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 1116 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 1117 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 1118 1119 1120 /* Description RSSI_EXT160_7_CHAIN3 1121 1122 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1123 MHz bandwidth. 1124 Value of 0x80 indicates invalid. 1125 */ 1126 1127 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 1128 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 1129 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 1130 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 1131 1132 1133 /* Description PHY_SW_STATUS_31_0 1134 1135 Some PHY micro code status that can be put in here. Details 1136 of definition within SW specification 1137 This field can be used for debugging, FW - SW message exchange, 1138 etc. 1139 It could for example be a pointer to a DDR memory location 1140 where PHY FW put some debug info. 1141 <legal all> 1142 */ 1143 1144 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 1145 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 1146 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 1147 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff 1148 1149 1150 /* Description PHY_SW_STATUS_63_32 1151 1152 Some PHY micro code status that can be put in here. Details 1153 of definition within SW specification 1154 This field can be used for debugging, FW - SW message exchange, 1155 etc. 1156 It could for example be a pointer to a DDR memory location 1157 where PHY FW put some debug info. 1158 <legal all> 1159 */ 1160 1161 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c 1162 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 1163 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 1164 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff 1165 1166 1167 1168 #endif // PHYRX_PKT_END_INFO 1169