1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MON_INGRESS_RING_H_ 27 #define _MON_INGRESS_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "buffer_addr_info.h" 32 #define NUM_OF_DWORDS_MON_INGRESS_RING 4 33 34 35 struct mon_ingress_ring { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct buffer_addr_info buffer_addr_info_details; 38 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 39 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 40 #else 41 struct buffer_addr_info buffer_addr_info_details; 42 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 43 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 44 #endif 45 }; 46 47 48 /* Description BUFFER_ADDR_INFO_DETAILS 49 50 Consumer: TXMON/RXMON 51 Producer: SW 52 53 Details of the physical address of the buffer 54 55 'Sw_buffer_cookie' and 'Return_buffer_manager' sub-fields 56 are reserved and unused by TXMON/RXMON. 57 */ 58 59 60 /* Description BUFFER_ADDR_31_0 61 62 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 63 descriptor OR Link Descriptor 64 65 In case of 'NULL' pointer, this field is set to 0 66 <legal all> 67 */ 68 69 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 70 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 71 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 72 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 73 74 75 /* Description BUFFER_ADDR_39_32 76 77 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 78 descriptor OR Link Descriptor 79 80 In case of 'NULL' pointer, this field is set to 0 81 <legal all> 82 */ 83 84 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 85 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 86 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 87 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 88 89 90 /* Description RETURN_BUFFER_MANAGER 91 92 Consumer: WBM 93 Producer: SW/FW 94 95 In case of 'NULL' pointer, this field is set to 0 96 97 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 98 descriptor OR link descriptor that is being pointed to 99 shall be returned after the frame has been processed. It 100 is used by WBM for routing purposes. 101 102 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 103 to the WMB buffer idle list 104 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 105 to the WBM idle link descriptor idle list, where the chip 106 0 WBM is chosen in case of a multi-chip config 107 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 108 to the chip 1 WBM idle link descriptor idle list 109 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 110 to the chip 2 WBM idle link descriptor idle list 111 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 112 returned to chip 3 WBM idle link descriptor idle list 113 <enum 4 FW_BM> This buffer shall be returned to the FW 114 <enum 5 SW0_BM> This buffer shall be returned to the SW, 115 ring 0 116 <enum 6 SW1_BM> This buffer shall be returned to the SW, 117 ring 1 118 <enum 7 SW2_BM> This buffer shall be returned to the SW, 119 ring 2 120 <enum 8 SW3_BM> This buffer shall be returned to the SW, 121 ring 3 122 <enum 9 SW4_BM> This buffer shall be returned to the SW, 123 ring 4 124 <enum 10 SW5_BM> This buffer shall be returned to the SW, 125 ring 5 126 <enum 11 SW6_BM> This buffer shall be returned to the SW, 127 ring 6 128 129 <legal 0-12> 130 */ 131 132 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 133 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 134 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 135 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 136 137 138 /* Description SW_BUFFER_COOKIE 139 140 Cookie field exclusively used by SW. 141 142 In case of 'NULL' pointer, this field is set to 0 143 144 HW ignores the contents, accept that it passes the programmed 145 value on to other descriptors together with the physical 146 address 147 148 Field can be used by SW to for example associate the buffers 149 physical address with the virtual address 150 The bit definitions as used by SW are within SW HLD specification 151 152 153 NOTE1: 154 The three most significant bits can have a special meaning 155 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 156 and field transmit_bw_restriction is set 157 158 In case of NON punctured transmission: 159 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 160 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 161 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 162 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 163 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 164 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 165 Sw_buffer_cookie[19:18] = 2'b11: reserved 166 167 In case of punctured transmission: 168 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 169 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 170 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 171 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 172 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 173 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 174 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 175 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 176 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 177 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 178 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 179 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 180 Sw_buffer_cookie[19:18] = 2'b11: reserved 181 182 Note: a punctured transmission is indicated by the presence 183 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 184 185 <legal all> 186 */ 187 188 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 189 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 190 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 191 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 192 193 194 /* Description BUFFER_VIRT_ADDR_31_0 195 196 Lower 32 bits of the 64-bit virtual address corresponding 197 to Buffer_addr_info_details 198 <legal all> 199 */ 200 201 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 202 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 203 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 204 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 205 206 207 /* Description BUFFER_VIRT_ADDR_63_32 208 209 Upper 32 bits of the 64-bit virtual address corresponding 210 to Buffer_addr_info_details 211 <legal all> 212 */ 213 214 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 215 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 216 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 217 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 218 219 220 221 #endif // MON_INGRESS_RING 222