1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _COEX_RX_STATUS_H_ 27 #define _COEX_RX_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_COEX_RX_STATUS 2 32 33 #define NUM_OF_QWORDS_COEX_RX_STATUS 1 34 35 36 struct coex_rx_status { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rx_mac_frame_status : 2, // [1:0] 39 rx_with_tx_response : 1, // [2:2] 40 rx_rate : 5, // [7:3] 41 rx_bw : 3, // [10:8] 42 single_mpdu : 1, // [11:11] 43 filter_status : 1, // [12:12] 44 ampdu : 1, // [13:13] 45 directed : 1, // [14:14] 46 reserved_0 : 1, // [15:15] 47 rx_nss : 3, // [18:16] 48 rx_rssi : 8, // [26:19] 49 rx_type : 3, // [29:27] 50 retry_bit_setting : 1, // [30:30] 51 more_data_bit_setting : 1; // [31:31] 52 uint32_t remain_rx_packet_time : 16, // [15:0] 53 rx_remaining_fes_time : 16; // [31:16] 54 #else 55 uint32_t more_data_bit_setting : 1, // [31:31] 56 retry_bit_setting : 1, // [30:30] 57 rx_type : 3, // [29:27] 58 rx_rssi : 8, // [26:19] 59 rx_nss : 3, // [18:16] 60 reserved_0 : 1, // [15:15] 61 directed : 1, // [14:14] 62 ampdu : 1, // [13:13] 63 filter_status : 1, // [12:12] 64 single_mpdu : 1, // [11:11] 65 rx_bw : 3, // [10:8] 66 rx_rate : 5, // [7:3] 67 rx_with_tx_response : 1, // [2:2] 68 rx_mac_frame_status : 2; // [1:0] 69 uint32_t rx_remaining_fes_time : 16, // [31:16] 70 remain_rx_packet_time : 16; // [15:0] 71 #endif 72 }; 73 74 75 /* Description RX_MAC_FRAME_STATUS 76 77 RXPCU send this bit as 1 when it receives the begin of a 78 frame from PHY, and it passes the address filter. RXPCUsend 79 this bit as 0 when the frame ends. (on/off bit) 80 <enum 0 ppdu_start> start of PPDU reception. 81 For SU: Generated the first time the MPDU header passes 82 the address filter and is destined to this STA. 83 For MU: Generated the first time the MPDU header from any 84 user passes the address filter and is destined to this 85 STA. 86 <enum 1 first_mpdu_FCS_pass> message only sent in case 87 of A-MPDU reception. 88 For SU: first time the FCS of an MPDU passes (and frame 89 is destined to this device) 90 For MU: first time the FCS of any MPDU passes (and frame 91 is destined to this device) 92 93 <enum 2 ppdu_end> receive of PPDU frame reception has 94 finished 95 <enum 3 ppdu_end_due_to_phy_nap> receive of PPDU frame reception 96 has finished as it has been aborted due to PHY NAP generation 97 98 <legal all> 99 */ 100 101 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 102 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 103 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 104 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 105 106 107 /* Description RX_WITH_TX_RESPONSE 108 109 Field only valid when rx_mac_frame_status is first_mpdu_FCS_pass 110 or ppdu_end. 111 112 For SU: RXPCU set this bit to indicate it is expecting the 113 TX to send a response after the receive. 114 For MU: RXPCU set this bit to indicate it is expecting that 115 at least for one of the users a response after the reception 116 needs to be generated. 117 118 <legal all> 119 */ 120 121 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 122 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 123 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 124 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 125 126 127 /* Description RX_RATE 128 129 For SU: RXPCU send the current receive rate at the beginning 130 of receive when rate is available from PHY. 131 For MU: RXPCU to use the current receive rate from the first 132 USER that triggers this TLV to be generated. 133 134 Field is always valid 135 136 <legal all> 137 */ 138 139 #define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 140 #define COEX_RX_STATUS_RX_RATE_LSB 3 141 #define COEX_RX_STATUS_RX_RATE_MSB 7 142 #define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 143 144 145 /* Description RX_BW 146 147 Actual RX bandwidth. Not SU or MU dependent. 148 RXPCU send the current receive rate at the beginning of 149 receive. This information is from PHY. 150 Field is always valid 151 152 <enum 0 20_mhz>20 Mhz BW 153 <enum 1 40_mhz>40 Mhz BW 154 <enum 2 80_mhz>80 Mhz BW 155 <enum 3 160_mhz>160 Mhz BW 156 <enum 4 320_mhz>320 Mhz BW 157 <enum 5 240_mhz>240 Mhz BW 158 */ 159 160 #define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 161 #define COEX_RX_STATUS_RX_BW_LSB 8 162 #define COEX_RX_STATUS_RX_BW_MSB 10 163 #define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 164 165 166 /* Description SINGLE_MPDU 167 168 For SU: Once set the Received frame is a single MPDU. This 169 can be a non-AMPDU reception or A-MPDU reception but with 170 an EOF bit set (VHT single AMPDU). 171 For MU: RXPCU to base this on the first USER that triggers 172 this TLV to be generated. 173 <legal all> 174 */ 175 176 #define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 177 #define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 178 #define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 179 #define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 180 181 182 /* Description FILTER_STATUS 183 184 1: LMAC is interested in receiving the full packet and forward 185 it to downstream modules. 0: LMAC is not interested in 186 receiving the packet. 187 188 In HastingsPrime based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' 189 Rx PCU will send this TLV for filtered-out packets as well, 190 with appropriate info in the fields filter_status, AMPDU 191 and Directed. Otherwise, and in other chips, this TLV is 192 sent only for packets filtered in, with these fields set 193 to zero. 194 <legal all> 195 */ 196 197 #define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 198 #define COEX_RX_STATUS_FILTER_STATUS_LSB 12 199 #define COEX_RX_STATUS_FILTER_STATUS_MSB 12 200 #define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 201 202 203 /* Description AMPDU 204 205 1: Indicates received frame is an AMPDU0: indicates received 206 frames in not an AMPDU 207 208 In HastingsPrime based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' 209 Rx PCU will send this TLV for filtered-out packets as well, 210 with appropriate info in the fields filter_status, AMPDU 211 and Directed. Otherwise, and in other chips, this TLV is 212 sent only for packets filtered in, with these fields set 213 to zero. 214 <legal all> 215 */ 216 217 #define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 218 #define COEX_RX_STATUS_AMPDU_LSB 13 219 #define COEX_RX_STATUS_AMPDU_MSB 13 220 #define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 221 222 223 /* Description DIRECTED 224 225 1: indicates AD1 matches our Receiver address0: indicates 226 AD1 does not match our Receiver address 227 228 In HastingsPrime based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' 229 Rx PCU will send this TLV for filtered-out packets as well, 230 with appropriate info in the fields filter_status, AMPDU 231 and Directed. Otherwise, and in other chips, this TLV is 232 sent only for packets filtered in, with these fields set 233 to zero. 234 <legal all> 235 */ 236 237 #define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 238 #define COEX_RX_STATUS_DIRECTED_LSB 14 239 #define COEX_RX_STATUS_DIRECTED_MSB 14 240 #define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 241 242 243 /* Description RESERVED_0 244 245 <legal 0> 246 */ 247 248 #define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 249 #define COEX_RX_STATUS_RESERVED_0_LSB 15 250 #define COEX_RX_STATUS_RESERVED_0_MSB 15 251 #define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 252 253 254 /* Description RX_NSS 255 256 For SU: Number of spatial streams in the reception. Field 257 is always valid 258 For MU: RXPCU to base this on the first USER that triggers 259 this TLV to be generated. 260 261 <enum 0 1_spatial_stream>Single spatial stream 262 <enum 1 2_spatial_streams>2 spatial streams 263 <enum 2 3_spatial_streams>3 spatial streams 264 <enum 3 4_spatial_streams>4 spatial streams 265 <enum 4 5_spatial_streams>5 spatial streams 266 <enum 5 6_spatial_streams>6 spatial streams 267 <enum 6 7_spatial_streams>7 spatial streams 268 <enum 7 8_spatial_streams>8 spatial streams 269 */ 270 271 #define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 272 #define COEX_RX_STATUS_RX_NSS_LSB 16 273 #define COEX_RX_STATUS_RX_NSS_MSB 18 274 #define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 275 276 277 /* Description RX_RSSI 278 279 RXPCU send the current receive RSSI (from the PHYRX_RSSI_LEGACY 280 TLV) at the beginning of reception. This is information 281 is from PHY and is not SU or MU dependent. 282 Field is always valid 283 <legal all> 284 */ 285 286 #define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 287 #define COEX_RX_STATUS_RX_RSSI_LSB 19 288 #define COEX_RX_STATUS_RX_RSSI_MSB 26 289 #define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 290 291 292 /* Description RX_TYPE 293 294 For SU: RXPCU send the current receive packet type. Field 295 is always valid.This info is from MAC. 296 For MU: RXPCU to base this on the first USER that triggers 297 this TLV to be generated. 298 299 <enum 0 data > 300 <enum 1 management> 301 <enum 2 beacon> 302 <enum 3 control> For reception of RTS frame 303 <enum 4 control_response> For reception of CTS, ACK 304 or BA frames 305 <enum 5 others> 306 <legal 0-5> 307 */ 308 309 #define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 310 #define COEX_RX_STATUS_RX_TYPE_LSB 27 311 #define COEX_RX_STATUS_RX_TYPE_MSB 29 312 #define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 313 314 315 /* Description RETRY_BIT_SETTING 316 317 For SU: Value of the retry bit in the frame control field 318 of the first MPDU MAC header that passes the RxPCU frame 319 filter 320 For MU: RXPCU to base this on the first USER that triggers 321 this TLV to be generated. 322 323 <legal all> 324 */ 325 326 #define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 327 #define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 328 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 329 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 330 331 332 /* Description MORE_DATA_BIT_SETTING 333 334 For SU: Value of the more data bit in the frame control 335 field of the first MPDU MAC header that passes the RxPCU 336 frame filter 337 For MU: RXPCU to base this on the first USER that triggers 338 this TLV to be generated. 339 340 <legal all> 341 */ 342 343 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 344 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 345 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 346 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 347 348 349 /* Description REMAIN_RX_PACKET_TIME 350 351 HWSCH sends current remaining rx PPDU frame time. This time 352 covers the entire rx_frame. This information is not in 353 the L-SIG and we expect to get it from PHY at the start 354 of the reception. 355 This is not SU or MU dependent. 356 <legal all> 357 */ 358 359 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 360 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 361 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 362 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 363 364 365 /* Description RX_REMAINING_FES_TIME 366 367 RXPCU sends the remaining time FES time the moment a frame 368 with proper FCS is received. The time indicated is the 369 remaining rx packet time with the duration field value added. 370 As long as no frame with valid FCS is received, this field 371 should be set equal to 'remain_rx_packet_time' 372 This is not SU or MU dependent. 373 <legal all> 374 */ 375 376 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 377 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 378 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 379 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 380 381 382 383 #endif // COEX_RX_STATUS 384