1 /*
2  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _RX_MSDU_DESC_INFO_H_
18 #define _RX_MSDU_DESC_INFO_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 
23 // ################ START SUMMARY #################
24 //
25 //	Dword	Fields
26 //	0	first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], l3_header_padding_msb[28], tcp_udp_chksum_fail[29], ip_chksum_fail[30], raw_mpdu[31]
27 //	1	sa_idx_or_sw_peer_id_14_0[14:0], mpdu_ast_idx_or_sw_peer_id_14_0[29:15], fr_ds[30], to_ds[31]
28 //
29 // ################ END SUMMARY #################
30 
31 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
32 
33 struct rx_msdu_desc_info {
34              uint32_t first_msdu_in_mpdu_flag         :  1, //[0]
35                       last_msdu_in_mpdu_flag          :  1, //[1]
36                       msdu_continuation               :  1, //[2]
37                       msdu_length                     : 14, //[16:3]
38                       reo_destination_indication      :  5, //[21:17]
39                       msdu_drop                       :  1, //[22]
40                       sa_is_valid                     :  1, //[23]
41                       sa_idx_timeout                  :  1, //[24]
42                       da_is_valid                     :  1, //[25]
43                       da_is_mcbc                      :  1, //[26]
44                       da_idx_timeout                  :  1, //[27]
45                       l3_header_padding_msb           :  1, //[28]
46                       tcp_udp_chksum_fail             :  1, //[29]
47                       ip_chksum_fail                  :  1, //[30]
48                       raw_mpdu                        :  1; //[31]
49              uint32_t sa_idx_or_sw_peer_id_14_0       : 15, //[14:0]
50                       mpdu_ast_idx_or_sw_peer_id_14_0 : 15, //[29:15]
51                       fr_ds                           :  1, //[30]
52                       to_ds                           :  1; //[31]
53 };
54 
55 /*
56 
57 first_msdu_in_mpdu_flag
58 
59 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
60 			over multiple buffers, this field will be valid in the Last
61 			buffer used by the MSDU
62 
63 
64 
65 			<enum 0 Not_first_msdu> This is not the first MSDU in
66 			the MPDU.
67 
68 			<enum 1 first_msdu> This MSDU is the first one in the
69 			MPDU.
70 
71 
72 
73 			<legal all>
74 
75 last_msdu_in_mpdu_flag
76 
77 			Consumer: WBM/REO/SW/FW
78 
79 			Producer: RXDMA
80 
81 
82 
83 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
84 			over multiple buffers, this field will be valid in the Last
85 			buffer used by the MSDU
86 
87 
88 
89 			<enum 0 Not_last_msdu> There are more MSDUs linked to
90 			this MSDU that belongs to this MPDU
91 
92 			<enum 1 Last_msdu> this MSDU is the last one in the
93 			MPDU. This setting is only allowed in combination with
94 			'Msdu_continuation' set to 0. This implies that when an msdu
95 			is spread out over multiple buffers and thus
96 			msdu_continuation is set, only for the very last buffer of
97 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
98 
99 
100 
101 			When both first_msdu_in_mpdu_flag and
102 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
103 			belongs to only contains a single MSDU.
104 
105 
106 
107 
108 
109 			<legal all>
110 
111 msdu_continuation
112 
113 			When set, this MSDU buffer was not able to hold the
114 			entire MSDU. The next buffer will therefor contain
115 			additional information related to this MSDU.
116 
117 
118 
119 			<legal all>
120 
121 msdu_length
122 
123 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
124 			over multiple buffers, this field will be valid in the First
125 			buffer used by MSDU.
126 
127 
128 
129 			Full MSDU length in bytes after decapsulation.
130 
131 
132 
133 			This field is still valid for MPDU frames without
134 			A-MSDU.  It still represents MSDU length after decapsulation
135 
136 
137 
138 			Or in case of RAW MPDUs, it indicates the length of the
139 			entire MPDU (without FCS field)
140 
141 			<legal all>
142 
143 reo_destination_indication
144 
145 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
146 			over multiple buffers, this field will be valid in the Last
147 			buffer used by the MSDU
148 
149 
150 
151 			The ID of the REO exit ring where the MSDU frame shall
152 			push after (MPDU level) reordering has finished.
153 
154 
155 
156 			<enum 0 reo_destination_tcl> Reo will push the frame
157 			into the REO2TCL ring
158 
159 			<enum 1 reo_destination_sw1> Reo will push the frame
160 			into the REO2SW1 ring
161 
162 			<enum 2 reo_destination_sw2> Reo will push the frame
163 			into the REO2SW2 ring
164 
165 			<enum 3 reo_destination_sw3> Reo will push the frame
166 			into the REO2SW3 ring
167 
168 			<enum 4 reo_destination_sw4> Reo will push the frame
169 			into the REO2SW4 ring
170 
171 			<enum 5 reo_destination_release> Reo will push the frame
172 			into the REO_release ring
173 
174 			<enum 6 reo_destination_fw> Reo will push the frame into
175 			the REO2FW ring
176 
177 			<enum 7 reo_destination_sw5> Reo will push the frame
178 			into the REO2SW5 ring (REO remaps this in chips without
179 			REO2SW5 ring, e.g. Pine)
180 
181 			<enum 8 reo_destination_sw6> Reo will push the frame
182 			into the REO2SW6 ring (REO remaps this in chips without
183 			REO2SW6 ring, e.g. Pine)
184 
185 			 <enum 9 reo_destination_9> REO remaps this <enum 10
186 			reo_destination_10> REO remaps this
187 
188 			<enum 11 reo_destination_11> REO remaps this
189 
190 			<enum 12 reo_destination_12> REO remaps this <enum 13
191 			reo_destination_13> REO remaps this
192 
193 			<enum 14 reo_destination_14> REO remaps this
194 
195 			<enum 15 reo_destination_15> REO remaps this
196 
197 			<enum 16 reo_destination_16> REO remaps this
198 
199 			<enum 17 reo_destination_17> REO remaps this
200 
201 			<enum 18 reo_destination_18> REO remaps this
202 
203 			<enum 19 reo_destination_19> REO remaps this
204 
205 			<enum 20 reo_destination_20> REO remaps this
206 
207 			<enum 21 reo_destination_21> REO remaps this
208 
209 			<enum 22 reo_destination_22> REO remaps this
210 
211 			<enum 23 reo_destination_23> REO remaps this
212 
213 			<enum 24 reo_destination_24> REO remaps this
214 
215 			<enum 25 reo_destination_25> REO remaps this
216 
217 			<enum 26 reo_destination_26> REO remaps this
218 
219 			<enum 27 reo_destination_27> REO remaps this
220 
221 			<enum 28 reo_destination_28> REO remaps this
222 
223 			<enum 29 reo_destination_29> REO remaps this
224 
225 			<enum 30 reo_destination_30> REO remaps this
226 
227 			<enum 31 reo_destination_31> REO remaps this
228 
229 
230 
231 			<legal all>
232 
233 msdu_drop
234 
235 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
236 			over multiple buffers, this field will be valid in the Last
237 			buffer used by the MSDU
238 
239 
240 
241 			When set, REO shall drop this MSDU and not forward it to
242 			any other ring...
243 
244 			<legal all>
245 
246 sa_is_valid
247 
248 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
249 			over multiple buffers, this field will be valid in the Last
250 			buffer used by the MSDU
251 
252 
253 
254 			Indicates that OLE found a valid SA entry for this MSDU
255 
256 			<legal all>
257 
258 sa_idx_timeout
259 
260 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
261 			over multiple buffers, this field will be valid in the Last
262 			buffer used by the MSDU
263 
264 
265 
266 			Indicates an unsuccessful MAC source address search due
267 			to the expiring of the search timer for this MSDU
268 
269 			<legal all>
270 
271 da_is_valid
272 
273 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
274 			over multiple buffers, this field will be valid in the Last
275 			buffer used by the MSDU
276 
277 
278 
279 			Indicates that OLE found a valid DA entry for this MSDU
280 
281 			<legal all>
282 
283 da_is_mcbc
284 
285 			Field Only valid if da_is_valid is set
286 
287 
288 
289 			Indicates the DA address was a Multicast of Broadcast
290 			address for this MSDU
291 
292 			<legal all>
293 
294 da_idx_timeout
295 
296 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
297 			over multiple buffers, this field will be valid in the Last
298 			buffer used by the MSDU
299 
300 
301 
302 			Indicates an unsuccessful MAC destination address search
303 			due to the expiring of the search timer for this MSDU
304 
305 			<legal all>
306 
307 l3_header_padding_msb
308 
309 			Passed on from 'RX_MSDU_END' TLV (only the MSB is
310 			reported as the LSB is always zero)
311 
312 			Number of bytes padded to make sure that the L3 header
313 			will always start of a Dword boundary
314 
315 			<legal all>
316 
317 tcp_udp_chksum_fail
318 
319 			Passed on from 'RX_ATTENTION' TLV
320 
321 			Indicates that the computed checksum did not match the
322 			checksum in the TCP/UDP header.
323 
324 			<legal all>
325 
326 ip_chksum_fail
327 
328 			Passed on from 'RX_ATTENTION' TLV
329 
330 			Indicates that the computed checksum did not match the
331 			checksum in the IP header.
332 
333 			<legal all>
334 
335 raw_mpdu
336 
337 			Passed on from 'RX_MPDU_INFO' structure in
338 			'RX_MPDU_START' TLV
339 
340 			Set to 1 by RXOLE when it has not performed any 802.11
341 			to Ethernet/Natvie WiFi header conversion on this MPDU.
342 
343 			<legal all>
344 
345 sa_idx_or_sw_peer_id_14_0
346 
347 			Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
348 
349 			Based on a register configuration in RXDMA, this field
350 			will contain:
351 
352 			The offset in the address search table which matches the
353 			MAC source address
354 
355 			OR
356 
357 
358 
359 			'sw_peer_id' from the address search entry corresponding
360 			to the source address of the MSDU
361 
362 			<legal all>
363 
364 mpdu_ast_idx_or_sw_peer_id_14_0
365 
366 			Passed on from 'RX_MPDU_INFO' structure in
367 			'RX_MPDU_START' TLV (one MSB is omitted)
368 
369 
370 
371 			Based on a register configuration in RXDMA, this field
372 			will contain:
373 
374 			The index of the address search entry corresponding to
375 			this MPDU (a value of 0xFFFF indicates an invalid AST index,
376 			meaning that no AST entry was found or no AST search was
377 			performed)
378 
379 
380 
381 			OR:
382 
383 
384 
385 			'sw_peer_id' from the address search entry corresponding
386 			to this MPDU (in case of ndp or phy_err or
387 			AST_based_lookup_valid == 0, this field will be set to 0)
388 
389 			<legal all>
390 
391 fr_ds
392 
393 			Passed on from 'RX_MPDU_INFO' structure in
394 			'RX_MPDU_START' TLV
395 
396 			Set if the 'from DS' bit is set in the frame control.
397 
398 			<legal all>
399 
400 to_ds
401 
402 			Passed on from 'RX_MPDU_INFO' structure in
403 			'RX_MPDU_START' TLV
404 
405 			Set if the 'to DS' bit is set in the frame control.
406 
407 			<legal all>
408 */
409 
410 
411 /* Description		RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG
412 
413 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
414 			over multiple buffers, this field will be valid in the Last
415 			buffer used by the MSDU
416 
417 
418 
419 			<enum 0 Not_first_msdu> This is not the first MSDU in
420 			the MPDU.
421 
422 			<enum 1 first_msdu> This MSDU is the first one in the
423 			MPDU.
424 
425 
426 
427 			<legal all>
428 */
429 #define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET           0x00000000
430 #define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB              0
431 #define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK             0x00000001
432 
433 /* Description		RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG
434 
435 			Consumer: WBM/REO/SW/FW
436 
437 			Producer: RXDMA
438 
439 
440 
441 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
442 			over multiple buffers, this field will be valid in the Last
443 			buffer used by the MSDU
444 
445 
446 
447 			<enum 0 Not_last_msdu> There are more MSDUs linked to
448 			this MSDU that belongs to this MPDU
449 
450 			<enum 1 Last_msdu> this MSDU is the last one in the
451 			MPDU. This setting is only allowed in combination with
452 			'Msdu_continuation' set to 0. This implies that when an msdu
453 			is spread out over multiple buffers and thus
454 			msdu_continuation is set, only for the very last buffer of
455 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
456 
457 
458 
459 			When both first_msdu_in_mpdu_flag and
460 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
461 			belongs to only contains a single MSDU.
462 
463 
464 
465 
466 
467 			<legal all>
468 */
469 #define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET            0x00000000
470 #define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB               1
471 #define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK              0x00000002
472 
473 /* Description		RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION
474 
475 			When set, this MSDU buffer was not able to hold the
476 			entire MSDU. The next buffer will therefor contain
477 			additional information related to this MSDU.
478 
479 
480 
481 			<legal all>
482 */
483 #define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET                 0x00000000
484 #define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB                    2
485 #define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK                   0x00000004
486 
487 /* Description		RX_MSDU_DESC_INFO_0_MSDU_LENGTH
488 
489 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
490 			over multiple buffers, this field will be valid in the First
491 			buffer used by MSDU.
492 
493 
494 
495 			Full MSDU length in bytes after decapsulation.
496 
497 
498 
499 			This field is still valid for MPDU frames without
500 			A-MSDU.  It still represents MSDU length after decapsulation
501 
502 
503 
504 			Or in case of RAW MPDUs, it indicates the length of the
505 			entire MPDU (without FCS field)
506 
507 			<legal all>
508 */
509 #define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET                       0x00000000
510 #define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB                          3
511 #define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK                         0x0001fff8
512 
513 /* Description		RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION
514 
515 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
516 			over multiple buffers, this field will be valid in the Last
517 			buffer used by the MSDU
518 
519 
520 
521 			The ID of the REO exit ring where the MSDU frame shall
522 			push after (MPDU level) reordering has finished.
523 
524 
525 
526 			<enum 0 reo_destination_tcl> Reo will push the frame
527 			into the REO2TCL ring
528 
529 			<enum 1 reo_destination_sw1> Reo will push the frame
530 			into the REO2SW1 ring
531 
532 			<enum 2 reo_destination_sw2> Reo will push the frame
533 			into the REO2SW2 ring
534 
535 			<enum 3 reo_destination_sw3> Reo will push the frame
536 			into the REO2SW3 ring
537 
538 			<enum 4 reo_destination_sw4> Reo will push the frame
539 			into the REO2SW4 ring
540 
541 			<enum 5 reo_destination_release> Reo will push the frame
542 			into the REO_release ring
543 
544 			<enum 6 reo_destination_fw> Reo will push the frame into
545 			the REO2FW ring
546 
547 			<enum 7 reo_destination_sw5> Reo will push the frame
548 			into the REO2SW5 ring (REO remaps this in chips without
549 			REO2SW5 ring, e.g. Pine)
550 
551 			<enum 8 reo_destination_sw6> Reo will push the frame
552 			into the REO2SW6 ring (REO remaps this in chips without
553 			REO2SW6 ring, e.g. Pine)
554 
555 			 <enum 9 reo_destination_9> REO remaps this <enum 10
556 			reo_destination_10> REO remaps this
557 
558 			<enum 11 reo_destination_11> REO remaps this
559 
560 			<enum 12 reo_destination_12> REO remaps this <enum 13
561 			reo_destination_13> REO remaps this
562 
563 			<enum 14 reo_destination_14> REO remaps this
564 
565 			<enum 15 reo_destination_15> REO remaps this
566 
567 			<enum 16 reo_destination_16> REO remaps this
568 
569 			<enum 17 reo_destination_17> REO remaps this
570 
571 			<enum 18 reo_destination_18> REO remaps this
572 
573 			<enum 19 reo_destination_19> REO remaps this
574 
575 			<enum 20 reo_destination_20> REO remaps this
576 
577 			<enum 21 reo_destination_21> REO remaps this
578 
579 			<enum 22 reo_destination_22> REO remaps this
580 
581 			<enum 23 reo_destination_23> REO remaps this
582 
583 			<enum 24 reo_destination_24> REO remaps this
584 
585 			<enum 25 reo_destination_25> REO remaps this
586 
587 			<enum 26 reo_destination_26> REO remaps this
588 
589 			<enum 27 reo_destination_27> REO remaps this
590 
591 			<enum 28 reo_destination_28> REO remaps this
592 
593 			<enum 29 reo_destination_29> REO remaps this
594 
595 			<enum 30 reo_destination_30> REO remaps this
596 
597 			<enum 31 reo_destination_31> REO remaps this
598 
599 
600 
601 			<legal all>
602 */
603 #define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET        0x00000000
604 #define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB           17
605 #define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK          0x003e0000
606 
607 /* Description		RX_MSDU_DESC_INFO_0_MSDU_DROP
608 
609 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
610 			over multiple buffers, this field will be valid in the Last
611 			buffer used by the MSDU
612 
613 
614 
615 			When set, REO shall drop this MSDU and not forward it to
616 			any other ring...
617 
618 			<legal all>
619 */
620 #define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET                         0x00000000
621 #define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB                            22
622 #define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK                           0x00400000
623 
624 /* Description		RX_MSDU_DESC_INFO_0_SA_IS_VALID
625 
626 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
627 			over multiple buffers, this field will be valid in the Last
628 			buffer used by the MSDU
629 
630 
631 
632 			Indicates that OLE found a valid SA entry for this MSDU
633 
634 			<legal all>
635 */
636 #define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET                       0x00000000
637 #define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB                          23
638 #define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK                         0x00800000
639 
640 /* Description		RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT
641 
642 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
643 			over multiple buffers, this field will be valid in the Last
644 			buffer used by the MSDU
645 
646 
647 
648 			Indicates an unsuccessful MAC source address search due
649 			to the expiring of the search timer for this MSDU
650 
651 			<legal all>
652 */
653 #define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET                    0x00000000
654 #define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB                       24
655 #define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK                      0x01000000
656 
657 /* Description		RX_MSDU_DESC_INFO_0_DA_IS_VALID
658 
659 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
660 			over multiple buffers, this field will be valid in the Last
661 			buffer used by the MSDU
662 
663 
664 
665 			Indicates that OLE found a valid DA entry for this MSDU
666 
667 			<legal all>
668 */
669 #define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET                       0x00000000
670 #define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB                          25
671 #define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK                         0x02000000
672 
673 /* Description		RX_MSDU_DESC_INFO_0_DA_IS_MCBC
674 
675 			Field Only valid if da_is_valid is set
676 
677 
678 
679 			Indicates the DA address was a Multicast of Broadcast
680 			address for this MSDU
681 
682 			<legal all>
683 */
684 #define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET                        0x00000000
685 #define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB                           26
686 #define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK                          0x04000000
687 
688 /* Description		RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT
689 
690 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
691 			over multiple buffers, this field will be valid in the Last
692 			buffer used by the MSDU
693 
694 
695 
696 			Indicates an unsuccessful MAC destination address search
697 			due to the expiring of the search timer for this MSDU
698 
699 			<legal all>
700 */
701 #define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET                    0x00000000
702 #define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB                       27
703 #define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK                      0x08000000
704 
705 /* Description		RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB
706 
707 			Passed on from 'RX_MSDU_END' TLV (only the MSB is
708 			reported as the LSB is always zero)
709 
710 			Number of bytes padded to make sure that the L3 header
711 			will always start of a Dword boundary
712 
713 			<legal all>
714 */
715 #define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET             0x00000000
716 #define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB                28
717 #define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK               0x10000000
718 
719 /* Description		RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL
720 
721 			Passed on from 'RX_ATTENTION' TLV
722 
723 			Indicates that the computed checksum did not match the
724 			checksum in the TCP/UDP header.
725 
726 			<legal all>
727 */
728 #define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET               0x00000000
729 #define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB                  29
730 #define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK                 0x20000000
731 
732 /* Description		RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL
733 
734 			Passed on from 'RX_ATTENTION' TLV
735 
736 			Indicates that the computed checksum did not match the
737 			checksum in the IP header.
738 
739 			<legal all>
740 */
741 #define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET                    0x00000000
742 #define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB                       30
743 #define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK                      0x40000000
744 
745 /* Description		RX_MSDU_DESC_INFO_0_RAW_MPDU
746 
747 			Passed on from 'RX_MPDU_INFO' structure in
748 			'RX_MPDU_START' TLV
749 
750 			Set to 1 by RXOLE when it has not performed any 802.11
751 			to Ethernet/Natvie WiFi header conversion on this MPDU.
752 
753 			<legal all>
754 */
755 #define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET                          0x00000000
756 #define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB                             31
757 #define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK                            0x80000000
758 
759 /* Description		RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0
760 
761 			Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
762 
763 			Based on a register configuration in RXDMA, this field
764 			will contain:
765 
766 			The offset in the address search table which matches the
767 			MAC source address
768 
769 			OR
770 
771 
772 
773 			'sw_peer_id' from the address search entry corresponding
774 			to the source address of the MSDU
775 
776 			<legal all>
777 */
778 #define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET         0x00000004
779 #define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB            0
780 #define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK           0x00007fff
781 
782 /* Description		RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
783 
784 			Passed on from 'RX_MPDU_INFO' structure in
785 			'RX_MPDU_START' TLV (one MSB is omitted)
786 
787 
788 
789 			Based on a register configuration in RXDMA, this field
790 			will contain:
791 
792 			The index of the address search entry corresponding to
793 			this MPDU (a value of 0xFFFF indicates an invalid AST index,
794 			meaning that no AST entry was found or no AST search was
795 			performed)
796 
797 
798 
799 			OR:
800 
801 
802 
803 			'sw_peer_id' from the address search entry corresponding
804 			to this MPDU (in case of ndp or phy_err or
805 			AST_based_lookup_valid == 0, this field will be set to 0)
806 
807 			<legal all>
808 */
809 #define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET   0x00000004
810 #define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB      15
811 #define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK     0x3fff8000
812 
813 /* Description		RX_MSDU_DESC_INFO_1_FR_DS
814 
815 			Passed on from 'RX_MPDU_INFO' structure in
816 			'RX_MPDU_START' TLV
817 
818 			Set if the 'from DS' bit is set in the frame control.
819 
820 			<legal all>
821 */
822 #define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET                             0x00000004
823 #define RX_MSDU_DESC_INFO_1_FR_DS_LSB                                30
824 #define RX_MSDU_DESC_INFO_1_FR_DS_MASK                               0x40000000
825 
826 /* Description		RX_MSDU_DESC_INFO_1_TO_DS
827 
828 			Passed on from 'RX_MPDU_INFO' structure in
829 			'RX_MPDU_START' TLV
830 
831 			Set if the 'to DS' bit is set in the frame control.
832 
833 			<legal all>
834 */
835 #define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET                             0x00000004
836 #define RX_MSDU_DESC_INFO_1_TO_DS_LSB                                31
837 #define RX_MSDU_DESC_INFO_1_TO_DS_MASK                               0x80000000
838 
839 
840 #endif // _RX_MSDU_DESC_INFO_H_
841