1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /////////////////////////////////////////////////////////////////////////////////////////////// 18 // 19 // reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 2/21/2020 20 // User Name:c_landav 21 // 22 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 23 // 24 /////////////////////////////////////////////////////////////////////////////////////////////// 25 26 #ifndef __REO_REG_SEQ_REG_H__ 27 #define __REO_REG_SEQ_REG_H__ 28 29 #include "seq_hwio.h" 30 #include "reo_reg_seq_hwiobase.h" 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 38 /////////////////////////////////////////////////////////////////////////////////////////////// 39 // Register Data for Block REO_REG 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 42 //// Register REO_R0_GENERAL_ENABLE //// 43 44 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) 45 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) 46 #define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xfbffff7f 47 #define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 48 #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ 49 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) 50 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ 51 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 52 #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ 53 out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) 54 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ 55 do {\ 56 HWIO_INTLOCK(); \ 57 out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ 58 HWIO_INTFREE();\ 59 } while (0) 60 61 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 62 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 0x1f 63 64 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 65 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 0x1e 66 67 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 68 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 0x1d 69 70 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 71 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1c 72 73 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x08000000 74 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1b 75 76 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x03800000 77 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x17 78 79 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00400000 80 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x16 81 82 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00200000 83 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x15 84 85 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00100000 86 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x14 87 88 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00080000 89 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x13 90 91 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00040000 92 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x12 93 94 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00020000 95 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x11 96 97 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00010000 98 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0x10 99 100 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00008000 101 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xf 102 103 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00004000 104 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xe 105 106 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00002000 107 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xd 108 109 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00001000 110 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xc 111 112 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000e00 113 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x9 114 115 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000100 116 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x8 117 118 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 119 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 120 121 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 122 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 123 124 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 125 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 126 127 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 128 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 129 130 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 131 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 132 133 //// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// 134 135 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) 136 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) 137 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0x77777777 138 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 0 139 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ 140 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) 141 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ 142 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 143 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ 144 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) 145 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ 146 do {\ 147 HWIO_INTLOCK(); \ 148 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ 149 HWIO_INTFREE();\ 150 } while (0) 151 152 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0x70000000 153 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1c 154 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x07000000 156 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x18 157 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x00700000 159 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x14 160 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00070000 162 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x10 163 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x00007000 165 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0xc 166 167 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x00000700 168 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0x8 169 170 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00000070 171 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0x4 172 173 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000007 174 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x0 175 176 //// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// 177 178 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) 179 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) 180 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0x77777777 181 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 0 182 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ 183 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) 184 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ 185 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 186 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ 187 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) 188 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ 189 do {\ 190 HWIO_INTLOCK(); \ 191 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ 192 HWIO_INTFREE();\ 193 } while (0) 194 195 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0x70000000 196 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1c 197 198 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x07000000 199 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x18 200 201 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x00700000 202 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x14 203 204 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00070000 205 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x10 206 207 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x00007000 208 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0xc 209 210 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x00000700 211 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0x8 212 213 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00000070 214 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0x4 215 216 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000007 217 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x0 218 219 //// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// 220 221 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) 222 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) 223 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0x77777777 224 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 0 225 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ 226 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) 227 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ 228 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 229 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ 230 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) 231 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ 232 do {\ 233 HWIO_INTLOCK(); \ 234 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ 235 HWIO_INTFREE();\ 236 } while (0) 237 238 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0x70000000 239 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1c 240 241 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x07000000 242 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x18 243 244 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x00700000 245 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x14 246 247 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00070000 248 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x10 249 250 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x00007000 251 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0xc 252 253 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x00000700 254 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0x8 255 256 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00000070 257 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0x4 258 259 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000007 260 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x0 261 262 //// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// 263 264 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) 265 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) 266 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0x77777777 267 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 0 268 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ 269 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) 270 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ 271 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 272 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ 273 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) 274 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ 275 do {\ 276 HWIO_INTLOCK(); \ 277 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ 278 HWIO_INTFREE();\ 279 } while (0) 280 281 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0x70000000 282 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1c 283 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x07000000 285 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x18 286 287 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x00700000 288 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x14 289 290 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00070000 291 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x10 292 293 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x00007000 294 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0xc 295 296 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x00000700 297 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0x8 298 299 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00000070 300 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0x4 301 302 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000007 303 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x0 304 305 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// 306 307 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) 308 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) 309 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0x77777777 310 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 0 311 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ 312 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) 313 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ 314 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 315 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ 316 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) 317 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ 318 do {\ 319 HWIO_INTLOCK(); \ 320 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ 321 HWIO_INTFREE();\ 322 } while (0) 323 324 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0x70000000 325 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1c 326 327 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x07000000 328 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x18 329 330 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x00700000 331 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x14 332 333 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00070000 334 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x10 335 336 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x00007000 337 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0xc 338 339 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x00000700 340 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0x8 341 342 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00000070 343 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0x4 344 345 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000007 346 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x0 347 348 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// 349 350 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) 351 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) 352 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0x77777777 353 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 0 354 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ 355 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) 356 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ 357 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 358 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ 359 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) 360 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ 361 do {\ 362 HWIO_INTLOCK(); \ 363 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ 364 HWIO_INTFREE();\ 365 } while (0) 366 367 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0x70000000 368 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1c 369 370 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x07000000 371 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x18 372 373 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x00700000 374 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x14 375 376 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00070000 377 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x10 378 379 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x00007000 380 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0xc 381 382 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x00000700 383 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0x8 384 385 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00000070 386 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0x4 387 388 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000007 389 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x0 390 391 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// 392 393 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) 394 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) 395 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0x77777777 396 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 0 397 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ 398 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) 399 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ 400 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 401 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ 402 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) 403 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ 404 do {\ 405 HWIO_INTLOCK(); \ 406 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ 407 HWIO_INTFREE();\ 408 } while (0) 409 410 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0x70000000 411 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1c 412 413 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x07000000 414 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x18 415 416 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x00700000 417 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x14 418 419 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00070000 420 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x10 421 422 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x00007000 423 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0xc 424 425 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x00000700 426 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0x8 427 428 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00000070 429 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0x4 430 431 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000007 432 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x0 433 434 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// 435 436 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) 437 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) 438 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0x77777777 439 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 0 440 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ 441 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) 442 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ 443 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 444 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ 445 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) 446 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ 447 do {\ 448 HWIO_INTLOCK(); \ 449 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ 450 HWIO_INTFREE();\ 451 } while (0) 452 453 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0x70000000 454 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1c 455 456 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x07000000 457 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x18 458 459 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x00700000 460 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x14 461 462 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00070000 463 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x10 464 465 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x00007000 466 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0xc 467 468 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x00000700 469 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0x8 470 471 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00000070 472 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0x4 473 474 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000007 475 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x0 476 477 //// Register REO_R0_TIMESTAMP //// 478 479 #define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) 480 #define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) 481 #define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff 482 #define HWIO_REO_R0_TIMESTAMP_SHFT 0 483 #define HWIO_REO_R0_TIMESTAMP_IN(x) \ 484 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) 485 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ 486 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 487 #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ 488 out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) 489 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ 490 do {\ 491 HWIO_INTLOCK(); \ 492 out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ 493 HWIO_INTFREE();\ 494 } while (0) 495 496 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff 497 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 498 499 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// 500 501 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) 502 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) 503 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x77777777 504 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 505 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ 506 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) 507 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ 508 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 509 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ 510 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) 511 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ 512 do {\ 513 HWIO_INTLOCK(); \ 514 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ 515 HWIO_INTFREE();\ 516 } while (0) 517 518 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x70000000 519 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x1c 520 521 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x07000000 522 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x18 523 524 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00700000 525 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0x14 526 527 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00070000 528 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0x10 529 530 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00007000 531 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0xc 532 533 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x00000700 534 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x8 535 536 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000070 537 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x4 538 539 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 540 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 541 542 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// 543 544 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) 545 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) 546 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x77777777 547 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 548 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ 549 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) 550 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ 551 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 552 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ 553 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) 554 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ 555 do {\ 556 HWIO_INTLOCK(); \ 557 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ 558 HWIO_INTFREE();\ 559 } while (0) 560 561 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x70000000 562 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0x1c 563 564 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x07000000 565 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0x18 566 567 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00700000 568 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x14 569 570 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x00070000 571 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x10 572 573 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00007000 574 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0xc 575 576 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000700 577 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x8 578 579 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0x00000070 580 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 0x4 581 582 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0x00000007 583 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0x0 584 585 //// Register REO_R0_IDLE_REQ_CTRL //// 586 587 #define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) 588 #define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) 589 #define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 590 #define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 591 #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ 592 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) 593 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ 594 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 595 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ 596 out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) 597 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ 598 do {\ 599 HWIO_INTLOCK(); \ 600 out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ 601 HWIO_INTFREE();\ 602 } while (0) 603 604 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 605 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 606 607 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 608 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 609 610 //// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// 611 612 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) 613 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) 614 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff 615 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 616 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ 617 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) 618 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ 619 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 620 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ 621 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) 622 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ 623 do {\ 624 HWIO_INTLOCK(); \ 625 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ 626 HWIO_INTFREE();\ 627 } while (0) 628 629 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 630 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 631 632 //// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// 633 634 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) 635 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) 636 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff 637 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 638 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ 639 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) 640 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ 641 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 642 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ 643 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) 644 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ 645 do {\ 646 HWIO_INTLOCK(); \ 647 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ 648 HWIO_INTFREE();\ 649 } while (0) 650 651 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 652 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 653 654 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 655 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 656 657 //// Register REO_R0_RXDMA2REO0_RING_ID //// 658 659 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) 660 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) 661 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff 662 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 663 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ 664 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) 665 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ 666 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 667 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ 668 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) 669 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ 670 do {\ 671 HWIO_INTLOCK(); \ 672 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ 673 HWIO_INTFREE();\ 674 } while (0) 675 676 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 677 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 678 679 //// Register REO_R0_RXDMA2REO0_RING_STATUS //// 680 681 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) 682 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) 683 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff 684 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 685 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ 686 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) 687 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ 688 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 689 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ 690 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) 691 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ 692 do {\ 693 HWIO_INTLOCK(); \ 694 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ 695 HWIO_INTFREE();\ 696 } while (0) 697 698 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 699 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 700 701 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 702 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 703 704 //// Register REO_R0_RXDMA2REO0_RING_MISC //// 705 706 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) 707 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) 708 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff 709 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 710 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ 711 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) 712 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ 713 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 714 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ 715 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) 716 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ 717 do {\ 718 HWIO_INTLOCK(); \ 719 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ 720 HWIO_INTFREE();\ 721 } while (0) 722 723 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 724 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe 725 726 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 727 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 728 729 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 730 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 731 732 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 733 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 734 735 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 736 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6 737 738 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 739 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 740 741 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 742 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 743 744 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 745 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 746 747 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 748 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 749 750 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 751 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 752 753 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 754 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 755 756 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// 757 758 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) 759 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) 760 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff 761 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 762 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ 763 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) 764 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ 765 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 766 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ 767 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) 768 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 769 do {\ 770 HWIO_INTLOCK(); \ 771 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ 772 HWIO_INTFREE();\ 773 } while (0) 774 775 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 776 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 777 778 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// 779 780 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) 781 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) 782 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff 783 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 784 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ 785 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) 786 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ 787 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 788 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ 789 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) 790 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 791 do {\ 792 HWIO_INTLOCK(); \ 793 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ 794 HWIO_INTFREE();\ 795 } while (0) 796 797 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 798 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 799 800 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// 801 802 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) 803 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) 804 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 805 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 806 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 807 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) 808 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 809 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 810 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 811 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 812 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 813 do {\ 814 HWIO_INTLOCK(); \ 815 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 816 HWIO_INTFREE();\ 817 } while (0) 818 819 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 820 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 821 822 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 823 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 824 825 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 826 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 827 828 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// 829 830 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) 831 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) 832 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 833 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 834 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 835 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) 836 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 837 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 838 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 839 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 840 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 841 do {\ 842 HWIO_INTLOCK(); \ 843 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 844 HWIO_INTFREE();\ 845 } while (0) 846 847 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 848 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 849 850 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// 851 852 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) 853 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) 854 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 855 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 856 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ 857 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) 858 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 859 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 860 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 861 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) 862 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 863 do {\ 864 HWIO_INTLOCK(); \ 865 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ 866 HWIO_INTFREE();\ 867 } while (0) 868 869 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 870 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 871 872 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 873 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 874 875 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 876 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 877 878 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// 879 880 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) 881 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) 882 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 883 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 884 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 885 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) 886 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 887 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 888 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 889 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 890 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 891 do {\ 892 HWIO_INTLOCK(); \ 893 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 894 HWIO_INTFREE();\ 895 } while (0) 896 897 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 898 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 899 900 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// 901 902 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) 903 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) 904 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 905 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 906 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 907 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) 908 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 909 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 910 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 911 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 912 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 913 do {\ 914 HWIO_INTLOCK(); \ 915 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 916 HWIO_INTFREE();\ 917 } while (0) 918 919 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 920 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 921 922 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// 923 924 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) 925 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) 926 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 927 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 928 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 929 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) 930 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 931 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 932 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 933 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 934 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 935 do {\ 936 HWIO_INTLOCK(); \ 937 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 938 HWIO_INTFREE();\ 939 } while (0) 940 941 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 942 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 943 944 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 945 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 946 947 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// 948 949 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) 950 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) 951 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff 952 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 953 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ 954 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) 955 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ 956 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 957 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ 958 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) 959 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 960 do {\ 961 HWIO_INTLOCK(); \ 962 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ 963 HWIO_INTFREE();\ 964 } while (0) 965 966 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 967 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 968 969 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// 970 971 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) 972 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) 973 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff 974 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 975 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ 976 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) 977 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ 978 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 979 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ 980 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) 981 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 982 do {\ 983 HWIO_INTLOCK(); \ 984 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ 985 HWIO_INTFREE();\ 986 } while (0) 987 988 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 989 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 990 991 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 992 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 993 994 //// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// 995 996 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) 997 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) 998 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff 999 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 1000 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ 1001 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) 1002 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ 1003 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 1004 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ 1005 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) 1006 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ 1007 do {\ 1008 HWIO_INTLOCK(); \ 1009 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ 1010 HWIO_INTFREE();\ 1011 } while (0) 1012 1013 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1014 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 1015 1016 //// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// 1017 1018 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) 1019 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) 1020 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1021 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 1022 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ 1023 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) 1024 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1025 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1026 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1027 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1028 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1029 do {\ 1030 HWIO_INTLOCK(); \ 1031 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ 1032 HWIO_INTFREE();\ 1033 } while (0) 1034 1035 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1036 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1037 1038 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// 1039 1040 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000008c) 1041 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000008c) 1042 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff 1043 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 1044 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ 1045 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) 1046 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ 1047 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 1048 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ 1049 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) 1050 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ 1051 do {\ 1052 HWIO_INTLOCK(); \ 1053 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ 1054 HWIO_INTFREE();\ 1055 } while (0) 1056 1057 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1058 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1059 1060 //// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// 1061 1062 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000090) 1063 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000090) 1064 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff 1065 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 1066 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ 1067 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) 1068 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ 1069 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 1070 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ 1071 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) 1072 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ 1073 do {\ 1074 HWIO_INTLOCK(); \ 1075 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ 1076 HWIO_INTFREE();\ 1077 } while (0) 1078 1079 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1080 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1081 1082 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1083 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1084 1085 //// Register REO_R0_WBM2REO_LINK_RING_ID //// 1086 1087 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000094) 1088 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000094) 1089 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff 1090 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 1091 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ 1092 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) 1093 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ 1094 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 1095 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ 1096 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) 1097 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ 1098 do {\ 1099 HWIO_INTLOCK(); \ 1100 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ 1101 HWIO_INTFREE();\ 1102 } while (0) 1103 1104 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1105 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 1106 1107 //// Register REO_R0_WBM2REO_LINK_RING_STATUS //// 1108 1109 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000098) 1110 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000098) 1111 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff 1112 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 1113 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ 1114 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) 1115 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ 1116 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 1117 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ 1118 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) 1119 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ 1120 do {\ 1121 HWIO_INTLOCK(); \ 1122 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ 1123 HWIO_INTFREE();\ 1124 } while (0) 1125 1126 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1127 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1128 1129 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1130 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1131 1132 //// Register REO_R0_WBM2REO_LINK_RING_MISC //// 1133 1134 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000009c) 1135 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000009c) 1136 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff 1137 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 1138 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ 1139 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) 1140 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ 1141 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 1142 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ 1143 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) 1144 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ 1145 do {\ 1146 HWIO_INTLOCK(); \ 1147 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ 1148 HWIO_INTFREE();\ 1149 } while (0) 1150 1151 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1152 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe 1153 1154 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1155 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1156 1157 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1158 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1159 1160 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1161 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1162 1163 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1164 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 1165 1166 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1167 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1168 1169 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1170 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1171 1172 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1173 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1174 1175 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1176 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 1177 1178 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1179 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1180 1181 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1182 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1183 1184 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// 1185 1186 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) 1187 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) 1188 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff 1189 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 1190 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ 1191 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) 1192 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ 1193 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 1194 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ 1195 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) 1196 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1197 do {\ 1198 HWIO_INTLOCK(); \ 1199 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ 1200 HWIO_INTFREE();\ 1201 } while (0) 1202 1203 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1204 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1205 1206 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// 1207 1208 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) 1209 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) 1210 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff 1211 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 1212 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ 1213 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) 1214 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ 1215 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 1216 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ 1217 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) 1218 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1219 do {\ 1220 HWIO_INTLOCK(); \ 1221 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ 1222 HWIO_INTFREE();\ 1223 } while (0) 1224 1225 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1226 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1227 1228 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// 1229 1230 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) 1231 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) 1232 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1233 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1234 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1235 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1236 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1237 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1238 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1239 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1240 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1241 do {\ 1242 HWIO_INTLOCK(); \ 1243 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1244 HWIO_INTFREE();\ 1245 } while (0) 1246 1247 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1248 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1249 1250 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1251 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1252 1253 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1254 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1255 1256 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// 1257 1258 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) 1259 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) 1260 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1261 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1262 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1263 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1264 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1265 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1266 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1267 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1268 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1269 do {\ 1270 HWIO_INTLOCK(); \ 1271 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1272 HWIO_INTFREE();\ 1273 } while (0) 1274 1275 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1276 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1277 1278 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// 1279 1280 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) 1281 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) 1282 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1283 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 1284 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ 1285 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) 1286 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1287 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1288 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1289 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1290 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1291 do {\ 1292 HWIO_INTLOCK(); \ 1293 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ 1294 HWIO_INTFREE();\ 1295 } while (0) 1296 1297 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1298 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1299 1300 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1301 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1302 1303 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1304 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1305 1306 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// 1307 1308 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) 1309 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) 1310 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1311 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1312 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1313 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1314 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1315 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1316 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1317 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1318 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1319 do {\ 1320 HWIO_INTLOCK(); \ 1321 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1322 HWIO_INTFREE();\ 1323 } while (0) 1324 1325 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1326 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1327 1328 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// 1329 1330 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) 1331 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) 1332 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1333 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1334 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1335 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1336 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1337 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1338 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1339 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1340 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1341 do {\ 1342 HWIO_INTLOCK(); \ 1343 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1344 HWIO_INTFREE();\ 1345 } while (0) 1346 1347 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1348 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1349 1350 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// 1351 1352 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) 1353 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) 1354 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1355 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1356 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1357 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1358 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1359 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1360 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1361 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1362 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1363 do {\ 1364 HWIO_INTLOCK(); \ 1365 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1366 HWIO_INTFREE();\ 1367 } while (0) 1368 1369 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1370 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1371 1372 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1373 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1374 1375 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB //// 1376 1377 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) 1378 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) 1379 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1380 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0 1381 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ 1382 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK) 1383 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ 1384 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) 1385 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ 1386 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) 1387 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1388 do {\ 1389 HWIO_INTLOCK(); \ 1390 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \ 1391 HWIO_INTFREE();\ 1392 } while (0) 1393 1394 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1395 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1396 1397 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB //// 1398 1399 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) 1400 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) 1401 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1402 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0 1403 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ 1404 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK) 1405 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ 1406 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) 1407 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ 1408 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) 1409 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1410 do {\ 1411 HWIO_INTLOCK(); \ 1412 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \ 1413 HWIO_INTFREE();\ 1414 } while (0) 1415 1416 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1417 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1418 1419 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1420 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1421 1422 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_DATA //// 1423 1424 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) 1425 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) 1426 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff 1427 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0 1428 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ 1429 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK) 1430 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \ 1431 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask) 1432 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \ 1433 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val) 1434 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ 1435 do {\ 1436 HWIO_INTLOCK(); \ 1437 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \ 1438 HWIO_INTFREE();\ 1439 } while (0) 1440 1441 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1442 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 1443 1444 //// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// 1445 1446 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) 1447 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) 1448 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1449 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 1450 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ 1451 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) 1452 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1453 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1454 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1455 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1456 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1457 do {\ 1458 HWIO_INTLOCK(); \ 1459 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ 1460 HWIO_INTFREE();\ 1461 } while (0) 1462 1463 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1464 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1465 1466 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// 1467 1468 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x000000e4) 1469 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x000000e4) 1470 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff 1471 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 1472 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ 1473 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) 1474 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ 1475 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 1476 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ 1477 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) 1478 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 1479 do {\ 1480 HWIO_INTLOCK(); \ 1481 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ 1482 HWIO_INTFREE();\ 1483 } while (0) 1484 1485 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1486 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1487 1488 //// Register REO_R0_REO_CMD_RING_BASE_MSB //// 1489 1490 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x000000e8) 1491 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x000000e8) 1492 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff 1493 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 1494 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ 1495 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) 1496 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ 1497 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 1498 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ 1499 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) 1500 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 1501 do {\ 1502 HWIO_INTLOCK(); \ 1503 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ 1504 HWIO_INTFREE();\ 1505 } while (0) 1506 1507 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1508 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1509 1510 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1511 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1512 1513 //// Register REO_R0_REO_CMD_RING_ID //// 1514 1515 #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x000000ec) 1516 #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x000000ec) 1517 #define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff 1518 #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 1519 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ 1520 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) 1521 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ 1522 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 1523 #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ 1524 out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) 1525 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ 1526 do {\ 1527 HWIO_INTLOCK(); \ 1528 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ 1529 HWIO_INTFREE();\ 1530 } while (0) 1531 1532 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1533 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 1534 1535 //// Register REO_R0_REO_CMD_RING_STATUS //// 1536 1537 #define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000000f0) 1538 #define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000000f0) 1539 #define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff 1540 #define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 1541 #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ 1542 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) 1543 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ 1544 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 1545 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ 1546 out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) 1547 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ 1548 do {\ 1549 HWIO_INTLOCK(); \ 1550 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ 1551 HWIO_INTFREE();\ 1552 } while (0) 1553 1554 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1555 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1556 1557 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1558 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1559 1560 //// Register REO_R0_REO_CMD_RING_MISC //// 1561 1562 #define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000000f4) 1563 #define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000000f4) 1564 #define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff 1565 #define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 1566 #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ 1567 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) 1568 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ 1569 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 1570 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ 1571 out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) 1572 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ 1573 do {\ 1574 HWIO_INTLOCK(); \ 1575 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ 1576 HWIO_INTFREE();\ 1577 } while (0) 1578 1579 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1580 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 1581 1582 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1583 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1584 1585 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1586 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1587 1588 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1589 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1590 1591 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1592 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 1593 1594 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1595 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1596 1597 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1598 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1599 1600 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1601 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1602 1603 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1604 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 1605 1606 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1607 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1608 1609 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1610 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1611 1612 //// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// 1613 1614 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) 1615 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) 1616 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 1617 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 1618 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ 1619 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) 1620 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 1621 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 1622 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 1623 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 1624 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1625 do {\ 1626 HWIO_INTLOCK(); \ 1627 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ 1628 HWIO_INTFREE();\ 1629 } while (0) 1630 1631 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1632 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1633 1634 //// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// 1635 1636 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) 1637 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) 1638 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 1639 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 1640 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ 1641 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) 1642 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 1643 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 1644 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 1645 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 1646 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1647 do {\ 1648 HWIO_INTLOCK(); \ 1649 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ 1650 HWIO_INTFREE();\ 1651 } while (0) 1652 1653 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1654 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1655 1656 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 1657 1658 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) 1659 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) 1660 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1661 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1662 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1663 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1664 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1665 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1666 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1667 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1668 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1669 do {\ 1670 HWIO_INTLOCK(); \ 1671 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1672 HWIO_INTFREE();\ 1673 } while (0) 1674 1675 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1676 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1677 1678 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1679 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1680 1681 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1682 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1683 1684 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 1685 1686 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) 1687 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) 1688 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1689 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1690 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1691 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1692 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1693 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1694 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1695 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1696 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1697 do {\ 1698 HWIO_INTLOCK(); \ 1699 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1700 HWIO_INTFREE();\ 1701 } while (0) 1702 1703 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1704 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1705 1706 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// 1707 1708 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) 1709 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) 1710 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1711 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 1712 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 1713 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) 1714 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1715 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1716 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1717 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1718 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1719 do {\ 1720 HWIO_INTLOCK(); \ 1721 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 1722 HWIO_INTFREE();\ 1723 } while (0) 1724 1725 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1726 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1727 1728 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1729 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1730 1731 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1732 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1733 1734 //// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// 1735 1736 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) 1737 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) 1738 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1739 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1740 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1741 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1742 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1743 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1744 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1745 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1746 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1747 do {\ 1748 HWIO_INTLOCK(); \ 1749 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1750 HWIO_INTFREE();\ 1751 } while (0) 1752 1753 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1754 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1755 1756 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// 1757 1758 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) 1759 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) 1760 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1761 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1762 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1763 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1764 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1765 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1766 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1767 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1768 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1769 do {\ 1770 HWIO_INTLOCK(); \ 1771 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1772 HWIO_INTFREE();\ 1773 } while (0) 1774 1775 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1776 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1777 1778 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// 1779 1780 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) 1781 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) 1782 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1783 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1784 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1785 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1786 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1787 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1788 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1789 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1790 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1791 do {\ 1792 HWIO_INTLOCK(); \ 1793 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1794 HWIO_INTFREE();\ 1795 } while (0) 1796 1797 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1798 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1799 1800 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1801 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1802 1803 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// 1804 1805 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) 1806 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) 1807 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1808 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 1809 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ 1810 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) 1811 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 1812 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 1813 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 1814 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 1815 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1816 do {\ 1817 HWIO_INTLOCK(); \ 1818 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 1819 HWIO_INTFREE();\ 1820 } while (0) 1821 1822 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1823 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1824 1825 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// 1826 1827 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) 1828 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) 1829 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1830 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 1831 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ 1832 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) 1833 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 1834 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 1835 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 1836 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 1837 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1838 do {\ 1839 HWIO_INTLOCK(); \ 1840 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 1841 HWIO_INTFREE();\ 1842 } while (0) 1843 1844 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1845 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1846 1847 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1848 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1849 1850 //// Register REO_R0_REO_CMD_RING_MSI1_DATA //// 1851 1852 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000134) 1853 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000134) 1854 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff 1855 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 1856 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ 1857 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) 1858 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ 1859 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 1860 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ 1861 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) 1862 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 1863 do {\ 1864 HWIO_INTLOCK(); \ 1865 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ 1866 HWIO_INTFREE();\ 1867 } while (0) 1868 1869 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1870 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 1871 1872 //// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// 1873 1874 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) 1875 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) 1876 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1877 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 1878 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 1879 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) 1880 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1881 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1882 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1883 out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1884 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1885 do {\ 1886 HWIO_INTLOCK(); \ 1887 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 1888 HWIO_INTFREE();\ 1889 } while (0) 1890 1891 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1892 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1893 1894 //// Register REO_R0_SW2REO_RING_BASE_LSB //// 1895 1896 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x0000013c) 1897 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x0000013c) 1898 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff 1899 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 1900 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ 1901 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) 1902 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ 1903 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 1904 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ 1905 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) 1906 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ 1907 do {\ 1908 HWIO_INTLOCK(); \ 1909 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ 1910 HWIO_INTFREE();\ 1911 } while (0) 1912 1913 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1914 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1915 1916 //// Register REO_R0_SW2REO_RING_BASE_MSB //// 1917 1918 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x00000140) 1919 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x00000140) 1920 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff 1921 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 1922 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ 1923 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) 1924 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ 1925 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 1926 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ 1927 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) 1928 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ 1929 do {\ 1930 HWIO_INTLOCK(); \ 1931 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ 1932 HWIO_INTFREE();\ 1933 } while (0) 1934 1935 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1936 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1937 1938 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1939 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1940 1941 //// Register REO_R0_SW2REO_RING_ID //// 1942 1943 #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x00000144) 1944 #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x00000144) 1945 #define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff 1946 #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 1947 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ 1948 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) 1949 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ 1950 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 1951 #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ 1952 out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) 1953 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ 1954 do {\ 1955 HWIO_INTLOCK(); \ 1956 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ 1957 HWIO_INTFREE();\ 1958 } while (0) 1959 1960 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1961 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 1962 1963 //// Register REO_R0_SW2REO_RING_STATUS //// 1964 1965 #define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x00000148) 1966 #define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x00000148) 1967 #define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff 1968 #define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 1969 #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ 1970 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) 1971 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ 1972 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 1973 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ 1974 out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) 1975 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ 1976 do {\ 1977 HWIO_INTLOCK(); \ 1978 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ 1979 HWIO_INTFREE();\ 1980 } while (0) 1981 1982 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1983 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1984 1985 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1986 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1987 1988 //// Register REO_R0_SW2REO_RING_MISC //// 1989 1990 #define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x0000014c) 1991 #define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x0000014c) 1992 #define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff 1993 #define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 1994 #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ 1995 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) 1996 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ 1997 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 1998 #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ 1999 out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) 2000 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ 2001 do {\ 2002 HWIO_INTLOCK(); \ 2003 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ 2004 HWIO_INTFREE();\ 2005 } while (0) 2006 2007 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2008 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe 2009 2010 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2011 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2012 2013 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2014 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2015 2016 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2017 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2018 2019 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2020 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6 2021 2022 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2023 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2024 2025 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2026 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2027 2028 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2029 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2030 2031 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2032 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 2033 2034 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2035 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2036 2037 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2038 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2039 2040 //// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// 2041 2042 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) 2043 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) 2044 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff 2045 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 2046 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ 2047 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) 2048 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ 2049 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 2050 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ 2051 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) 2052 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2053 do {\ 2054 HWIO_INTLOCK(); \ 2055 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ 2056 HWIO_INTFREE();\ 2057 } while (0) 2058 2059 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2060 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2061 2062 //// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// 2063 2064 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) 2065 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) 2066 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff 2067 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 2068 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ 2069 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) 2070 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ 2071 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 2072 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ 2073 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) 2074 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2075 do {\ 2076 HWIO_INTLOCK(); \ 2077 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ 2078 HWIO_INTFREE();\ 2079 } while (0) 2080 2081 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2082 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2083 2084 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// 2085 2086 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) 2087 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) 2088 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2089 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2090 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2091 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2092 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2093 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2094 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2095 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2096 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2097 do {\ 2098 HWIO_INTLOCK(); \ 2099 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2100 HWIO_INTFREE();\ 2101 } while (0) 2102 2103 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2104 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2105 2106 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2107 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2108 2109 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2110 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2111 2112 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// 2113 2114 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) 2115 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) 2116 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2117 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2118 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2119 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2120 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2121 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2122 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2123 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2124 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2125 do {\ 2126 HWIO_INTLOCK(); \ 2127 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2128 HWIO_INTFREE();\ 2129 } while (0) 2130 2131 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2132 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2133 2134 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// 2135 2136 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) 2137 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) 2138 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2139 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 2140 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ 2141 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) 2142 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2143 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2144 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2145 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2146 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2147 do {\ 2148 HWIO_INTLOCK(); \ 2149 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ 2150 HWIO_INTFREE();\ 2151 } while (0) 2152 2153 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2154 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2155 2156 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2157 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2158 2159 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2160 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2161 2162 //// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// 2163 2164 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) 2165 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) 2166 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2167 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2168 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2169 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2170 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2171 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2172 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2173 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2174 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2175 do {\ 2176 HWIO_INTLOCK(); \ 2177 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2178 HWIO_INTFREE();\ 2179 } while (0) 2180 2181 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2182 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2183 2184 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// 2185 2186 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) 2187 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) 2188 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2189 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2190 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2191 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2192 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2193 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2194 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2195 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2196 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2197 do {\ 2198 HWIO_INTLOCK(); \ 2199 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2200 HWIO_INTFREE();\ 2201 } while (0) 2202 2203 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2204 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2205 2206 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// 2207 2208 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) 2209 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) 2210 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2211 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2212 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2213 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2214 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2215 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2216 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2217 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2218 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2219 do {\ 2220 HWIO_INTLOCK(); \ 2221 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2222 HWIO_INTFREE();\ 2223 } while (0) 2224 2225 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2226 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2227 2228 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2229 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2230 2231 //// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// 2232 2233 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184) 2234 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184) 2235 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2236 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 2237 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ 2238 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) 2239 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ 2240 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 2241 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ 2242 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) 2243 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2244 do {\ 2245 HWIO_INTLOCK(); \ 2246 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ 2247 HWIO_INTFREE();\ 2248 } while (0) 2249 2250 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2251 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2252 2253 //// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// 2254 2255 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188) 2256 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188) 2257 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2258 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 2259 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ 2260 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) 2261 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ 2262 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 2263 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ 2264 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) 2265 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2266 do {\ 2267 HWIO_INTLOCK(); \ 2268 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ 2269 HWIO_INTFREE();\ 2270 } while (0) 2271 2272 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2273 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2274 2275 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2276 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2277 2278 //// Register REO_R0_SW2REO_RING_MSI1_DATA //// 2279 2280 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000018c) 2281 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000018c) 2282 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff 2283 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 2284 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ 2285 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) 2286 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ 2287 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 2288 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ 2289 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) 2290 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ 2291 do {\ 2292 HWIO_INTLOCK(); \ 2293 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ 2294 HWIO_INTFREE();\ 2295 } while (0) 2296 2297 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2298 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 2299 2300 //// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// 2301 2302 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) 2303 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) 2304 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2305 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 2306 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ 2307 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) 2308 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2309 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2310 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2311 out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2312 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2313 do {\ 2314 HWIO_INTLOCK(); \ 2315 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ 2316 HWIO_INTFREE();\ 2317 } while (0) 2318 2319 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2320 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2321 2322 //// Register REO_R0_SW2REO1_RING_BASE_LSB //// 2323 2324 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) (x+0x00000194) 2325 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) (x+0x00000194) 2326 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff 2327 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT 0 2328 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ 2329 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK) 2330 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \ 2331 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask) 2332 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val) \ 2333 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val) 2334 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 2335 do {\ 2336 HWIO_INTLOCK(); \ 2337 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \ 2338 HWIO_INTFREE();\ 2339 } while (0) 2340 2341 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2342 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2343 2344 //// Register REO_R0_SW2REO1_RING_BASE_MSB //// 2345 2346 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000198) 2347 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000198) 2348 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0x00ffffff 2349 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT 0 2350 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ 2351 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK) 2352 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \ 2353 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask) 2354 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val) \ 2355 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val) 2356 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 2357 do {\ 2358 HWIO_INTLOCK(); \ 2359 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \ 2360 HWIO_INTFREE();\ 2361 } while (0) 2362 2363 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2364 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2365 2366 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2367 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2368 2369 //// Register REO_R0_SW2REO1_RING_ID //// 2370 2371 #define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) (x+0x0000019c) 2372 #define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) (x+0x0000019c) 2373 #define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0x000000ff 2374 #define HWIO_REO_R0_SW2REO1_RING_ID_SHFT 0 2375 #define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ 2376 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK) 2377 #define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \ 2378 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask) 2379 #define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val) \ 2380 out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val) 2381 #define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \ 2382 do {\ 2383 HWIO_INTLOCK(); \ 2384 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \ 2385 HWIO_INTFREE();\ 2386 } while (0) 2387 2388 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2389 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 2390 2391 //// Register REO_R0_SW2REO1_RING_STATUS //// 2392 2393 #define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) (x+0x000001a0) 2394 #define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) (x+0x000001a0) 2395 #define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff 2396 #define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT 0 2397 #define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ 2398 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK) 2399 #define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \ 2400 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask) 2401 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val) \ 2402 out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val) 2403 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \ 2404 do {\ 2405 HWIO_INTLOCK(); \ 2406 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \ 2407 HWIO_INTFREE();\ 2408 } while (0) 2409 2410 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2411 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2412 2413 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2414 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2415 2416 //// Register REO_R0_SW2REO1_RING_MISC //// 2417 2418 #define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) (x+0x000001a4) 2419 #define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) (x+0x000001a4) 2420 #define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x003fffff 2421 #define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT 0 2422 #define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ 2423 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK) 2424 #define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \ 2425 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask) 2426 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val) \ 2427 out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val) 2428 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \ 2429 do {\ 2430 HWIO_INTLOCK(); \ 2431 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \ 2432 HWIO_INTFREE();\ 2433 } while (0) 2434 2435 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2436 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2437 2438 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2439 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2440 2441 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2442 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2443 2444 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2445 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2446 2447 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2448 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2449 2450 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2451 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2452 2453 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2454 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2455 2456 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2457 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2458 2459 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2460 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 2461 2462 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2463 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2464 2465 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2466 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2467 2468 //// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB //// 2469 2470 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) 2471 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) 2472 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2473 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT 0 2474 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ 2475 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK) 2476 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 2477 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 2478 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 2479 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 2480 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2481 do {\ 2482 HWIO_INTLOCK(); \ 2483 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \ 2484 HWIO_INTFREE();\ 2485 } while (0) 2486 2487 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2488 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2489 2490 //// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB //// 2491 2492 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) 2493 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) 2494 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2495 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT 0 2496 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ 2497 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK) 2498 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 2499 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 2500 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 2501 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 2502 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2503 do {\ 2504 HWIO_INTLOCK(); \ 2505 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \ 2506 HWIO_INTFREE();\ 2507 } while (0) 2508 2509 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2510 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2511 2512 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 2513 2514 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) 2515 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) 2516 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2517 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2518 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2519 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2520 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2521 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2522 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2523 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2524 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2525 do {\ 2526 HWIO_INTLOCK(); \ 2527 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2528 HWIO_INTFREE();\ 2529 } while (0) 2530 2531 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2532 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2533 2534 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2535 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2536 2537 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2538 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2539 2540 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 2541 2542 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) 2543 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) 2544 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2545 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2546 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2547 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2548 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2549 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2550 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2551 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2552 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2553 do {\ 2554 HWIO_INTLOCK(); \ 2555 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2556 HWIO_INTFREE();\ 2557 } while (0) 2558 2559 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2560 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2561 2562 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS //// 2563 2564 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) 2565 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) 2566 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2567 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 2568 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 2569 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK) 2570 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2571 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2572 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2573 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2574 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2575 do {\ 2576 HWIO_INTLOCK(); \ 2577 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 2578 HWIO_INTFREE();\ 2579 } while (0) 2580 2581 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2582 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2583 2584 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2585 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2586 2587 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2588 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2589 2590 //// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER //// 2591 2592 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) 2593 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) 2594 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2595 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2596 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2597 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2598 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2599 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2600 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2601 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2602 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2603 do {\ 2604 HWIO_INTLOCK(); \ 2605 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2606 HWIO_INTFREE();\ 2607 } while (0) 2608 2609 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2610 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2611 2612 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER //// 2613 2614 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) 2615 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) 2616 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2617 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2618 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2619 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2620 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2621 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2622 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2623 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2624 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2625 do {\ 2626 HWIO_INTLOCK(); \ 2627 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2628 HWIO_INTFREE();\ 2629 } while (0) 2630 2631 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2632 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2633 2634 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS //// 2635 2636 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) 2637 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) 2638 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2639 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2640 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2641 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2642 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2643 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2644 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2645 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2646 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2647 do {\ 2648 HWIO_INTLOCK(); \ 2649 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2650 HWIO_INTFREE();\ 2651 } while (0) 2652 2653 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2654 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2655 2656 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2657 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2658 2659 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB //// 2660 2661 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) 2662 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) 2663 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2664 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT 0 2665 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ 2666 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK) 2667 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 2668 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 2669 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 2670 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 2671 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2672 do {\ 2673 HWIO_INTLOCK(); \ 2674 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 2675 HWIO_INTFREE();\ 2676 } while (0) 2677 2678 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2679 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2680 2681 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB //// 2682 2683 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) 2684 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) 2685 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2686 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT 0 2687 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ 2688 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK) 2689 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 2690 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 2691 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 2692 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 2693 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2694 do {\ 2695 HWIO_INTLOCK(); \ 2696 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 2697 HWIO_INTFREE();\ 2698 } while (0) 2699 2700 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2701 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2702 2703 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2704 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2705 2706 //// Register REO_R0_SW2REO1_RING_MSI1_DATA //// 2707 2708 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) 2709 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) 2710 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff 2711 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT 0 2712 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ 2713 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK) 2714 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \ 2715 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask) 2716 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val) \ 2717 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val) 2718 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 2719 do {\ 2720 HWIO_INTLOCK(); \ 2721 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \ 2722 HWIO_INTFREE();\ 2723 } while (0) 2724 2725 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2726 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 2727 2728 //// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET //// 2729 2730 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) 2731 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) 2732 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2733 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 2734 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 2735 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK) 2736 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2737 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2738 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2739 out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2740 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2741 do {\ 2742 HWIO_INTLOCK(); \ 2743 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 2744 HWIO_INTFREE();\ 2745 } while (0) 2746 2747 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2748 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2749 2750 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// 2751 2752 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x000001ec) 2753 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x000001ec) 2754 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff 2755 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 2756 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ 2757 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) 2758 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ 2759 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 2760 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ 2761 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) 2762 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ 2763 do {\ 2764 HWIO_INTLOCK(); \ 2765 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ 2766 HWIO_INTFREE();\ 2767 } while (0) 2768 2769 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2770 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2771 2772 //// Register REO_R0_REO2SW1_RING_BASE_MSB //// 2773 2774 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x000001f0) 2775 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x000001f0) 2776 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x0fffffff 2777 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 2778 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ 2779 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) 2780 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ 2781 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 2782 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ 2783 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) 2784 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ 2785 do {\ 2786 HWIO_INTLOCK(); \ 2787 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ 2788 HWIO_INTFREE();\ 2789 } while (0) 2790 2791 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2792 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2793 2794 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2795 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2796 2797 //// Register REO_R0_REO2SW1_RING_ID //// 2798 2799 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x000001f4) 2800 #define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x000001f4) 2801 #define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff 2802 #define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 2803 #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ 2804 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) 2805 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ 2806 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 2807 #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ 2808 out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) 2809 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ 2810 do {\ 2811 HWIO_INTLOCK(); \ 2812 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ 2813 HWIO_INTFREE();\ 2814 } while (0) 2815 2816 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 2817 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 2818 2819 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2820 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 2821 2822 //// Register REO_R0_REO2SW1_RING_STATUS //// 2823 2824 #define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x000001f8) 2825 #define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x000001f8) 2826 #define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff 2827 #define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 2828 #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ 2829 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) 2830 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ 2831 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 2832 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ 2833 out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) 2834 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ 2835 do {\ 2836 HWIO_INTLOCK(); \ 2837 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ 2838 HWIO_INTFREE();\ 2839 } while (0) 2840 2841 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2842 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2843 2844 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2845 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2846 2847 //// Register REO_R0_REO2SW1_RING_MISC //// 2848 2849 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x000001fc) 2850 #define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x000001fc) 2851 #define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff 2852 #define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 2853 #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ 2854 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) 2855 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ 2856 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 2857 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ 2858 out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) 2859 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ 2860 do {\ 2861 HWIO_INTLOCK(); \ 2862 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ 2863 HWIO_INTFREE();\ 2864 } while (0) 2865 2866 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 2867 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16 2868 2869 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2870 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2871 2872 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2873 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2874 2875 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2876 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2877 2878 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2879 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2880 2881 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2882 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2883 2884 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2885 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2886 2887 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2888 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2889 2890 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2891 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2892 2893 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2894 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 2895 2896 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2897 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2898 2899 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2900 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2901 2902 //// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// 2903 2904 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000200) 2905 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000200) 2906 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff 2907 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 2908 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ 2909 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) 2910 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ 2911 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 2912 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ 2913 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) 2914 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 2915 do {\ 2916 HWIO_INTLOCK(); \ 2917 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ 2918 HWIO_INTFREE();\ 2919 } while (0) 2920 2921 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 2922 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 2923 2924 //// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// 2925 2926 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000204) 2927 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000204) 2928 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff 2929 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 2930 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ 2931 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) 2932 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ 2933 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 2934 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ 2935 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) 2936 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 2937 do {\ 2938 HWIO_INTLOCK(); \ 2939 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ 2940 HWIO_INTFREE();\ 2941 } while (0) 2942 2943 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 2944 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 2945 2946 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// 2947 2948 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000210) 2949 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000210) 2950 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 2951 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 2952 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ 2953 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) 2954 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 2955 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 2956 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 2957 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 2958 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 2959 do {\ 2960 HWIO_INTLOCK(); \ 2961 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ 2962 HWIO_INTFREE();\ 2963 } while (0) 2964 2965 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2966 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2967 2968 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 2969 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 2970 2971 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2972 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2973 2974 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// 2975 2976 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000214) 2977 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000214) 2978 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 2979 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 2980 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ 2981 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) 2982 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 2983 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 2984 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 2985 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 2986 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 2987 do {\ 2988 HWIO_INTLOCK(); \ 2989 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ 2990 HWIO_INTFREE();\ 2991 } while (0) 2992 2993 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2994 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2995 2996 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 2997 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 2998 2999 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3000 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3001 3002 //// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// 3003 3004 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000218) 3005 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000218) 3006 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3007 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3008 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3009 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) 3010 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3011 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3012 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3013 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3014 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3015 do {\ 3016 HWIO_INTLOCK(); \ 3017 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3018 HWIO_INTFREE();\ 3019 } while (0) 3020 3021 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3022 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3023 3024 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// 3025 3026 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) 3027 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) 3028 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3029 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 3030 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ 3031 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) 3032 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3033 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3034 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3035 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) 3036 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3037 do {\ 3038 HWIO_INTLOCK(); \ 3039 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ 3040 HWIO_INTFREE();\ 3041 } while (0) 3042 3043 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3044 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3045 3046 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// 3047 3048 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) 3049 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) 3050 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3051 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 3052 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ 3053 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) 3054 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3055 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3056 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3057 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) 3058 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3059 do {\ 3060 HWIO_INTLOCK(); \ 3061 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ 3062 HWIO_INTFREE();\ 3063 } while (0) 3064 3065 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3066 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3067 3068 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3069 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3070 3071 //// Register REO_R0_REO2SW1_RING_MSI1_DATA //// 3072 3073 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) 3074 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) 3075 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff 3076 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 3077 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ 3078 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) 3079 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ 3080 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 3081 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ 3082 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) 3083 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3084 do {\ 3085 HWIO_INTLOCK(); \ 3086 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ 3087 HWIO_INTFREE();\ 3088 } while (0) 3089 3090 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3091 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 3092 3093 //// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// 3094 3095 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) 3096 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) 3097 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3098 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 3099 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ 3100 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) 3101 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3102 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3103 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3104 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3105 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3106 do {\ 3107 HWIO_INTLOCK(); \ 3108 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3109 HWIO_INTFREE();\ 3110 } while (0) 3111 3112 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3113 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3114 3115 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// 3116 3117 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x00000244) 3118 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x00000244) 3119 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff 3120 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 3121 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ 3122 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) 3123 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ 3124 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 3125 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ 3126 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) 3127 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ 3128 do {\ 3129 HWIO_INTLOCK(); \ 3130 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ 3131 HWIO_INTFREE();\ 3132 } while (0) 3133 3134 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3135 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3136 3137 //// Register REO_R0_REO2SW2_RING_BASE_MSB //// 3138 3139 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x00000248) 3140 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x00000248) 3141 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x0fffffff 3142 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 3143 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ 3144 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) 3145 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ 3146 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 3147 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ 3148 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) 3149 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ 3150 do {\ 3151 HWIO_INTLOCK(); \ 3152 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ 3153 HWIO_INTFREE();\ 3154 } while (0) 3155 3156 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3157 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3158 3159 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3160 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3161 3162 //// Register REO_R0_REO2SW2_RING_ID //// 3163 3164 #define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x0000024c) 3165 #define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x0000024c) 3166 #define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff 3167 #define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 3168 #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ 3169 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) 3170 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ 3171 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 3172 #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ 3173 out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) 3174 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ 3175 do {\ 3176 HWIO_INTLOCK(); \ 3177 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ 3178 HWIO_INTFREE();\ 3179 } while (0) 3180 3181 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 3182 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 3183 3184 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3185 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 3186 3187 //// Register REO_R0_REO2SW2_RING_STATUS //// 3188 3189 #define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x00000250) 3190 #define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x00000250) 3191 #define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff 3192 #define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 3193 #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ 3194 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) 3195 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ 3196 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 3197 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ 3198 out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) 3199 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ 3200 do {\ 3201 HWIO_INTLOCK(); \ 3202 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ 3203 HWIO_INTFREE();\ 3204 } while (0) 3205 3206 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3207 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3208 3209 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3210 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3211 3212 //// Register REO_R0_REO2SW2_RING_MISC //// 3213 3214 #define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x00000254) 3215 #define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x00000254) 3216 #define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff 3217 #define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 3218 #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ 3219 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) 3220 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ 3221 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 3222 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ 3223 out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) 3224 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ 3225 do {\ 3226 HWIO_INTLOCK(); \ 3227 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ 3228 HWIO_INTFREE();\ 3229 } while (0) 3230 3231 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3232 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16 3233 3234 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3235 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe 3236 3237 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3238 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3239 3240 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3241 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3242 3243 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3244 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3245 3246 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3247 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6 3248 3249 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3250 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3251 3252 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3253 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3254 3255 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3256 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3257 3258 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3259 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 3260 3261 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3262 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3263 3264 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3265 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3266 3267 //// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// 3268 3269 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) 3270 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) 3271 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3272 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 3273 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ 3274 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) 3275 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ 3276 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 3277 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ 3278 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) 3279 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3280 do {\ 3281 HWIO_INTLOCK(); \ 3282 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ 3283 HWIO_INTFREE();\ 3284 } while (0) 3285 3286 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3287 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3288 3289 //// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// 3290 3291 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) 3292 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) 3293 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3294 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 3295 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ 3296 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) 3297 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ 3298 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 3299 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ 3300 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) 3301 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3302 do {\ 3303 HWIO_INTLOCK(); \ 3304 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ 3305 HWIO_INTFREE();\ 3306 } while (0) 3307 3308 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3309 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3310 3311 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// 3312 3313 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) 3314 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) 3315 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3316 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 3317 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ 3318 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) 3319 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3320 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3321 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3322 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3323 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3324 do {\ 3325 HWIO_INTLOCK(); \ 3326 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ 3327 HWIO_INTFREE();\ 3328 } while (0) 3329 3330 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3331 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3332 3333 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3334 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3335 3336 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3337 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3338 3339 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// 3340 3341 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) 3342 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) 3343 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3344 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 3345 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ 3346 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) 3347 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3348 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3349 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3350 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3351 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3352 do {\ 3353 HWIO_INTLOCK(); \ 3354 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ 3355 HWIO_INTFREE();\ 3356 } while (0) 3357 3358 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3359 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3360 3361 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3362 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3363 3364 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3365 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3366 3367 //// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// 3368 3369 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) 3370 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) 3371 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3372 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 3373 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3374 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) 3375 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3376 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3377 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3378 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3379 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3380 do {\ 3381 HWIO_INTLOCK(); \ 3382 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3383 HWIO_INTFREE();\ 3384 } while (0) 3385 3386 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3387 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3388 3389 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// 3390 3391 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) 3392 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) 3393 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3394 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 3395 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ 3396 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) 3397 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ 3398 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 3399 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ 3400 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) 3401 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3402 do {\ 3403 HWIO_INTLOCK(); \ 3404 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ 3405 HWIO_INTFREE();\ 3406 } while (0) 3407 3408 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3409 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3410 3411 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// 3412 3413 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) 3414 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) 3415 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3416 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 3417 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ 3418 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) 3419 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ 3420 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 3421 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ 3422 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) 3423 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3424 do {\ 3425 HWIO_INTLOCK(); \ 3426 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ 3427 HWIO_INTFREE();\ 3428 } while (0) 3429 3430 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3431 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3432 3433 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3434 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3435 3436 //// Register REO_R0_REO2SW2_RING_MSI1_DATA //// 3437 3438 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x00000294) 3439 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x00000294) 3440 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff 3441 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 3442 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ 3443 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) 3444 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ 3445 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 3446 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ 3447 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) 3448 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ 3449 do {\ 3450 HWIO_INTLOCK(); \ 3451 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ 3452 HWIO_INTFREE();\ 3453 } while (0) 3454 3455 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3456 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 3457 3458 //// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// 3459 3460 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) 3461 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) 3462 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3463 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 3464 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ 3465 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) 3466 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3467 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3468 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3469 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3470 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3471 do {\ 3472 HWIO_INTLOCK(); \ 3473 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ 3474 HWIO_INTFREE();\ 3475 } while (0) 3476 3477 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3478 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3479 3480 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// 3481 3482 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x0000029c) 3483 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x0000029c) 3484 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff 3485 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 3486 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ 3487 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) 3488 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ 3489 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 3490 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ 3491 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) 3492 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ 3493 do {\ 3494 HWIO_INTLOCK(); \ 3495 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ 3496 HWIO_INTFREE();\ 3497 } while (0) 3498 3499 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3500 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3501 3502 //// Register REO_R0_REO2SW3_RING_BASE_MSB //// 3503 3504 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002a0) 3505 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002a0) 3506 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x0fffffff 3507 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 3508 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ 3509 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) 3510 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ 3511 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 3512 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ 3513 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) 3514 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ 3515 do {\ 3516 HWIO_INTLOCK(); \ 3517 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ 3518 HWIO_INTFREE();\ 3519 } while (0) 3520 3521 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3522 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3523 3524 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3525 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3526 3527 //// Register REO_R0_REO2SW3_RING_ID //// 3528 3529 #define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002a4) 3530 #define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002a4) 3531 #define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff 3532 #define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 3533 #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ 3534 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) 3535 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ 3536 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 3537 #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ 3538 out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) 3539 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ 3540 do {\ 3541 HWIO_INTLOCK(); \ 3542 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ 3543 HWIO_INTFREE();\ 3544 } while (0) 3545 3546 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 3547 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 3548 3549 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3550 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 3551 3552 //// Register REO_R0_REO2SW3_RING_STATUS //// 3553 3554 #define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x000002a8) 3555 #define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x000002a8) 3556 #define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff 3557 #define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 3558 #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ 3559 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) 3560 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ 3561 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 3562 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ 3563 out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) 3564 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ 3565 do {\ 3566 HWIO_INTLOCK(); \ 3567 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ 3568 HWIO_INTFREE();\ 3569 } while (0) 3570 3571 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3572 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3573 3574 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3575 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3576 3577 //// Register REO_R0_REO2SW3_RING_MISC //// 3578 3579 #define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x000002ac) 3580 #define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x000002ac) 3581 #define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff 3582 #define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 3583 #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ 3584 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) 3585 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ 3586 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 3587 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ 3588 out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) 3589 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ 3590 do {\ 3591 HWIO_INTLOCK(); \ 3592 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ 3593 HWIO_INTFREE();\ 3594 } while (0) 3595 3596 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3597 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16 3598 3599 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3600 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe 3601 3602 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3603 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3604 3605 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3606 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3607 3608 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3609 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3610 3611 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3612 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6 3613 3614 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3615 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3616 3617 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3618 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3619 3620 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3621 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3622 3623 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3624 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 3625 3626 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3627 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3628 3629 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3630 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3631 3632 //// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// 3633 3634 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) 3635 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) 3636 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff 3637 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 3638 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ 3639 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) 3640 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ 3641 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 3642 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ 3643 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) 3644 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3645 do {\ 3646 HWIO_INTLOCK(); \ 3647 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ 3648 HWIO_INTFREE();\ 3649 } while (0) 3650 3651 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3652 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3653 3654 //// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// 3655 3656 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) 3657 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) 3658 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff 3659 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 3660 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ 3661 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) 3662 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ 3663 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 3664 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ 3665 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) 3666 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3667 do {\ 3668 HWIO_INTLOCK(); \ 3669 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ 3670 HWIO_INTFREE();\ 3671 } while (0) 3672 3673 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3674 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3675 3676 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// 3677 3678 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) 3679 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) 3680 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3681 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 3682 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ 3683 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) 3684 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3685 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3686 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3687 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3688 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3689 do {\ 3690 HWIO_INTLOCK(); \ 3691 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ 3692 HWIO_INTFREE();\ 3693 } while (0) 3694 3695 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3696 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3697 3698 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3699 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3700 3701 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3702 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3703 3704 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// 3705 3706 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) 3707 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) 3708 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3709 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 3710 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ 3711 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) 3712 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3713 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3714 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3715 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3716 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3717 do {\ 3718 HWIO_INTLOCK(); \ 3719 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ 3720 HWIO_INTFREE();\ 3721 } while (0) 3722 3723 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3724 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3725 3726 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3727 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3728 3729 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3730 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3731 3732 //// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// 3733 3734 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) 3735 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) 3736 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3737 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 3738 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3739 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) 3740 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3741 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3742 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3743 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3744 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3745 do {\ 3746 HWIO_INTLOCK(); \ 3747 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3748 HWIO_INTFREE();\ 3749 } while (0) 3750 3751 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3752 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3753 3754 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// 3755 3756 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) 3757 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) 3758 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3759 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 3760 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ 3761 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) 3762 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ 3763 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 3764 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ 3765 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) 3766 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3767 do {\ 3768 HWIO_INTLOCK(); \ 3769 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ 3770 HWIO_INTFREE();\ 3771 } while (0) 3772 3773 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3774 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3775 3776 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// 3777 3778 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) 3779 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) 3780 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3781 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 3782 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ 3783 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) 3784 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ 3785 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 3786 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ 3787 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) 3788 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3789 do {\ 3790 HWIO_INTLOCK(); \ 3791 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ 3792 HWIO_INTFREE();\ 3793 } while (0) 3794 3795 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3796 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3797 3798 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3799 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3800 3801 //// Register REO_R0_REO2SW3_RING_MSI1_DATA //// 3802 3803 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) 3804 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) 3805 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff 3806 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 3807 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ 3808 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) 3809 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ 3810 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 3811 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ 3812 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) 3813 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ 3814 do {\ 3815 HWIO_INTLOCK(); \ 3816 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ 3817 HWIO_INTFREE();\ 3818 } while (0) 3819 3820 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3821 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 3822 3823 //// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// 3824 3825 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) 3826 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) 3827 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3828 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 3829 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ 3830 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) 3831 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3832 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3833 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3834 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3835 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3836 do {\ 3837 HWIO_INTLOCK(); \ 3838 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ 3839 HWIO_INTFREE();\ 3840 } while (0) 3841 3842 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3843 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3844 3845 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// 3846 3847 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x000002f4) 3848 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x000002f4) 3849 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff 3850 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 3851 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ 3852 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) 3853 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ 3854 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 3855 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ 3856 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) 3857 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ 3858 do {\ 3859 HWIO_INTLOCK(); \ 3860 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ 3861 HWIO_INTFREE();\ 3862 } while (0) 3863 3864 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3865 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3866 3867 //// Register REO_R0_REO2SW4_RING_BASE_MSB //// 3868 3869 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x000002f8) 3870 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x000002f8) 3871 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x0fffffff 3872 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 3873 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ 3874 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) 3875 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ 3876 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 3877 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ 3878 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) 3879 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ 3880 do {\ 3881 HWIO_INTLOCK(); \ 3882 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ 3883 HWIO_INTFREE();\ 3884 } while (0) 3885 3886 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3887 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3888 3889 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3890 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3891 3892 //// Register REO_R0_REO2SW4_RING_ID //// 3893 3894 #define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x000002fc) 3895 #define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x000002fc) 3896 #define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff 3897 #define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 3898 #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ 3899 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) 3900 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ 3901 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 3902 #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ 3903 out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) 3904 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ 3905 do {\ 3906 HWIO_INTLOCK(); \ 3907 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ 3908 HWIO_INTFREE();\ 3909 } while (0) 3910 3911 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 3912 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 3913 3914 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3915 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 3916 3917 //// Register REO_R0_REO2SW4_RING_STATUS //// 3918 3919 #define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000300) 3920 #define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000300) 3921 #define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff 3922 #define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 3923 #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ 3924 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) 3925 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ 3926 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 3927 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ 3928 out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) 3929 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ 3930 do {\ 3931 HWIO_INTLOCK(); \ 3932 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ 3933 HWIO_INTFREE();\ 3934 } while (0) 3935 3936 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3937 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3938 3939 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3940 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3941 3942 //// Register REO_R0_REO2SW4_RING_MISC //// 3943 3944 #define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x00000304) 3945 #define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x00000304) 3946 #define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff 3947 #define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 3948 #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ 3949 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) 3950 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ 3951 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 3952 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ 3953 out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) 3954 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ 3955 do {\ 3956 HWIO_INTLOCK(); \ 3957 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ 3958 HWIO_INTFREE();\ 3959 } while (0) 3960 3961 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3962 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16 3963 3964 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3965 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe 3966 3967 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3968 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3969 3970 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3971 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3972 3973 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3974 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3975 3976 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3977 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6 3978 3979 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3980 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3981 3982 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3983 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3984 3985 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3986 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3987 3988 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3989 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 3990 3991 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3992 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3993 3994 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3995 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3996 3997 //// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// 3998 3999 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) 4000 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) 4001 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff 4002 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 4003 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ 4004 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) 4005 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ 4006 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 4007 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ 4008 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) 4009 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4010 do {\ 4011 HWIO_INTLOCK(); \ 4012 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ 4013 HWIO_INTFREE();\ 4014 } while (0) 4015 4016 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4017 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4018 4019 //// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// 4020 4021 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) 4022 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) 4023 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff 4024 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 4025 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ 4026 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) 4027 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ 4028 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 4029 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ 4030 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) 4031 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4032 do {\ 4033 HWIO_INTLOCK(); \ 4034 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ 4035 HWIO_INTFREE();\ 4036 } while (0) 4037 4038 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4039 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4040 4041 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// 4042 4043 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) 4044 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) 4045 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4046 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 4047 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ 4048 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) 4049 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4050 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4051 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4052 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4053 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4054 do {\ 4055 HWIO_INTLOCK(); \ 4056 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ 4057 HWIO_INTFREE();\ 4058 } while (0) 4059 4060 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4061 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4062 4063 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4064 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4065 4066 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4067 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4068 4069 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// 4070 4071 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) 4072 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) 4073 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4074 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 4075 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ 4076 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) 4077 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4078 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4079 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4080 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4081 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4082 do {\ 4083 HWIO_INTLOCK(); \ 4084 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ 4085 HWIO_INTFREE();\ 4086 } while (0) 4087 4088 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4089 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4090 4091 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4092 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4093 4094 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4095 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4096 4097 //// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// 4098 4099 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) 4100 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) 4101 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4102 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 4103 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4104 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) 4105 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4106 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4107 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4108 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4109 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4110 do {\ 4111 HWIO_INTLOCK(); \ 4112 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4113 HWIO_INTFREE();\ 4114 } while (0) 4115 4116 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4117 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4118 4119 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// 4120 4121 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) 4122 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) 4123 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4124 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 4125 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ 4126 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) 4127 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ 4128 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 4129 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ 4130 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) 4131 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4132 do {\ 4133 HWIO_INTLOCK(); \ 4134 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ 4135 HWIO_INTFREE();\ 4136 } while (0) 4137 4138 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4139 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4140 4141 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// 4142 4143 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) 4144 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) 4145 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4146 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 4147 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ 4148 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) 4149 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ 4150 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 4151 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ 4152 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) 4153 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4154 do {\ 4155 HWIO_INTLOCK(); \ 4156 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ 4157 HWIO_INTFREE();\ 4158 } while (0) 4159 4160 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4161 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4162 4163 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4164 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4165 4166 //// Register REO_R0_REO2SW4_RING_MSI1_DATA //// 4167 4168 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x00000344) 4169 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x00000344) 4170 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff 4171 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 4172 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ 4173 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) 4174 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ 4175 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 4176 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ 4177 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) 4178 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ 4179 do {\ 4180 HWIO_INTLOCK(); \ 4181 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ 4182 HWIO_INTFREE();\ 4183 } while (0) 4184 4185 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4186 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 4187 4188 //// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// 4189 4190 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) 4191 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) 4192 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4193 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 4194 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ 4195 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) 4196 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4197 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4198 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4199 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4200 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4201 do {\ 4202 HWIO_INTLOCK(); \ 4203 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ 4204 HWIO_INTFREE();\ 4205 } while (0) 4206 4207 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4208 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4209 4210 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// 4211 4212 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003fc) 4213 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003fc) 4214 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff 4215 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 4216 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ 4217 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) 4218 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ 4219 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 4220 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ 4221 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) 4222 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ 4223 do {\ 4224 HWIO_INTLOCK(); \ 4225 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ 4226 HWIO_INTFREE();\ 4227 } while (0) 4228 4229 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4230 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4231 4232 //// Register REO_R0_REO2TCL_RING_BASE_MSB //// 4233 4234 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x00000400) 4235 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x00000400) 4236 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x0fffffff 4237 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 4238 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ 4239 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) 4240 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ 4241 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 4242 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ 4243 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) 4244 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ 4245 do {\ 4246 HWIO_INTLOCK(); \ 4247 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ 4248 HWIO_INTFREE();\ 4249 } while (0) 4250 4251 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4252 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4253 4254 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4255 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4256 4257 //// Register REO_R0_REO2TCL_RING_ID //// 4258 4259 #define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x00000404) 4260 #define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x00000404) 4261 #define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff 4262 #define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 4263 #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ 4264 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) 4265 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ 4266 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 4267 #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ 4268 out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) 4269 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ 4270 do {\ 4271 HWIO_INTLOCK(); \ 4272 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ 4273 HWIO_INTFREE();\ 4274 } while (0) 4275 4276 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 4277 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 4278 4279 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4280 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 4281 4282 //// Register REO_R0_REO2TCL_RING_STATUS //// 4283 4284 #define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x00000408) 4285 #define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x00000408) 4286 #define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff 4287 #define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 4288 #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ 4289 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) 4290 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ 4291 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 4292 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ 4293 out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) 4294 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ 4295 do {\ 4296 HWIO_INTLOCK(); \ 4297 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ 4298 HWIO_INTFREE();\ 4299 } while (0) 4300 4301 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4302 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4303 4304 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4305 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4306 4307 //// Register REO_R0_REO2TCL_RING_MISC //// 4308 4309 #define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x0000040c) 4310 #define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x0000040c) 4311 #define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff 4312 #define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 4313 #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ 4314 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) 4315 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ 4316 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 4317 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ 4318 out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) 4319 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ 4320 do {\ 4321 HWIO_INTLOCK(); \ 4322 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ 4323 HWIO_INTFREE();\ 4324 } while (0) 4325 4326 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4327 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16 4328 4329 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4330 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe 4331 4332 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4333 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4334 4335 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4336 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4337 4338 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4339 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4340 4341 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4342 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6 4343 4344 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4345 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4346 4347 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4348 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4349 4350 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4351 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4352 4353 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4354 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 4355 4356 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4357 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4358 4359 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4360 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4361 4362 //// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// 4363 4364 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) 4365 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) 4366 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff 4367 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 4368 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ 4369 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) 4370 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ 4371 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 4372 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ 4373 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) 4374 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4375 do {\ 4376 HWIO_INTLOCK(); \ 4377 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ 4378 HWIO_INTFREE();\ 4379 } while (0) 4380 4381 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4382 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4383 4384 //// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// 4385 4386 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) 4387 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) 4388 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff 4389 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 4390 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ 4391 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) 4392 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ 4393 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 4394 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ 4395 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) 4396 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4397 do {\ 4398 HWIO_INTLOCK(); \ 4399 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ 4400 HWIO_INTFREE();\ 4401 } while (0) 4402 4403 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4404 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4405 4406 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// 4407 4408 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) 4409 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) 4410 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4411 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 4412 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ 4413 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) 4414 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4415 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4416 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4417 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4418 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4419 do {\ 4420 HWIO_INTLOCK(); \ 4421 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ 4422 HWIO_INTFREE();\ 4423 } while (0) 4424 4425 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4426 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4427 4428 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4429 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4430 4431 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4432 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4433 4434 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// 4435 4436 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) 4437 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) 4438 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4439 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 4440 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ 4441 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) 4442 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4443 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4444 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4445 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4446 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4447 do {\ 4448 HWIO_INTLOCK(); \ 4449 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ 4450 HWIO_INTFREE();\ 4451 } while (0) 4452 4453 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4454 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4455 4456 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4457 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4458 4459 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4460 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4461 4462 //// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// 4463 4464 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) 4465 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) 4466 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4467 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 4468 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4469 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) 4470 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4471 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4472 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4473 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4474 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4475 do {\ 4476 HWIO_INTLOCK(); \ 4477 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4478 HWIO_INTFREE();\ 4479 } while (0) 4480 4481 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4482 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4483 4484 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// 4485 4486 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) 4487 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) 4488 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4489 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 4490 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ 4491 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) 4492 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ 4493 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 4494 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ 4495 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) 4496 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4497 do {\ 4498 HWIO_INTLOCK(); \ 4499 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ 4500 HWIO_INTFREE();\ 4501 } while (0) 4502 4503 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4504 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4505 4506 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// 4507 4508 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) 4509 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) 4510 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4511 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 4512 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ 4513 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) 4514 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ 4515 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 4516 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ 4517 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) 4518 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4519 do {\ 4520 HWIO_INTLOCK(); \ 4521 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ 4522 HWIO_INTFREE();\ 4523 } while (0) 4524 4525 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4526 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4527 4528 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4529 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4530 4531 //// Register REO_R0_REO2TCL_RING_MSI1_DATA //// 4532 4533 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) 4534 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) 4535 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff 4536 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 4537 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ 4538 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) 4539 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ 4540 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 4541 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ 4542 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) 4543 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ 4544 do {\ 4545 HWIO_INTLOCK(); \ 4546 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ 4547 HWIO_INTFREE();\ 4548 } while (0) 4549 4550 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4551 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 4552 4553 //// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// 4554 4555 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) 4556 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) 4557 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4558 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 4559 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ 4560 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) 4561 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4562 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4563 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4564 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4565 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4566 do {\ 4567 HWIO_INTLOCK(); \ 4568 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ 4569 HWIO_INTFREE();\ 4570 } while (0) 4571 4572 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4573 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4574 4575 //// Register REO_R0_REO2FW_RING_BASE_LSB //// 4576 4577 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x00000454) 4578 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x00000454) 4579 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff 4580 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 4581 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ 4582 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) 4583 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ 4584 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 4585 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ 4586 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) 4587 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4588 do {\ 4589 HWIO_INTLOCK(); \ 4590 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ 4591 HWIO_INTFREE();\ 4592 } while (0) 4593 4594 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4595 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4596 4597 //// Register REO_R0_REO2FW_RING_BASE_MSB //// 4598 4599 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000458) 4600 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000458) 4601 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x0fffffff 4602 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 4603 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ 4604 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) 4605 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ 4606 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 4607 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ 4608 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) 4609 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4610 do {\ 4611 HWIO_INTLOCK(); \ 4612 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ 4613 HWIO_INTFREE();\ 4614 } while (0) 4615 4616 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4617 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4618 4619 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4620 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4621 4622 //// Register REO_R0_REO2FW_RING_ID //// 4623 4624 #define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x0000045c) 4625 #define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x0000045c) 4626 #define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff 4627 #define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 4628 #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ 4629 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) 4630 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ 4631 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 4632 #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ 4633 out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) 4634 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ 4635 do {\ 4636 HWIO_INTLOCK(); \ 4637 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ 4638 HWIO_INTFREE();\ 4639 } while (0) 4640 4641 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4642 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 4643 4644 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4645 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4646 4647 //// Register REO_R0_REO2FW_RING_STATUS //// 4648 4649 #define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000460) 4650 #define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000460) 4651 #define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff 4652 #define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 4653 #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ 4654 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) 4655 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ 4656 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 4657 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ 4658 out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) 4659 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ 4660 do {\ 4661 HWIO_INTLOCK(); \ 4662 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ 4663 HWIO_INTFREE();\ 4664 } while (0) 4665 4666 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4667 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4668 4669 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4670 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4671 4672 //// Register REO_R0_REO2FW_RING_MISC //// 4673 4674 #define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x00000464) 4675 #define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x00000464) 4676 #define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff 4677 #define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 4678 #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ 4679 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) 4680 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ 4681 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 4682 #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ 4683 out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) 4684 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ 4685 do {\ 4686 HWIO_INTLOCK(); \ 4687 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ 4688 HWIO_INTFREE();\ 4689 } while (0) 4690 4691 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4692 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4693 4694 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4695 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4696 4697 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4698 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4699 4700 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4701 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4702 4703 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4704 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4705 4706 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4707 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4708 4709 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4710 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4711 4712 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4713 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4714 4715 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4716 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4717 4718 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4719 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4720 4721 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4722 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4723 4724 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4725 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4726 4727 //// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// 4728 4729 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) 4730 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) 4731 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4732 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 4733 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ 4734 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) 4735 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4736 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4737 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4738 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4739 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4740 do {\ 4741 HWIO_INTLOCK(); \ 4742 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ 4743 HWIO_INTFREE();\ 4744 } while (0) 4745 4746 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4747 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4748 4749 //// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// 4750 4751 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) 4752 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) 4753 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4754 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 4755 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ 4756 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) 4757 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4758 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4759 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4760 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4761 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4762 do {\ 4763 HWIO_INTLOCK(); \ 4764 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ 4765 HWIO_INTFREE();\ 4766 } while (0) 4767 4768 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4769 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4770 4771 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// 4772 4773 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) 4774 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) 4775 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4776 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4777 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4778 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) 4779 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4780 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4781 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4782 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4783 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4784 do {\ 4785 HWIO_INTLOCK(); \ 4786 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4787 HWIO_INTFREE();\ 4788 } while (0) 4789 4790 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4791 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4792 4793 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4794 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4795 4796 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4797 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4798 4799 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// 4800 4801 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) 4802 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) 4803 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4804 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4805 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4806 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) 4807 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4808 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4809 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4810 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4811 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4812 do {\ 4813 HWIO_INTLOCK(); \ 4814 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4815 HWIO_INTFREE();\ 4816 } while (0) 4817 4818 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4819 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4820 4821 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4822 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4823 4824 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4825 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4826 4827 //// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// 4828 4829 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) 4830 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) 4831 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4832 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4833 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4834 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4835 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4836 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4837 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4838 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4839 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4840 do {\ 4841 HWIO_INTLOCK(); \ 4842 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4843 HWIO_INTFREE();\ 4844 } while (0) 4845 4846 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4847 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4848 4849 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// 4850 4851 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c) 4852 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c) 4853 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4854 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 4855 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ 4856 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) 4857 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 4858 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 4859 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 4860 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 4861 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4862 do {\ 4863 HWIO_INTLOCK(); \ 4864 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ 4865 HWIO_INTFREE();\ 4866 } while (0) 4867 4868 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4869 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4870 4871 //// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// 4872 4873 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0) 4874 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0) 4875 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4876 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 4877 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ 4878 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) 4879 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 4880 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 4881 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 4882 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 4883 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4884 do {\ 4885 HWIO_INTLOCK(); \ 4886 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ 4887 HWIO_INTFREE();\ 4888 } while (0) 4889 4890 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4891 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4892 4893 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4894 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4895 4896 //// Register REO_R0_REO2FW_RING_MSI1_DATA //// 4897 4898 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x000004a4) 4899 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x000004a4) 4900 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff 4901 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 4902 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ 4903 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) 4904 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ 4905 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 4906 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ 4907 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) 4908 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 4909 do {\ 4910 HWIO_INTLOCK(); \ 4911 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ 4912 HWIO_INTFREE();\ 4913 } while (0) 4914 4915 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4916 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 4917 4918 //// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// 4919 4920 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) 4921 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) 4922 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4923 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4924 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4925 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) 4926 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4927 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4928 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4929 out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4930 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4931 do {\ 4932 HWIO_INTLOCK(); \ 4933 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4934 HWIO_INTFREE();\ 4935 } while (0) 4936 4937 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4938 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4939 4940 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// 4941 4942 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000004ac) 4943 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000004ac) 4944 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff 4945 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 4946 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ 4947 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) 4948 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ 4949 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 4950 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ 4951 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) 4952 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ 4953 do {\ 4954 HWIO_INTLOCK(); \ 4955 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ 4956 HWIO_INTFREE();\ 4957 } while (0) 4958 4959 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4960 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4961 4962 //// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// 4963 4964 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000004b0) 4965 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000004b0) 4966 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff 4967 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 4968 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ 4969 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) 4970 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ 4971 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 4972 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ 4973 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) 4974 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ 4975 do {\ 4976 HWIO_INTLOCK(); \ 4977 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ 4978 HWIO_INTFREE();\ 4979 } while (0) 4980 4981 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4982 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4983 4984 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4985 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4986 4987 //// Register REO_R0_REO_RELEASE_RING_ID //// 4988 4989 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x000004b4) 4990 #define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x000004b4) 4991 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff 4992 #define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 4993 #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ 4994 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) 4995 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ 4996 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 4997 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ 4998 out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) 4999 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ 5000 do {\ 5001 HWIO_INTLOCK(); \ 5002 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ 5003 HWIO_INTFREE();\ 5004 } while (0) 5005 5006 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 5007 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 5008 5009 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5010 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 5011 5012 //// Register REO_R0_REO_RELEASE_RING_STATUS //// 5013 5014 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000004b8) 5015 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000004b8) 5016 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff 5017 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 5018 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ 5019 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) 5020 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ 5021 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 5022 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ 5023 out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) 5024 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ 5025 do {\ 5026 HWIO_INTLOCK(); \ 5027 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ 5028 HWIO_INTFREE();\ 5029 } while (0) 5030 5031 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5032 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5033 5034 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5035 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5036 5037 //// Register REO_R0_REO_RELEASE_RING_MISC //// 5038 5039 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000004bc) 5040 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000004bc) 5041 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff 5042 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 5043 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ 5044 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) 5045 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ 5046 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 5047 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ 5048 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) 5049 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ 5050 do {\ 5051 HWIO_INTLOCK(); \ 5052 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ 5053 HWIO_INTFREE();\ 5054 } while (0) 5055 5056 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5057 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 5058 5059 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5060 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe 5061 5062 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5063 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5064 5065 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5066 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5067 5068 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5069 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5070 5071 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5072 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 5073 5074 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5075 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5076 5077 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5078 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5079 5080 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5081 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5082 5083 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5084 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 5085 5086 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5087 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5088 5089 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5090 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5091 5092 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// 5093 5094 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) 5095 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) 5096 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff 5097 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 5098 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ 5099 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) 5100 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ 5101 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 5102 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ 5103 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) 5104 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5105 do {\ 5106 HWIO_INTLOCK(); \ 5107 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ 5108 HWIO_INTFREE();\ 5109 } while (0) 5110 5111 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5112 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5113 5114 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// 5115 5116 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) 5117 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) 5118 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff 5119 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 5120 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ 5121 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) 5122 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ 5123 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 5124 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ 5125 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) 5126 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5127 do {\ 5128 HWIO_INTLOCK(); \ 5129 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ 5130 HWIO_INTFREE();\ 5131 } while (0) 5132 5133 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5134 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5135 5136 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// 5137 5138 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) 5139 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) 5140 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5141 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 5142 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ 5143 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) 5144 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5145 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5146 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5147 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5148 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5149 do {\ 5150 HWIO_INTLOCK(); \ 5151 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ 5152 HWIO_INTFREE();\ 5153 } while (0) 5154 5155 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5156 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5157 5158 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5159 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5160 5161 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5162 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5163 5164 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// 5165 5166 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) 5167 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) 5168 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5169 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 5170 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ 5171 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) 5172 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5173 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5174 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5175 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5176 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5177 do {\ 5178 HWIO_INTLOCK(); \ 5179 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ 5180 HWIO_INTFREE();\ 5181 } while (0) 5182 5183 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5184 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5185 5186 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5187 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5188 5189 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5190 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5191 5192 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// 5193 5194 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) 5195 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) 5196 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5197 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 5198 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5199 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) 5200 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5201 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5202 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5203 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5204 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5205 do {\ 5206 HWIO_INTLOCK(); \ 5207 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5208 HWIO_INTFREE();\ 5209 } while (0) 5210 5211 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5212 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5213 5214 //// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB //// 5215 5216 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) 5217 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) 5218 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5219 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 5220 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ 5221 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK) 5222 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ 5223 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 5224 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ 5225 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) 5226 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5227 do {\ 5228 HWIO_INTLOCK(); \ 5229 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ 5230 HWIO_INTFREE();\ 5231 } while (0) 5232 5233 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5234 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5235 5236 //// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB //// 5237 5238 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) 5239 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) 5240 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5241 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 5242 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ 5243 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK) 5244 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ 5245 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 5246 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ 5247 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) 5248 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5249 do {\ 5250 HWIO_INTLOCK(); \ 5251 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ 5252 HWIO_INTFREE();\ 5253 } while (0) 5254 5255 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5256 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5257 5258 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5259 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5260 5261 //// Register REO_R0_REO_RELEASE_RING_MSI1_DATA //// 5262 5263 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) 5264 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) 5265 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff 5266 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0 5267 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ 5268 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK) 5269 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \ 5270 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 5271 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \ 5272 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val) 5273 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ 5274 do {\ 5275 HWIO_INTLOCK(); \ 5276 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \ 5277 HWIO_INTFREE();\ 5278 } while (0) 5279 5280 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5281 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 5282 5283 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// 5284 5285 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) 5286 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) 5287 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5288 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 5289 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ 5290 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) 5291 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5292 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5293 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5294 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5295 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5296 do {\ 5297 HWIO_INTLOCK(); \ 5298 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ 5299 HWIO_INTFREE();\ 5300 } while (0) 5301 5302 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5303 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5304 5305 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// 5306 5307 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000504) 5308 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000504) 5309 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff 5310 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 5311 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ 5312 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) 5313 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ 5314 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 5315 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ 5316 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) 5317 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 5318 do {\ 5319 HWIO_INTLOCK(); \ 5320 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ 5321 HWIO_INTFREE();\ 5322 } while (0) 5323 5324 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5325 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5326 5327 //// Register REO_R0_REO_STATUS_RING_BASE_MSB //// 5328 5329 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x00000508) 5330 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x00000508) 5331 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 5332 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 5333 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ 5334 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) 5335 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ 5336 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 5337 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ 5338 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) 5339 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 5340 do {\ 5341 HWIO_INTLOCK(); \ 5342 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ 5343 HWIO_INTFREE();\ 5344 } while (0) 5345 5346 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5347 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5348 5349 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5350 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5351 5352 //// Register REO_R0_REO_STATUS_RING_ID //// 5353 5354 #define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x0000050c) 5355 #define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x0000050c) 5356 #define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff 5357 #define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 5358 #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ 5359 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) 5360 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ 5361 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 5362 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ 5363 out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) 5364 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ 5365 do {\ 5366 HWIO_INTLOCK(); \ 5367 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ 5368 HWIO_INTFREE();\ 5369 } while (0) 5370 5371 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 5372 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 5373 5374 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5375 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 5376 5377 //// Register REO_R0_REO_STATUS_RING_STATUS //// 5378 5379 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x00000510) 5380 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x00000510) 5381 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff 5382 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 5383 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ 5384 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) 5385 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ 5386 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 5387 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ 5388 out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) 5389 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ 5390 do {\ 5391 HWIO_INTLOCK(); \ 5392 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ 5393 HWIO_INTFREE();\ 5394 } while (0) 5395 5396 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5397 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5398 5399 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5400 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5401 5402 //// Register REO_R0_REO_STATUS_RING_MISC //// 5403 5404 #define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x00000514) 5405 #define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x00000514) 5406 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff 5407 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 5408 #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ 5409 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) 5410 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ 5411 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 5412 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ 5413 out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) 5414 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ 5415 do {\ 5416 HWIO_INTLOCK(); \ 5417 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ 5418 HWIO_INTFREE();\ 5419 } while (0) 5420 5421 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5422 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 5423 5424 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5425 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 5426 5427 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5428 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5429 5430 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5431 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5432 5433 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5434 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5435 5436 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5437 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 5438 5439 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5440 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5441 5442 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5443 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5444 5445 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5446 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5447 5448 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5449 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 5450 5451 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5452 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5453 5454 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5455 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5456 5457 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// 5458 5459 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000518) 5460 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000518) 5461 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 5462 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 5463 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ 5464 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) 5465 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 5466 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 5467 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 5468 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 5469 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5470 do {\ 5471 HWIO_INTLOCK(); \ 5472 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 5473 HWIO_INTFREE();\ 5474 } while (0) 5475 5476 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5477 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5478 5479 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// 5480 5481 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000051c) 5482 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000051c) 5483 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 5484 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 5485 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ 5486 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) 5487 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 5488 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 5489 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 5490 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 5491 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5492 do {\ 5493 HWIO_INTLOCK(); \ 5494 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 5495 HWIO_INTFREE();\ 5496 } while (0) 5497 5498 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5499 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5500 5501 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// 5502 5503 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000528) 5504 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000528) 5505 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5506 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 5507 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 5508 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 5509 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5510 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5511 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5512 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5513 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5514 do {\ 5515 HWIO_INTLOCK(); \ 5516 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 5517 HWIO_INTFREE();\ 5518 } while (0) 5519 5520 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5521 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5522 5523 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5524 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5525 5526 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5527 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5528 5529 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// 5530 5531 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000052c) 5532 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000052c) 5533 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5534 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 5535 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 5536 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 5537 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5538 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5539 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5540 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5541 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5542 do {\ 5543 HWIO_INTLOCK(); \ 5544 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 5545 HWIO_INTFREE();\ 5546 } while (0) 5547 5548 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5549 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5550 5551 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5552 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5553 5554 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5555 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5556 5557 //// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// 5558 5559 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000530) 5560 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000530) 5561 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5562 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 5563 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5564 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 5565 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5566 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5567 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5568 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5569 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5570 do {\ 5571 HWIO_INTLOCK(); \ 5572 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5573 HWIO_INTFREE();\ 5574 } while (0) 5575 5576 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5577 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5578 5579 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// 5580 5581 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000054c) 5582 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000054c) 5583 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5584 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 5585 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 5586 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) 5587 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 5588 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 5589 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 5590 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 5591 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5592 do {\ 5593 HWIO_INTLOCK(); \ 5594 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 5595 HWIO_INTFREE();\ 5596 } while (0) 5597 5598 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5599 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5600 5601 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// 5602 5603 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000550) 5604 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000550) 5605 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5606 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 5607 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 5608 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) 5609 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 5610 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 5611 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 5612 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 5613 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5614 do {\ 5615 HWIO_INTLOCK(); \ 5616 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 5617 HWIO_INTFREE();\ 5618 } while (0) 5619 5620 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5621 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5622 5623 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5624 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5625 5626 //// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// 5627 5628 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x00000554) 5629 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x00000554) 5630 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 5631 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 5632 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ 5633 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) 5634 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ 5635 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 5636 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ 5637 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) 5638 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 5639 do {\ 5640 HWIO_INTLOCK(); \ 5641 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ 5642 HWIO_INTFREE();\ 5643 } while (0) 5644 5645 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5646 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 5647 5648 //// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// 5649 5650 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000558) 5651 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000558) 5652 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5653 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 5654 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 5655 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 5656 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5657 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5658 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5659 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5660 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5661 do {\ 5662 HWIO_INTLOCK(); \ 5663 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 5664 HWIO_INTFREE();\ 5665 } while (0) 5666 5667 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5668 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5669 5670 //// Register REO_R0_WATCHDOG_TIMEOUT //// 5671 5672 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000055c) 5673 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000055c) 5674 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff 5675 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 5676 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ 5677 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) 5678 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ 5679 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 5680 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ 5681 out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) 5682 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ 5683 do {\ 5684 HWIO_INTLOCK(); \ 5685 out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ 5686 HWIO_INTFREE();\ 5687 } while (0) 5688 5689 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000 5690 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc 5691 5692 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff 5693 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 5694 5695 //// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// 5696 5697 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000560) 5698 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000560) 5699 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff 5700 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 5701 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ 5702 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) 5703 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ 5704 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 5705 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ 5706 out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) 5707 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ 5708 do {\ 5709 HWIO_INTLOCK(); \ 5710 out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ 5711 HWIO_INTFREE();\ 5712 } while (0) 5713 5714 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff 5715 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 5716 5717 //// Register REO_R0_AGING_THRESHOLD_IX_0 //// 5718 5719 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x00000564) 5720 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x00000564) 5721 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff 5722 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 5723 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ 5724 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) 5725 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ 5726 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 5727 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ 5728 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) 5729 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ 5730 do {\ 5731 HWIO_INTLOCK(); \ 5732 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ 5733 HWIO_INTFREE();\ 5734 } while (0) 5735 5736 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff 5737 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 5738 5739 //// Register REO_R0_AGING_THRESHOLD_IX_1 //// 5740 5741 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000568) 5742 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000568) 5743 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff 5744 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 5745 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ 5746 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) 5747 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ 5748 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 5749 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ 5750 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) 5751 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ 5752 do {\ 5753 HWIO_INTLOCK(); \ 5754 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ 5755 HWIO_INTFREE();\ 5756 } while (0) 5757 5758 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff 5759 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 5760 5761 //// Register REO_R0_AGING_THRESHOLD_IX_2 //// 5762 5763 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x0000056c) 5764 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x0000056c) 5765 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff 5766 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 5767 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ 5768 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) 5769 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ 5770 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 5771 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ 5772 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) 5773 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ 5774 do {\ 5775 HWIO_INTLOCK(); \ 5776 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ 5777 HWIO_INTFREE();\ 5778 } while (0) 5779 5780 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff 5781 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 5782 5783 //// Register REO_R0_AGING_THRESHOLD_IX_3 //// 5784 5785 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000570) 5786 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000570) 5787 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff 5788 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 5789 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ 5790 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) 5791 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ 5792 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 5793 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ 5794 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) 5795 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ 5796 do {\ 5797 HWIO_INTLOCK(); \ 5798 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ 5799 HWIO_INTFREE();\ 5800 } while (0) 5801 5802 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff 5803 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 5804 5805 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// 5806 5807 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x00000574) 5808 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x00000574) 5809 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff 5810 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 5811 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ 5812 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) 5813 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ 5814 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 5815 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ 5816 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) 5817 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ 5818 do {\ 5819 HWIO_INTLOCK(); \ 5820 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ 5821 HWIO_INTFREE();\ 5822 } while (0) 5823 5824 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5825 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 5826 5827 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// 5828 5829 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000578) 5830 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000578) 5831 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff 5832 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 5833 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ 5834 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) 5835 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ 5836 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 5837 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ 5838 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) 5839 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ 5840 do {\ 5841 HWIO_INTLOCK(); \ 5842 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ 5843 HWIO_INTFREE();\ 5844 } while (0) 5845 5846 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 5847 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 5848 5849 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// 5850 5851 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x0000057c) 5852 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x0000057c) 5853 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff 5854 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 5855 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ 5856 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) 5857 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ 5858 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 5859 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ 5860 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) 5861 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ 5862 do {\ 5863 HWIO_INTLOCK(); \ 5864 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ 5865 HWIO_INTFREE();\ 5866 } while (0) 5867 5868 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 5869 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 5870 5871 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// 5872 5873 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000580) 5874 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000580) 5875 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff 5876 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 5877 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ 5878 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) 5879 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ 5880 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 5881 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ 5882 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) 5883 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ 5884 do {\ 5885 HWIO_INTLOCK(); \ 5886 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ 5887 HWIO_INTFREE();\ 5888 } while (0) 5889 5890 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 5891 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 5892 5893 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// 5894 5895 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x00000584) 5896 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x00000584) 5897 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff 5898 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 5899 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ 5900 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) 5901 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ 5902 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 5903 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ 5904 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) 5905 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ 5906 do {\ 5907 HWIO_INTLOCK(); \ 5908 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ 5909 HWIO_INTFREE();\ 5910 } while (0) 5911 5912 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5913 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 5914 5915 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// 5916 5917 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000588) 5918 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000588) 5919 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff 5920 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 5921 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ 5922 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) 5923 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ 5924 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 5925 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ 5926 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) 5927 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ 5928 do {\ 5929 HWIO_INTLOCK(); \ 5930 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ 5931 HWIO_INTFREE();\ 5932 } while (0) 5933 5934 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 5935 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 5936 5937 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// 5938 5939 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x0000058c) 5940 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x0000058c) 5941 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff 5942 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 5943 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ 5944 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) 5945 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ 5946 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 5947 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ 5948 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) 5949 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ 5950 do {\ 5951 HWIO_INTLOCK(); \ 5952 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ 5953 HWIO_INTFREE();\ 5954 } while (0) 5955 5956 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 5957 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 5958 5959 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// 5960 5961 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000590) 5962 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000590) 5963 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff 5964 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 5965 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ 5966 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) 5967 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ 5968 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 5969 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ 5970 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) 5971 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ 5972 do {\ 5973 HWIO_INTLOCK(); \ 5974 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ 5975 HWIO_INTFREE();\ 5976 } while (0) 5977 5978 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 5979 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 5980 5981 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// 5982 5983 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x00000594) 5984 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x00000594) 5985 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff 5986 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 5987 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ 5988 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) 5989 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ 5990 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 5991 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ 5992 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) 5993 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ 5994 do {\ 5995 HWIO_INTLOCK(); \ 5996 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ 5997 HWIO_INTFREE();\ 5998 } while (0) 5999 6000 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6001 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 6002 6003 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// 6004 6005 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000598) 6006 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000598) 6007 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff 6008 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 6009 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ 6010 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) 6011 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ 6012 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 6013 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ 6014 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) 6015 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ 6016 do {\ 6017 HWIO_INTLOCK(); \ 6018 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ 6019 HWIO_INTFREE();\ 6020 } while (0) 6021 6022 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6023 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 6024 6025 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// 6026 6027 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x0000059c) 6028 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x0000059c) 6029 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff 6030 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 6031 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ 6032 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) 6033 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ 6034 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 6035 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ 6036 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) 6037 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ 6038 do {\ 6039 HWIO_INTLOCK(); \ 6040 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ 6041 HWIO_INTFREE();\ 6042 } while (0) 6043 6044 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6045 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 6046 6047 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// 6048 6049 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x000005a0) 6050 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x000005a0) 6051 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff 6052 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 6053 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ 6054 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) 6055 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ 6056 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 6057 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ 6058 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) 6059 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ 6060 do {\ 6061 HWIO_INTLOCK(); \ 6062 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ 6063 HWIO_INTFREE();\ 6064 } while (0) 6065 6066 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6067 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 6068 6069 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// 6070 6071 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x000005a4) 6072 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x000005a4) 6073 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff 6074 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 6075 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ 6076 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) 6077 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ 6078 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 6079 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ 6080 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) 6081 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ 6082 do {\ 6083 HWIO_INTLOCK(); \ 6084 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ 6085 HWIO_INTFREE();\ 6086 } while (0) 6087 6088 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6089 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 6090 6091 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// 6092 6093 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x000005a8) 6094 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x000005a8) 6095 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff 6096 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 6097 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ 6098 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) 6099 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ 6100 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 6101 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ 6102 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) 6103 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ 6104 do {\ 6105 HWIO_INTLOCK(); \ 6106 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ 6107 HWIO_INTFREE();\ 6108 } while (0) 6109 6110 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6111 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 6112 6113 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// 6114 6115 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x000005ac) 6116 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x000005ac) 6117 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff 6118 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 6119 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ 6120 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) 6121 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ 6122 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 6123 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ 6124 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) 6125 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ 6126 do {\ 6127 HWIO_INTLOCK(); \ 6128 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ 6129 HWIO_INTFREE();\ 6130 } while (0) 6131 6132 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6133 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 6134 6135 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// 6136 6137 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x000005b0) 6138 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x000005b0) 6139 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff 6140 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 6141 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ 6142 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) 6143 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ 6144 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 6145 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ 6146 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) 6147 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ 6148 do {\ 6149 HWIO_INTLOCK(); \ 6150 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ 6151 HWIO_INTFREE();\ 6152 } while (0) 6153 6154 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6155 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 6156 6157 //// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// 6158 6159 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x000005b4) 6160 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x000005b4) 6161 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff 6162 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 6163 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ 6164 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) 6165 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ 6166 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 6167 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ 6168 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) 6169 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ 6170 do {\ 6171 HWIO_INTLOCK(); \ 6172 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ 6173 HWIO_INTFREE();\ 6174 } while (0) 6175 6176 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff 6177 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 6178 6179 //// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// 6180 6181 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x000005b8) 6182 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x000005b8) 6183 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff 6184 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 6185 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ 6186 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) 6187 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ 6188 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 6189 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ 6190 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) 6191 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ 6192 do {\ 6193 HWIO_INTLOCK(); \ 6194 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ 6195 HWIO_INTFREE();\ 6196 } while (0) 6197 6198 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff 6199 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 6200 6201 //// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// 6202 6203 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x000005bc) 6204 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x000005bc) 6205 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff 6206 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 6207 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ 6208 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) 6209 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ 6210 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 6211 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ 6212 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) 6213 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ 6214 do {\ 6215 HWIO_INTLOCK(); \ 6216 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ 6217 HWIO_INTFREE();\ 6218 } while (0) 6219 6220 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff 6221 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 6222 6223 //// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// 6224 6225 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x000005c0) 6226 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x000005c0) 6227 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff 6228 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 6229 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ 6230 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) 6231 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ 6232 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 6233 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ 6234 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) 6235 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ 6236 do {\ 6237 HWIO_INTLOCK(); \ 6238 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ 6239 HWIO_INTFREE();\ 6240 } while (0) 6241 6242 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff 6243 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 6244 6245 //// Register REO_R0_AGING_TIMESTAMP_IX_0 //// 6246 6247 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x000005c4) 6248 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x000005c4) 6249 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff 6250 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 6251 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ 6252 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) 6253 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ 6254 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 6255 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ 6256 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) 6257 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ 6258 do {\ 6259 HWIO_INTLOCK(); \ 6260 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ 6261 HWIO_INTFREE();\ 6262 } while (0) 6263 6264 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff 6265 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 6266 6267 //// Register REO_R0_AGING_TIMESTAMP_IX_1 //// 6268 6269 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x000005c8) 6270 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x000005c8) 6271 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff 6272 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 6273 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ 6274 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) 6275 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ 6276 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 6277 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ 6278 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) 6279 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ 6280 do {\ 6281 HWIO_INTLOCK(); \ 6282 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ 6283 HWIO_INTFREE();\ 6284 } while (0) 6285 6286 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff 6287 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 6288 6289 //// Register REO_R0_AGING_TIMESTAMP_IX_2 //// 6290 6291 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x000005cc) 6292 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x000005cc) 6293 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff 6294 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 6295 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ 6296 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) 6297 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ 6298 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 6299 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ 6300 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) 6301 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ 6302 do {\ 6303 HWIO_INTLOCK(); \ 6304 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ 6305 HWIO_INTFREE();\ 6306 } while (0) 6307 6308 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff 6309 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 6310 6311 //// Register REO_R0_AGING_TIMESTAMP_IX_3 //// 6312 6313 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x000005d0) 6314 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x000005d0) 6315 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff 6316 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 6317 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ 6318 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) 6319 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ 6320 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 6321 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ 6322 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) 6323 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ 6324 do {\ 6325 HWIO_INTLOCK(); \ 6326 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ 6327 HWIO_INTFREE();\ 6328 } while (0) 6329 6330 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff 6331 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 6332 6333 //// Register REO_R0_AGING_CONTROL //// 6334 6335 #define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x000005d4) 6336 #define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x000005d4) 6337 #define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f 6338 #define HWIO_REO_R0_AGING_CONTROL_SHFT 0 6339 #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ 6340 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) 6341 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ 6342 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 6343 #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ 6344 out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) 6345 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ 6346 do {\ 6347 HWIO_INTLOCK(); \ 6348 out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ 6349 HWIO_INTFREE();\ 6350 } while (0) 6351 6352 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f 6353 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 6354 6355 //// Register REO_R0_MISC_CTL //// 6356 6357 #define HWIO_REO_R0_MISC_CTL_ADDR(x) (x+0x000005d8) 6358 #define HWIO_REO_R0_MISC_CTL_PHYS(x) (x+0x000005d8) 6359 #define HWIO_REO_R0_MISC_CTL_RMSK 0x000fffff 6360 #define HWIO_REO_R0_MISC_CTL_SHFT 0 6361 #define HWIO_REO_R0_MISC_CTL_IN(x) \ 6362 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK) 6363 #define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ 6364 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask) 6365 #define HWIO_REO_R0_MISC_CTL_OUT(x, val) \ 6366 out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val) 6367 #define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ 6368 do {\ 6369 HWIO_INTLOCK(); \ 6370 out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \ 6371 HWIO_INTFREE();\ 6372 } while (0) 6373 6374 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x000e0000 6375 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 0x11 6376 6377 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x00010000 6378 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 0x10 6379 6380 #define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x00008000 6381 #define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 0xf 6382 6383 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x00007fff 6384 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0x0 6385 6386 //// Register REO_R0_HIGH_MEMORY_THRESHOLD //// 6387 6388 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x000005dc) 6389 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x000005dc) 6390 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff 6391 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 6392 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ 6393 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) 6394 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ 6395 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 6396 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ 6397 out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) 6398 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ 6399 do {\ 6400 HWIO_INTLOCK(); \ 6401 out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ 6402 HWIO_INTFREE();\ 6403 } while (0) 6404 6405 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff 6406 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 6407 6408 //// Register REO_R0_AC_BUFFERS_USED_IX_0 //// 6409 6410 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x000005e0) 6411 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x000005e0) 6412 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff 6413 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 6414 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ 6415 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) 6416 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ 6417 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 6418 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ 6419 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) 6420 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ 6421 do {\ 6422 HWIO_INTLOCK(); \ 6423 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ 6424 HWIO_INTFREE();\ 6425 } while (0) 6426 6427 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff 6428 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 6429 6430 //// Register REO_R0_AC_BUFFERS_USED_IX_1 //// 6431 6432 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x000005e4) 6433 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x000005e4) 6434 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff 6435 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 6436 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ 6437 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) 6438 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ 6439 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 6440 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ 6441 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) 6442 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ 6443 do {\ 6444 HWIO_INTLOCK(); \ 6445 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ 6446 HWIO_INTFREE();\ 6447 } while (0) 6448 6449 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff 6450 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 6451 6452 //// Register REO_R0_AC_BUFFERS_USED_IX_2 //// 6453 6454 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x000005e8) 6455 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x000005e8) 6456 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff 6457 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 6458 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ 6459 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) 6460 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ 6461 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 6462 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ 6463 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) 6464 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ 6465 do {\ 6466 HWIO_INTLOCK(); \ 6467 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ 6468 HWIO_INTFREE();\ 6469 } while (0) 6470 6471 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff 6472 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 6473 6474 //// Register REO_R0_AC_BUFFERS_USED_IX_3 //// 6475 6476 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x000005ec) 6477 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x000005ec) 6478 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff 6479 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 6480 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ 6481 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) 6482 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ 6483 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 6484 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ 6485 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) 6486 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ 6487 do {\ 6488 HWIO_INTLOCK(); \ 6489 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ 6490 HWIO_INTFREE();\ 6491 } while (0) 6492 6493 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff 6494 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 6495 6496 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// 6497 6498 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x000005f0) 6499 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x000005f0) 6500 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff 6501 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 6502 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ 6503 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) 6504 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ 6505 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 6506 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ 6507 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) 6508 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ 6509 do {\ 6510 HWIO_INTLOCK(); \ 6511 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ 6512 HWIO_INTFREE();\ 6513 } while (0) 6514 6515 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff 6516 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 6517 6518 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// 6519 6520 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x000005f4) 6521 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x000005f4) 6522 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff 6523 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 6524 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ 6525 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) 6526 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ 6527 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 6528 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ 6529 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) 6530 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ 6531 do {\ 6532 HWIO_INTLOCK(); \ 6533 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ 6534 HWIO_INTFREE();\ 6535 } while (0) 6536 6537 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff 6538 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 6539 6540 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// 6541 6542 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x000005f8) 6543 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x000005f8) 6544 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff 6545 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 6546 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ 6547 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) 6548 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ 6549 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 6550 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ 6551 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) 6552 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ 6553 do {\ 6554 HWIO_INTLOCK(); \ 6555 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ 6556 HWIO_INTFREE();\ 6557 } while (0) 6558 6559 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff 6560 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 6561 6562 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// 6563 6564 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005fc) 6565 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005fc) 6566 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff 6567 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 6568 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ 6569 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) 6570 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ 6571 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 6572 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ 6573 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) 6574 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ 6575 do {\ 6576 HWIO_INTLOCK(); \ 6577 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ 6578 HWIO_INTFREE();\ 6579 } while (0) 6580 6581 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff 6582 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 6583 6584 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// 6585 6586 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x00000600) 6587 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x00000600) 6588 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff 6589 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 6590 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ 6591 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) 6592 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ 6593 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 6594 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ 6595 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) 6596 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ 6597 do {\ 6598 HWIO_INTLOCK(); \ 6599 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ 6600 HWIO_INTFREE();\ 6601 } while (0) 6602 6603 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff 6604 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 6605 6606 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// 6607 6608 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x00000604) 6609 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x00000604) 6610 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff 6611 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 6612 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ 6613 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) 6614 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ 6615 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 6616 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ 6617 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) 6618 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ 6619 do {\ 6620 HWIO_INTLOCK(); \ 6621 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ 6622 HWIO_INTFREE();\ 6623 } while (0) 6624 6625 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff 6626 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 6627 6628 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// 6629 6630 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x00000608) 6631 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x00000608) 6632 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff 6633 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 6634 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ 6635 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) 6636 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ 6637 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 6638 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ 6639 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) 6640 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ 6641 do {\ 6642 HWIO_INTLOCK(); \ 6643 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ 6644 HWIO_INTFREE();\ 6645 } while (0) 6646 6647 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff 6648 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 6649 6650 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// 6651 6652 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x0000060c) 6653 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x0000060c) 6654 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 6655 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 6656 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ 6657 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) 6658 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ 6659 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 6660 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ 6661 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) 6662 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ 6663 do {\ 6664 HWIO_INTLOCK(); \ 6665 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ 6666 HWIO_INTFREE();\ 6667 } while (0) 6668 6669 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 6670 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 6671 6672 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// 6673 6674 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x00000610) 6675 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x00000610) 6676 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff 6677 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 6678 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ 6679 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) 6680 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ 6681 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 6682 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ 6683 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) 6684 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ 6685 do {\ 6686 HWIO_INTLOCK(); \ 6687 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ 6688 HWIO_INTFREE();\ 6689 } while (0) 6690 6691 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff 6692 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 6693 6694 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// 6695 6696 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x00000614) 6697 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x00000614) 6698 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff 6699 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 6700 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ 6701 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) 6702 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ 6703 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 6704 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ 6705 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) 6706 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ 6707 do {\ 6708 HWIO_INTLOCK(); \ 6709 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ 6710 HWIO_INTFREE();\ 6711 } while (0) 6712 6713 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff 6714 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 6715 6716 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// 6717 6718 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x00000618) 6719 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x00000618) 6720 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff 6721 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 6722 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ 6723 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) 6724 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ 6725 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 6726 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ 6727 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) 6728 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ 6729 do {\ 6730 HWIO_INTLOCK(); \ 6731 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ 6732 HWIO_INTFREE();\ 6733 } while (0) 6734 6735 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff 6736 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 6737 6738 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// 6739 6740 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x0000061c) 6741 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x0000061c) 6742 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff 6743 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 6744 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ 6745 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) 6746 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ 6747 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 6748 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ 6749 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) 6750 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ 6751 do {\ 6752 HWIO_INTLOCK(); \ 6753 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ 6754 HWIO_INTFREE();\ 6755 } while (0) 6756 6757 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff 6758 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 6759 6760 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// 6761 6762 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x00000620) 6763 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x00000620) 6764 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff 6765 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 6766 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ 6767 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) 6768 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ 6769 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 6770 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ 6771 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) 6772 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ 6773 do {\ 6774 HWIO_INTLOCK(); \ 6775 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ 6776 HWIO_INTFREE();\ 6777 } while (0) 6778 6779 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff 6780 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 6781 6782 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// 6783 6784 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x00000624) 6785 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x00000624) 6786 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff 6787 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 6788 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ 6789 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) 6790 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ 6791 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 6792 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ 6793 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) 6794 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ 6795 do {\ 6796 HWIO_INTLOCK(); \ 6797 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ 6798 HWIO_INTFREE();\ 6799 } while (0) 6800 6801 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff 6802 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 6803 6804 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// 6805 6806 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x00000628) 6807 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x00000628) 6808 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff 6809 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 6810 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ 6811 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) 6812 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ 6813 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 6814 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ 6815 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) 6816 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ 6817 do {\ 6818 HWIO_INTLOCK(); \ 6819 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ 6820 HWIO_INTFREE();\ 6821 } while (0) 6822 6823 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff 6824 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 6825 6826 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// 6827 6828 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x0000062c) 6829 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x0000062c) 6830 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff 6831 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 6832 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ 6833 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) 6834 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ 6835 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 6836 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ 6837 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) 6838 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ 6839 do {\ 6840 HWIO_INTLOCK(); \ 6841 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ 6842 HWIO_INTFREE();\ 6843 } while (0) 6844 6845 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff 6846 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 6847 6848 //// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// 6849 6850 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x00000630) 6851 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x00000630) 6852 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f 6853 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 6854 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ 6855 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) 6856 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ 6857 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 6858 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ 6859 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) 6860 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ 6861 do {\ 6862 HWIO_INTLOCK(); \ 6863 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ 6864 HWIO_INTFREE();\ 6865 } while (0) 6866 6867 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 6868 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 6869 6870 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f 6871 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 6872 6873 //// Register REO_R0_GXI_TESTBUS_LOWER //// 6874 6875 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000654) 6876 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000654) 6877 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 6878 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 6879 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ 6880 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) 6881 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 6882 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 6883 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 6884 out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 6885 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 6886 do {\ 6887 HWIO_INTLOCK(); \ 6888 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ 6889 HWIO_INTFREE();\ 6890 } while (0) 6891 6892 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 6893 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 6894 6895 //// Register REO_R0_GXI_TESTBUS_UPPER //// 6896 6897 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000658) 6898 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000658) 6899 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 6900 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 6901 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ 6902 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) 6903 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 6904 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 6905 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 6906 out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 6907 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 6908 do {\ 6909 HWIO_INTLOCK(); \ 6910 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ 6911 HWIO_INTFREE();\ 6912 } while (0) 6913 6914 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 6915 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 6916 6917 //// Register REO_R0_GXI_SM_STATES_IX_0 //// 6918 6919 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000065c) 6920 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000065c) 6921 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 6922 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 6923 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ 6924 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) 6925 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 6926 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 6927 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 6928 out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 6929 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 6930 do {\ 6931 HWIO_INTLOCK(); \ 6932 out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ 6933 HWIO_INTFREE();\ 6934 } while (0) 6935 6936 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 6937 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 6938 6939 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 6940 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 6941 6942 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 6943 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 6944 6945 //// Register REO_R0_GXI_END_OF_TEST_CHECK //// 6946 6947 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000660) 6948 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000660) 6949 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 6950 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 6951 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 6952 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) 6953 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 6954 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 6955 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 6956 out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 6957 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6958 do {\ 6959 HWIO_INTLOCK(); \ 6960 out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 6961 HWIO_INTFREE();\ 6962 } while (0) 6963 6964 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6965 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6966 6967 //// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// 6968 6969 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000664) 6970 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000664) 6971 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 6972 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 6973 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 6974 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 6975 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 6976 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 6977 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 6978 out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 6979 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 6980 do {\ 6981 HWIO_INTLOCK(); \ 6982 out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 6983 HWIO_INTFREE();\ 6984 } while (0) 6985 6986 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 6987 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 6988 6989 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 6990 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 6991 6992 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 6993 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 6994 6995 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 6996 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 6997 6998 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 6999 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 7000 7001 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 7002 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 7003 7004 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 7005 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 7006 7007 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 7008 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 7009 7010 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 7011 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 7012 7013 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 7014 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 7015 7016 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 7017 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 7018 7019 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 7020 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 7021 7022 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 7023 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 7024 7025 //// Register REO_R0_GXI_GXI_ERR_INTS //// 7026 7027 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000668) 7028 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000668) 7029 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 7030 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 7031 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ 7032 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) 7033 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 7034 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 7035 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 7036 out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 7037 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 7038 do {\ 7039 HWIO_INTLOCK(); \ 7040 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ 7041 HWIO_INTFREE();\ 7042 } while (0) 7043 7044 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 7045 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 7046 7047 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 7048 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 7049 7050 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 7051 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 7052 7053 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 7054 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 7055 7056 //// Register REO_R0_GXI_GXI_ERR_STATS //// 7057 7058 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000066c) 7059 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000066c) 7060 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 7061 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 7062 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ 7063 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) 7064 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 7065 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 7066 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 7067 out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 7068 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 7069 do {\ 7070 HWIO_INTLOCK(); \ 7071 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ 7072 HWIO_INTFREE();\ 7073 } while (0) 7074 7075 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 7076 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 7077 7078 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 7079 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 7080 7081 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 7082 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 7083 7084 //// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// 7085 7086 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000670) 7087 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000670) 7088 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 7089 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 7090 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 7091 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 7092 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 7093 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 7094 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 7095 out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 7096 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 7097 do {\ 7098 HWIO_INTLOCK(); \ 7099 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 7100 HWIO_INTFREE();\ 7101 } while (0) 7102 7103 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 7104 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 7105 7106 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7107 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 7108 7109 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 7110 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 7111 7112 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 7113 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 7114 7115 //// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// 7116 7117 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000674) 7118 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000674) 7119 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 7120 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 7121 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 7122 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 7123 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 7124 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 7125 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 7126 out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 7127 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 7128 do {\ 7129 HWIO_INTLOCK(); \ 7130 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 7131 HWIO_INTFREE();\ 7132 } while (0) 7133 7134 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 7135 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 7136 7137 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7138 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 7139 7140 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 7141 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 7142 7143 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 7144 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 7145 7146 //// Register REO_R0_GXI_GXI_MISC_CONTROL //// 7147 7148 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000678) 7149 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000678) 7150 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 7151 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 7152 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 7153 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) 7154 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 7155 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 7156 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 7157 out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 7158 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 7159 do {\ 7160 HWIO_INTLOCK(); \ 7161 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 7162 HWIO_INTFREE();\ 7163 } while (0) 7164 7165 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 7166 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 7167 7168 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 7169 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 7170 7171 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 7172 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 7173 7174 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 7175 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 7176 7177 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 7178 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 7179 7180 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 7181 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 7182 7183 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 7184 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 7185 7186 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 7187 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 7188 7189 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 7190 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 7191 7192 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 7193 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 7194 7195 //// Register REO_R0_GXI_GXI_WDOG_CONTROL //// 7196 7197 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000067c) 7198 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000067c) 7199 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 7200 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 7201 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 7202 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) 7203 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 7204 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 7205 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 7206 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 7207 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 7208 do {\ 7209 HWIO_INTLOCK(); \ 7210 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 7211 HWIO_INTFREE();\ 7212 } while (0) 7213 7214 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 7215 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 7216 7217 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 7218 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 7219 7220 //// Register REO_R0_GXI_GXI_WDOG_STATUS //// 7221 7222 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000680) 7223 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000680) 7224 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 7225 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 7226 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 7227 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) 7228 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 7229 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 7230 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 7231 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 7232 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 7233 do {\ 7234 HWIO_INTLOCK(); \ 7235 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 7236 HWIO_INTFREE();\ 7237 } while (0) 7238 7239 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 7240 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 7241 7242 //// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// 7243 7244 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000684) 7245 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000684) 7246 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 7247 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 7248 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 7249 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 7250 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 7251 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 7252 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 7253 out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 7254 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 7255 do {\ 7256 HWIO_INTLOCK(); \ 7257 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 7258 HWIO_INTFREE();\ 7259 } while (0) 7260 7261 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 7262 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 7263 7264 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 7265 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 7266 7267 //// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL //// 7268 7269 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000688) 7270 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000688) 7271 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 7272 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 7273 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 7274 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 7275 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 7276 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 7277 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 7278 out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 7279 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 7280 do {\ 7281 HWIO_INTLOCK(); \ 7282 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 7283 HWIO_INTFREE();\ 7284 } while (0) 7285 7286 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 7287 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 7288 7289 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 7290 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 7291 7292 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 7293 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 7294 7295 //// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL //// 7296 7297 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x0000068c) 7298 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x0000068c) 7299 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 7300 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 7301 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 7302 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 7303 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 7304 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 7305 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 7306 out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 7307 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 7308 do {\ 7309 HWIO_INTLOCK(); \ 7310 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 7311 HWIO_INTFREE();\ 7312 } while (0) 7313 7314 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 7315 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 7316 7317 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 7318 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 7319 7320 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 7321 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 7322 7323 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// 7324 7325 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000690) 7326 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000690) 7327 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 7328 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 7329 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ 7330 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 7331 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 7332 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 7333 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 7334 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 7335 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 7336 do {\ 7337 HWIO_INTLOCK(); \ 7338 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ 7339 HWIO_INTFREE();\ 7340 } while (0) 7341 7342 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 7343 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 7344 7345 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// 7346 7347 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000694) 7348 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000694) 7349 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 7350 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 7351 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ 7352 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 7353 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 7354 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 7355 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 7356 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 7357 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 7358 do {\ 7359 HWIO_INTLOCK(); \ 7360 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ 7361 HWIO_INTFREE();\ 7362 } while (0) 7363 7364 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 7365 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 7366 7367 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// 7368 7369 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000698) 7370 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000698) 7371 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 7372 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 7373 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ 7374 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 7375 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 7376 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 7377 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 7378 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 7379 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 7380 do {\ 7381 HWIO_INTLOCK(); \ 7382 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ 7383 HWIO_INTFREE();\ 7384 } while (0) 7385 7386 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 7387 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 7388 7389 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// 7390 7391 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x0000069c) 7392 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x0000069c) 7393 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 7394 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 7395 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ 7396 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 7397 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 7398 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 7399 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 7400 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 7401 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 7402 do {\ 7403 HWIO_INTLOCK(); \ 7404 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ 7405 HWIO_INTFREE();\ 7406 } while (0) 7407 7408 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 7409 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 7410 7411 //// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL //// 7412 7413 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000006a0) 7414 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000006a0) 7415 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f 7416 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 7417 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ 7418 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) 7419 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ 7420 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 7421 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ 7422 out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) 7423 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ 7424 do {\ 7425 HWIO_INTLOCK(); \ 7426 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ 7427 HWIO_INTFREE();\ 7428 } while (0) 7429 7430 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 7431 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf 7432 7433 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 7434 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 7435 7436 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 7437 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 7438 7439 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f 7440 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 7441 7442 //// Register REO_R0_CACHE_CTL_CONFIG //// 7443 7444 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x000006a4) 7445 #define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x000006a4) 7446 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff 7447 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 7448 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ 7449 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) 7450 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ 7451 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 7452 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ 7453 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) 7454 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ 7455 do {\ 7456 HWIO_INTLOCK(); \ 7457 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ 7458 HWIO_INTFREE();\ 7459 } while (0) 7460 7461 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 7462 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x18 7463 7464 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00800000 7465 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x17 7466 7467 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00400000 7468 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x16 7469 7470 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00200000 7471 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x15 7472 7473 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00100000 7474 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x14 7475 7476 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00080000 7477 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x13 7478 7479 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00040000 7480 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x12 7481 7482 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00020000 7483 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x11 7484 7485 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x0001fe00 7486 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x9 7487 7488 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000001ff 7489 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 7490 7491 //// Register REO_R0_CACHE_CTL_CONTROL //// 7492 7493 #define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x000006a8) 7494 #define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x000006a8) 7495 #define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000003 7496 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 7497 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ 7498 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) 7499 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ 7500 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 7501 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ 7502 out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) 7503 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ 7504 do {\ 7505 HWIO_INTLOCK(); \ 7506 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ 7507 HWIO_INTFREE();\ 7508 } while (0) 7509 7510 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002 7511 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 0x1 7512 7513 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 7514 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 7515 7516 //// Register REO_R0_CACHE_CTL_CONFIG_SET //// 7517 7518 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) (x+0x000006ac) 7519 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) (x+0x000006ac) 7520 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x01ffffff 7521 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT 0 7522 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ 7523 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK) 7524 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \ 7525 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask) 7526 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val) \ 7527 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val) 7528 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \ 7529 do {\ 7530 HWIO_INTLOCK(); \ 7531 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \ 7532 HWIO_INTFREE();\ 7533 } while (0) 7534 7535 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x01ffffff 7536 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0x0 7537 7538 //// Register REO_R0_CACHE_CTL_SET_SIZE //// 7539 7540 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) (x+0x000006b0) 7541 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) (x+0x000006b0) 7542 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x000001ff 7543 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT 0 7544 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ 7545 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK) 7546 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \ 7547 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask) 7548 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val) \ 7549 out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val) 7550 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \ 7551 do {\ 7552 HWIO_INTLOCK(); \ 7553 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \ 7554 HWIO_INTFREE();\ 7555 } while (0) 7556 7557 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x000001ff 7558 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0x0 7559 7560 //// Register REO_R0_CLK_GATE_CTRL //// 7561 7562 #define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x000006b4) 7563 #define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x000006b4) 7564 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff 7565 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 7566 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ 7567 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) 7568 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ 7569 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 7570 #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ 7571 out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) 7572 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ 7573 do {\ 7574 HWIO_INTLOCK(); \ 7575 out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ 7576 HWIO_INTFREE();\ 7577 } while (0) 7578 7579 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 7580 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 7581 7582 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 7583 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 7584 7585 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 7586 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 7587 7588 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 7589 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf 7590 7591 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 7592 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe 7593 7594 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 7595 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd 7596 7597 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x00001000 7598 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 0xc 7599 7600 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x00000800 7601 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 0xb 7602 7603 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 7604 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa 7605 7606 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff 7607 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 7608 7609 //// Register REO_R0_EVENTMASK_IX_0 //// 7610 7611 #define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x000006b8) 7612 #define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x000006b8) 7613 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff 7614 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 7615 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ 7616 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) 7617 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ 7618 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 7619 #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ 7620 out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) 7621 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ 7622 do {\ 7623 HWIO_INTLOCK(); \ 7624 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ 7625 HWIO_INTFREE();\ 7626 } while (0) 7627 7628 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 7629 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 7630 7631 //// Register REO_R0_EVENTMASK_IX_1 //// 7632 7633 #define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x000006bc) 7634 #define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x000006bc) 7635 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff 7636 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 7637 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ 7638 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) 7639 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ 7640 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 7641 #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ 7642 out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) 7643 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ 7644 do {\ 7645 HWIO_INTLOCK(); \ 7646 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ 7647 HWIO_INTFREE();\ 7648 } while (0) 7649 7650 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 7651 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 7652 7653 //// Register REO_R0_EVENTMASK_IX_2 //// 7654 7655 #define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x000006c0) 7656 #define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x000006c0) 7657 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff 7658 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 7659 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ 7660 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) 7661 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ 7662 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 7663 #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ 7664 out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) 7665 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ 7666 do {\ 7667 HWIO_INTLOCK(); \ 7668 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ 7669 HWIO_INTFREE();\ 7670 } while (0) 7671 7672 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff 7673 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 7674 7675 //// Register REO_R0_EVENTMASK_IX_3 //// 7676 7677 #define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x000006c4) 7678 #define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x000006c4) 7679 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff 7680 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 7681 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ 7682 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) 7683 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ 7684 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 7685 #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ 7686 out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) 7687 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ 7688 do {\ 7689 HWIO_INTLOCK(); \ 7690 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ 7691 HWIO_INTFREE();\ 7692 } while (0) 7693 7694 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff 7695 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 7696 7697 //// Register REO_R1_MISC_DEBUG_CTRL //// 7698 7699 #define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) 7700 #define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) 7701 #define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff 7702 #define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 7703 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ 7704 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) 7705 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ 7706 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 7707 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ 7708 out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) 7709 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ 7710 do {\ 7711 HWIO_INTLOCK(); \ 7712 out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ 7713 HWIO_INTFREE();\ 7714 } while (0) 7715 7716 #define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000 7717 #define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 0x1f 7718 7719 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 7720 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 0x1e 7721 7722 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 7723 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 7724 7725 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 7726 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa 7727 7728 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff 7729 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 7730 7731 //// Register REO_R1_MISC_PERF_DEBUG_CTRL //// 7732 7733 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) 7734 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) 7735 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff 7736 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 7737 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ 7738 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) 7739 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ 7740 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 7741 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ 7742 out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) 7743 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ 7744 do {\ 7745 HWIO_INTLOCK(); \ 7746 out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ 7747 HWIO_INTFREE();\ 7748 } while (0) 7749 7750 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 7751 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc 7752 7753 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff 7754 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 7755 7756 //// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// 7757 7758 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) 7759 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) 7760 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x00000fff 7761 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 7762 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ 7763 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) 7764 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ 7765 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 7766 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ 7767 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) 7768 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ 7769 do {\ 7770 HWIO_INTLOCK(); \ 7771 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ 7772 HWIO_INTFREE();\ 7773 } while (0) 7774 7775 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000800 7776 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0xb 7777 7778 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000400 7779 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0xa 7780 7781 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000200 7782 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x9 7783 7784 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x000001ff 7785 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 7786 7787 //// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// 7788 7789 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) 7790 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) 7791 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff 7792 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 7793 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ 7794 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) 7795 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ 7796 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 7797 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ 7798 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) 7799 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ 7800 do {\ 7801 HWIO_INTLOCK(); \ 7802 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ 7803 HWIO_INTFREE();\ 7804 } while (0) 7805 7806 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff 7807 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 7808 7809 //// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// 7810 7811 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) 7812 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) 7813 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff 7814 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 7815 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ 7816 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) 7817 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ 7818 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 7819 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ 7820 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) 7821 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ 7822 do {\ 7823 HWIO_INTLOCK(); \ 7824 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ 7825 HWIO_INTFREE();\ 7826 } while (0) 7827 7828 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff 7829 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 7830 7831 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// 7832 7833 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) 7834 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) 7835 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff 7836 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 7837 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ 7838 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) 7839 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ 7840 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 7841 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ 7842 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) 7843 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ 7844 do {\ 7845 HWIO_INTLOCK(); \ 7846 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ 7847 HWIO_INTFREE();\ 7848 } while (0) 7849 7850 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff 7851 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 7852 7853 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// 7854 7855 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) 7856 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) 7857 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff 7858 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 7859 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ 7860 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) 7861 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ 7862 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 7863 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ 7864 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) 7865 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ 7866 do {\ 7867 HWIO_INTLOCK(); \ 7868 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ 7869 HWIO_INTFREE();\ 7870 } while (0) 7871 7872 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff 7873 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 7874 7875 //// Register REO_R1_CACHE_CTL_DEBUG_STM //// 7876 7877 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) 7878 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) 7879 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff 7880 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 7881 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ 7882 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) 7883 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ 7884 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 7885 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ 7886 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) 7887 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ 7888 do {\ 7889 HWIO_INTLOCK(); \ 7890 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ 7891 HWIO_INTFREE();\ 7892 } while (0) 7893 7894 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff 7895 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 7896 7897 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// 7898 7899 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) 7900 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) 7901 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x0007ffff 7902 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 7903 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ 7904 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) 7905 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ 7906 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 7907 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ 7908 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) 7909 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ 7910 do {\ 7911 HWIO_INTLOCK(); \ 7912 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ 7913 HWIO_INTFREE();\ 7914 } while (0) 7915 7916 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0007fc00 7917 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0xa 7918 7919 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000003ff 7920 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 7921 7922 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 //// 7923 7924 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) (x+0x00002024) 7925 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) (x+0x00002024) 7926 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x0007ffff 7927 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT 0 7928 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ 7929 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK) 7930 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \ 7931 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask) 7932 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val) \ 7933 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val) 7934 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \ 7935 do {\ 7936 HWIO_INTLOCK(); \ 7937 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \ 7938 HWIO_INTFREE();\ 7939 } while (0) 7940 7941 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x0007fc00 7942 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 0xa 7943 7944 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x000003ff 7945 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0x0 7946 7947 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 //// 7948 7949 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) (x+0x00002028) 7950 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) (x+0x00002028) 7951 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x0007ffff 7952 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT 0 7953 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ 7954 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK) 7955 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \ 7956 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask) 7957 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val) \ 7958 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val) 7959 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \ 7960 do {\ 7961 HWIO_INTLOCK(); \ 7962 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \ 7963 HWIO_INTFREE();\ 7964 } while (0) 7965 7966 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x0007fc00 7967 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 0xa 7968 7969 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x000003ff 7970 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0x0 7971 7972 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 //// 7973 7974 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) (x+0x0000202c) 7975 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) (x+0x0000202c) 7976 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x0007ffff 7977 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT 0 7978 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ 7979 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK) 7980 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \ 7981 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask) 7982 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val) \ 7983 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val) 7984 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \ 7985 do {\ 7986 HWIO_INTLOCK(); \ 7987 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \ 7988 HWIO_INTFREE();\ 7989 } while (0) 7990 7991 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x0007fc00 7992 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 0xa 7993 7994 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x000003ff 7995 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0x0 7996 7997 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW //// 7998 7999 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) (x+0x00002030) 8000 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) (x+0x00002030) 8001 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff 8002 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT 0 8003 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ 8004 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK) 8005 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ 8006 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask) 8007 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val) \ 8008 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val) 8009 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ 8010 do {\ 8011 HWIO_INTLOCK(); \ 8012 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \ 8013 HWIO_INTFREE();\ 8014 } while (0) 8015 8016 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff 8017 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0x0 8018 8019 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH //// 8020 8021 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) (x+0x00002034) 8022 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) (x+0x00002034) 8023 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff 8024 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT 0 8025 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ 8026 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK) 8027 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ 8028 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask) 8029 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val) \ 8030 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val) 8031 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ 8032 do {\ 8033 HWIO_INTLOCK(); \ 8034 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \ 8035 HWIO_INTFREE();\ 8036 } while (0) 8037 8038 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff 8039 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0x0 8040 8041 //// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER //// 8042 8043 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) (x+0x00002038) 8044 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) (x+0x00002038) 8045 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0x000fffff 8046 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT 0 8047 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ 8048 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK) 8049 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \ 8050 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) 8051 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val) \ 8052 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val) 8053 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \ 8054 do {\ 8055 HWIO_INTLOCK(); \ 8056 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \ 8057 HWIO_INTFREE();\ 8058 } while (0) 8059 8060 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0x000ffc00 8061 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 0xa 8062 8063 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x000003ff 8064 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0x0 8065 8066 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// 8067 8068 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x0000203c) 8069 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x0000203c) 8070 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 8071 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 8072 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ 8073 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) 8074 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ 8075 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 8076 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ 8077 out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) 8078 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 8079 do {\ 8080 HWIO_INTLOCK(); \ 8081 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ 8082 HWIO_INTFREE();\ 8083 } while (0) 8084 8085 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 8086 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 8087 8088 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 //// 8089 8090 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) (x+0x00002040) 8091 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) (x+0x00002040) 8092 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x000007ff 8093 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_SHFT 0 8094 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ 8095 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK) 8096 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask) \ 8097 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask) 8098 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, val) \ 8099 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), val) 8100 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \ 8101 do {\ 8102 HWIO_INTLOCK(); \ 8103 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)); \ 8104 HWIO_INTFREE();\ 8105 } while (0) 8106 8107 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x000007f8 8108 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 0x3 8109 8110 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x00000004 8111 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 0x2 8112 8113 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x00000002 8114 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 0x1 8115 8116 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x00000001 8117 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0x0 8118 8119 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 //// 8120 8121 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) (x+0x00002044) 8122 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) (x+0x00002044) 8123 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff 8124 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_SHFT 0 8125 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ 8126 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK) 8127 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask) \ 8128 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask) 8129 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, val) \ 8130 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), val) 8131 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \ 8132 do {\ 8133 HWIO_INTLOCK(); \ 8134 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)); \ 8135 HWIO_INTFREE();\ 8136 } while (0) 8137 8138 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff 8139 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0x0 8140 8141 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 //// 8142 8143 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) (x+0x00002048) 8144 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) (x+0x00002048) 8145 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0x000000ff 8146 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_SHFT 0 8147 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ 8148 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK) 8149 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask) \ 8150 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask) 8151 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, val) \ 8152 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), val) 8153 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \ 8154 do {\ 8155 HWIO_INTLOCK(); \ 8156 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)); \ 8157 HWIO_INTFREE();\ 8158 } while (0) 8159 8160 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0x000000ff 8161 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0x0 8162 8163 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS //// 8164 8165 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) (x+0x0000204c) 8166 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) (x+0x0000204c) 8167 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff 8168 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_SHFT 0 8169 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ 8170 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK) 8171 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask) \ 8172 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask) 8173 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUT(x, val) \ 8174 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), val) 8175 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val) \ 8176 do {\ 8177 HWIO_INTLOCK(); \ 8178 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)); \ 8179 HWIO_INTFREE();\ 8180 } while (0) 8181 8182 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 8183 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 0x16 8184 8185 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x003ff000 8186 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 0xc 8187 8188 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x00000800 8189 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 0xb 8190 8191 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x00000600 8192 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 0x9 8193 8194 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x000001e0 8195 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 0x5 8196 8197 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x0000001c 8198 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 0x2 8199 8200 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x00000002 8201 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 0x1 8202 8203 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x00000001 8204 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0x0 8205 8206 //// Register REO_R1_END_OF_TEST_CHECK //// 8207 8208 #define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002050) 8209 #define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002050) 8210 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 8211 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 8212 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ 8213 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) 8214 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ 8215 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 8216 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ 8217 out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) 8218 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 8219 do {\ 8220 HWIO_INTLOCK(); \ 8221 out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ 8222 HWIO_INTFREE();\ 8223 } while (0) 8224 8225 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 8226 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 8227 8228 //// Register REO_R1_SM_ALL_IDLE //// 8229 8230 #define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002054) 8231 #define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002054) 8232 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 8233 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 8234 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ 8235 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) 8236 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ 8237 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 8238 #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ 8239 out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) 8240 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ 8241 do {\ 8242 HWIO_INTLOCK(); \ 8243 out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ 8244 HWIO_INTFREE();\ 8245 } while (0) 8246 8247 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 8248 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 8249 8250 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 8251 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 8252 8253 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 8254 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 8255 8256 //// Register REO_R1_TESTBUS_CTRL //// 8257 8258 #define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002058) 8259 #define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002058) 8260 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f 8261 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 8262 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ 8263 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) 8264 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ 8265 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 8266 #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ 8267 out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) 8268 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 8269 do {\ 8270 HWIO_INTLOCK(); \ 8271 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ 8272 HWIO_INTFREE();\ 8273 } while (0) 8274 8275 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f 8276 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 8277 8278 //// Register REO_R1_TESTBUS_LOWER //// 8279 8280 #define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000205c) 8281 #define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000205c) 8282 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff 8283 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 8284 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ 8285 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) 8286 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ 8287 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 8288 #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ 8289 out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) 8290 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ 8291 do {\ 8292 HWIO_INTLOCK(); \ 8293 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ 8294 HWIO_INTFREE();\ 8295 } while (0) 8296 8297 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 8298 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 8299 8300 //// Register REO_R1_TESTBUS_HIGHER //// 8301 8302 #define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002060) 8303 #define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002060) 8304 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff 8305 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 8306 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ 8307 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) 8308 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ 8309 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 8310 #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ 8311 out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) 8312 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ 8313 do {\ 8314 HWIO_INTLOCK(); \ 8315 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ 8316 HWIO_INTFREE();\ 8317 } while (0) 8318 8319 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff 8320 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 8321 8322 //// Register REO_R1_SM_STATES_IX_0 //// 8323 8324 #define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002064) 8325 #define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002064) 8326 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff 8327 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 8328 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ 8329 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) 8330 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ 8331 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 8332 #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ 8333 out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) 8334 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 8335 do {\ 8336 HWIO_INTLOCK(); \ 8337 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ 8338 HWIO_INTFREE();\ 8339 } while (0) 8340 8341 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff 8342 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 8343 8344 //// Register REO_R1_SM_STATES_IX_1 //// 8345 8346 #define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002068) 8347 #define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002068) 8348 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff 8349 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 8350 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ 8351 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) 8352 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ 8353 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 8354 #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ 8355 out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) 8356 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 8357 do {\ 8358 HWIO_INTLOCK(); \ 8359 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ 8360 HWIO_INTFREE();\ 8361 } while (0) 8362 8363 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff 8364 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 8365 8366 //// Register REO_R1_SM_STATES_IX_2 //// 8367 8368 #define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000206c) 8369 #define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000206c) 8370 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff 8371 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 8372 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ 8373 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) 8374 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ 8375 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 8376 #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ 8377 out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) 8378 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ 8379 do {\ 8380 HWIO_INTLOCK(); \ 8381 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ 8382 HWIO_INTFREE();\ 8383 } while (0) 8384 8385 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff 8386 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 8387 8388 //// Register REO_R1_SM_STATES_IX_3 //// 8389 8390 #define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002070) 8391 #define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002070) 8392 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff 8393 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 8394 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ 8395 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) 8396 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ 8397 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 8398 #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ 8399 out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) 8400 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ 8401 do {\ 8402 HWIO_INTLOCK(); \ 8403 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ 8404 HWIO_INTFREE();\ 8405 } while (0) 8406 8407 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff 8408 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 8409 8410 //// Register REO_R1_SM_STATES_IX_4 //// 8411 8412 #define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002074) 8413 #define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002074) 8414 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff 8415 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 8416 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ 8417 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) 8418 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ 8419 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 8420 #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ 8421 out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) 8422 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ 8423 do {\ 8424 HWIO_INTLOCK(); \ 8425 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ 8426 HWIO_INTFREE();\ 8427 } while (0) 8428 8429 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff 8430 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 8431 8432 //// Register REO_R1_SM_STATES_IX_5 //// 8433 8434 #define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002078) 8435 #define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002078) 8436 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff 8437 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 8438 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ 8439 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) 8440 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ 8441 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 8442 #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ 8443 out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) 8444 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ 8445 do {\ 8446 HWIO_INTLOCK(); \ 8447 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ 8448 HWIO_INTFREE();\ 8449 } while (0) 8450 8451 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff 8452 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 8453 8454 //// Register REO_R1_SM_STATES_IX_6 //// 8455 8456 #define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000207c) 8457 #define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000207c) 8458 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff 8459 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 8460 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ 8461 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) 8462 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ 8463 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 8464 #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ 8465 out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) 8466 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ 8467 do {\ 8468 HWIO_INTLOCK(); \ 8469 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ 8470 HWIO_INTFREE();\ 8471 } while (0) 8472 8473 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff 8474 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 8475 8476 //// Register REO_R1_IDLE_STATES_IX_0 //// 8477 8478 #define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002080) 8479 #define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002080) 8480 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff 8481 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 8482 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ 8483 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) 8484 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ 8485 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 8486 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ 8487 out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) 8488 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ 8489 do {\ 8490 HWIO_INTLOCK(); \ 8491 out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ 8492 HWIO_INTFREE();\ 8493 } while (0) 8494 8495 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff 8496 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 8497 8498 //// Register REO_R1_INVALID_APB_ACCESS //// 8499 8500 #define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002084) 8501 #define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002084) 8502 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff 8503 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 8504 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ 8505 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) 8506 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ 8507 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 8508 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ 8509 out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) 8510 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ 8511 do {\ 8512 HWIO_INTLOCK(); \ 8513 out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ 8514 HWIO_INTFREE();\ 8515 } while (0) 8516 8517 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 8518 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 8519 8520 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff 8521 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 8522 8523 //// Register REO_R2_RXDMA2REO0_RING_HP //// 8524 8525 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) 8526 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) 8527 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff 8528 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 8529 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ 8530 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) 8531 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ 8532 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 8533 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ 8534 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) 8535 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ 8536 do {\ 8537 HWIO_INTLOCK(); \ 8538 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ 8539 HWIO_INTFREE();\ 8540 } while (0) 8541 8542 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8543 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 8544 8545 //// Register REO_R2_RXDMA2REO0_RING_TP //// 8546 8547 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) 8548 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) 8549 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff 8550 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 8551 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ 8552 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) 8553 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ 8554 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 8555 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ 8556 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) 8557 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ 8558 do {\ 8559 HWIO_INTLOCK(); \ 8560 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ 8561 HWIO_INTFREE();\ 8562 } while (0) 8563 8564 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8565 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 8566 8567 //// Register REO_R2_WBM2REO_LINK_RING_HP //// 8568 8569 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003008) 8570 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003008) 8571 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff 8572 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 8573 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ 8574 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) 8575 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ 8576 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 8577 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ 8578 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) 8579 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ 8580 do {\ 8581 HWIO_INTLOCK(); \ 8582 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ 8583 HWIO_INTFREE();\ 8584 } while (0) 8585 8586 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8587 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 8588 8589 //// Register REO_R2_WBM2REO_LINK_RING_TP //// 8590 8591 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000300c) 8592 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000300c) 8593 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff 8594 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 8595 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ 8596 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) 8597 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ 8598 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 8599 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ 8600 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) 8601 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ 8602 do {\ 8603 HWIO_INTLOCK(); \ 8604 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ 8605 HWIO_INTFREE();\ 8606 } while (0) 8607 8608 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8609 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 8610 8611 //// Register REO_R2_REO_CMD_RING_HP //// 8612 8613 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003010) 8614 #define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003010) 8615 #define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff 8616 #define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 8617 #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ 8618 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) 8619 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ 8620 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 8621 #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ 8622 out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) 8623 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ 8624 do {\ 8625 HWIO_INTLOCK(); \ 8626 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ 8627 HWIO_INTFREE();\ 8628 } while (0) 8629 8630 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8631 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 8632 8633 //// Register REO_R2_REO_CMD_RING_TP //// 8634 8635 #define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003014) 8636 #define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003014) 8637 #define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff 8638 #define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 8639 #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ 8640 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) 8641 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ 8642 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 8643 #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ 8644 out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) 8645 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ 8646 do {\ 8647 HWIO_INTLOCK(); \ 8648 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ 8649 HWIO_INTFREE();\ 8650 } while (0) 8651 8652 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8653 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 8654 8655 //// Register REO_R2_SW2REO_RING_HP //// 8656 8657 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003018) 8658 #define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003018) 8659 #define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff 8660 #define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 8661 #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ 8662 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) 8663 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ 8664 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 8665 #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ 8666 out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) 8667 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ 8668 do {\ 8669 HWIO_INTLOCK(); \ 8670 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ 8671 HWIO_INTFREE();\ 8672 } while (0) 8673 8674 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8675 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 8676 8677 //// Register REO_R2_SW2REO_RING_TP //// 8678 8679 #define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000301c) 8680 #define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000301c) 8681 #define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff 8682 #define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 8683 #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ 8684 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) 8685 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ 8686 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 8687 #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ 8688 out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) 8689 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ 8690 do {\ 8691 HWIO_INTLOCK(); \ 8692 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ 8693 HWIO_INTFREE();\ 8694 } while (0) 8695 8696 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8697 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 8698 8699 //// Register REO_R2_SW2REO1_RING_HP //// 8700 8701 #define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) (x+0x00003020) 8702 #define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) (x+0x00003020) 8703 #define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0x0000ffff 8704 #define HWIO_REO_R2_SW2REO1_RING_HP_SHFT 0 8705 #define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ 8706 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK) 8707 #define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \ 8708 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask) 8709 #define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val) \ 8710 out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val) 8711 #define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \ 8712 do {\ 8713 HWIO_INTLOCK(); \ 8714 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \ 8715 HWIO_INTFREE();\ 8716 } while (0) 8717 8718 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8719 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0x0 8720 8721 //// Register REO_R2_SW2REO1_RING_TP //// 8722 8723 #define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) (x+0x00003024) 8724 #define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) (x+0x00003024) 8725 #define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0x0000ffff 8726 #define HWIO_REO_R2_SW2REO1_RING_TP_SHFT 0 8727 #define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ 8728 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK) 8729 #define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \ 8730 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask) 8731 #define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val) \ 8732 out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val) 8733 #define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \ 8734 do {\ 8735 HWIO_INTLOCK(); \ 8736 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \ 8737 HWIO_INTFREE();\ 8738 } while (0) 8739 8740 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8741 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0x0 8742 8743 //// Register REO_R2_REO2SW1_RING_HP //// 8744 8745 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003028) 8746 #define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003028) 8747 #define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x000fffff 8748 #define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 8749 #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ 8750 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) 8751 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ 8752 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 8753 #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ 8754 out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) 8755 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ 8756 do {\ 8757 HWIO_INTLOCK(); \ 8758 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ 8759 HWIO_INTFREE();\ 8760 } while (0) 8761 8762 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x000fffff 8763 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 8764 8765 //// Register REO_R2_REO2SW1_RING_TP //// 8766 8767 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x0000302c) 8768 #define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x0000302c) 8769 #define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x000fffff 8770 #define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 8771 #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ 8772 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) 8773 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ 8774 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 8775 #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ 8776 out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) 8777 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ 8778 do {\ 8779 HWIO_INTLOCK(); \ 8780 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ 8781 HWIO_INTFREE();\ 8782 } while (0) 8783 8784 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x000fffff 8785 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 8786 8787 //// Register REO_R2_REO2SW2_RING_HP //// 8788 8789 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003030) 8790 #define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003030) 8791 #define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x000fffff 8792 #define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 8793 #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ 8794 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) 8795 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ 8796 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 8797 #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ 8798 out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) 8799 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ 8800 do {\ 8801 HWIO_INTLOCK(); \ 8802 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ 8803 HWIO_INTFREE();\ 8804 } while (0) 8805 8806 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x000fffff 8807 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 8808 8809 //// Register REO_R2_REO2SW2_RING_TP //// 8810 8811 #define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x00003034) 8812 #define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x00003034) 8813 #define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x000fffff 8814 #define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 8815 #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ 8816 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) 8817 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ 8818 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 8819 #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ 8820 out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) 8821 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ 8822 do {\ 8823 HWIO_INTLOCK(); \ 8824 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ 8825 HWIO_INTFREE();\ 8826 } while (0) 8827 8828 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x000fffff 8829 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 8830 8831 //// Register REO_R2_REO2SW3_RING_HP //// 8832 8833 #define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003038) 8834 #define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003038) 8835 #define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x000fffff 8836 #define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 8837 #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ 8838 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) 8839 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ 8840 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 8841 #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ 8842 out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) 8843 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ 8844 do {\ 8845 HWIO_INTLOCK(); \ 8846 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ 8847 HWIO_INTFREE();\ 8848 } while (0) 8849 8850 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x000fffff 8851 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 8852 8853 //// Register REO_R2_REO2SW3_RING_TP //// 8854 8855 #define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x0000303c) 8856 #define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x0000303c) 8857 #define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x000fffff 8858 #define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 8859 #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ 8860 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) 8861 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ 8862 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 8863 #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ 8864 out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) 8865 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ 8866 do {\ 8867 HWIO_INTLOCK(); \ 8868 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ 8869 HWIO_INTFREE();\ 8870 } while (0) 8871 8872 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x000fffff 8873 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 8874 8875 //// Register REO_R2_REO2SW4_RING_HP //// 8876 8877 #define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003040) 8878 #define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003040) 8879 #define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x000fffff 8880 #define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 8881 #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ 8882 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) 8883 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ 8884 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 8885 #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ 8886 out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) 8887 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ 8888 do {\ 8889 HWIO_INTLOCK(); \ 8890 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ 8891 HWIO_INTFREE();\ 8892 } while (0) 8893 8894 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x000fffff 8895 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 8896 8897 //// Register REO_R2_REO2SW4_RING_TP //// 8898 8899 #define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x00003044) 8900 #define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x00003044) 8901 #define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x000fffff 8902 #define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 8903 #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ 8904 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) 8905 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ 8906 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 8907 #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ 8908 out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) 8909 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ 8910 do {\ 8911 HWIO_INTLOCK(); \ 8912 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ 8913 HWIO_INTFREE();\ 8914 } while (0) 8915 8916 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x000fffff 8917 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 8918 8919 //// Register REO_R2_REO2TCL_RING_HP //// 8920 8921 #define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003058) 8922 #define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003058) 8923 #define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x000fffff 8924 #define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 8925 #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ 8926 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) 8927 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ 8928 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 8929 #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ 8930 out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) 8931 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ 8932 do {\ 8933 HWIO_INTLOCK(); \ 8934 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ 8935 HWIO_INTFREE();\ 8936 } while (0) 8937 8938 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x000fffff 8939 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 8940 8941 //// Register REO_R2_REO2TCL_RING_TP //// 8942 8943 #define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x0000305c) 8944 #define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x0000305c) 8945 #define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x000fffff 8946 #define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 8947 #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ 8948 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) 8949 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ 8950 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 8951 #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ 8952 out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) 8953 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ 8954 do {\ 8955 HWIO_INTLOCK(); \ 8956 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ 8957 HWIO_INTFREE();\ 8958 } while (0) 8959 8960 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x000fffff 8961 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 8962 8963 //// Register REO_R2_REO2FW_RING_HP //// 8964 8965 #define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003060) 8966 #define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003060) 8967 #define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x000fffff 8968 #define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 8969 #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ 8970 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) 8971 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ 8972 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 8973 #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ 8974 out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) 8975 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ 8976 do {\ 8977 HWIO_INTLOCK(); \ 8978 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ 8979 HWIO_INTFREE();\ 8980 } while (0) 8981 8982 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x000fffff 8983 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 8984 8985 //// Register REO_R2_REO2FW_RING_TP //// 8986 8987 #define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x00003064) 8988 #define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x00003064) 8989 #define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x000fffff 8990 #define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 8991 #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ 8992 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) 8993 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ 8994 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 8995 #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ 8996 out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) 8997 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ 8998 do {\ 8999 HWIO_INTLOCK(); \ 9000 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ 9001 HWIO_INTFREE();\ 9002 } while (0) 9003 9004 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x000fffff 9005 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 9006 9007 //// Register REO_R2_REO_RELEASE_RING_HP //// 9008 9009 #define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003068) 9010 #define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003068) 9011 #define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff 9012 #define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 9013 #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ 9014 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) 9015 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ 9016 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 9017 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ 9018 out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) 9019 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ 9020 do {\ 9021 HWIO_INTLOCK(); \ 9022 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ 9023 HWIO_INTFREE();\ 9024 } while (0) 9025 9026 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9027 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 9028 9029 //// Register REO_R2_REO_RELEASE_RING_TP //// 9030 9031 #define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x0000306c) 9032 #define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x0000306c) 9033 #define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff 9034 #define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 9035 #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ 9036 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) 9037 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ 9038 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 9039 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ 9040 out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) 9041 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ 9042 do {\ 9043 HWIO_INTLOCK(); \ 9044 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ 9045 HWIO_INTFREE();\ 9046 } while (0) 9047 9048 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9049 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 9050 9051 //// Register REO_R2_REO_STATUS_RING_HP //// 9052 9053 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003070) 9054 #define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003070) 9055 #define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff 9056 #define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 9057 #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ 9058 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) 9059 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ 9060 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 9061 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ 9062 out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) 9063 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ 9064 do {\ 9065 HWIO_INTLOCK(); \ 9066 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ 9067 HWIO_INTFREE();\ 9068 } while (0) 9069 9070 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9071 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 9072 9073 //// Register REO_R2_REO_STATUS_RING_TP //// 9074 9075 #define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x00003074) 9076 #define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x00003074) 9077 #define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff 9078 #define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 9079 #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ 9080 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) 9081 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ 9082 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 9083 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ 9084 out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) 9085 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ 9086 do {\ 9087 HWIO_INTLOCK(); \ 9088 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ 9089 HWIO_INTFREE();\ 9090 } while (0) 9091 9092 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9093 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 9094 9095 9096 #endif 9097 9098