1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_DESTINATION_RING_H_ 18 #define _REO_DESTINATION_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_mpdu_desc_info.h" 24 #include "rx_msdu_desc_info.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; 30 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 31 // 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; 32 // 6 rx_reo_queue_desc_addr_31_0[31:0] 33 // 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] 34 // 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22] 35 // 9 reo_destination_struct_signature[31:0] 36 // 10 reserved_10a[31:0] 37 // 11 reserved_11a[31:0] 38 // 12 reserved_12a[31:0] 39 // 13 reserved_13a[31:0] 40 // 14 reserved_14a[31:0] 41 // 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_REO_DESTINATION_RING 16 46 47 struct reo_destination_ring { 48 struct buffer_addr_info buf_or_link_desc_addr_info; 49 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 50 struct rx_msdu_desc_info rx_msdu_desc_info_details; 51 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 52 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 53 reo_dest_buffer_type : 1, //[8] 54 reo_push_reason : 2, //[10:9] 55 reo_error_code : 5, //[15:11] 56 receive_queue_number : 16; //[31:16] 57 uint32_t soft_reorder_info_valid : 1, //[0] 58 reorder_opcode : 4, //[4:1] 59 reorder_slot_index : 8, //[12:5] 60 mpdu_fragment_number : 4, //[16:13] 61 captured_msdu_data_size : 4, //[20:17] 62 sw_exception : 1, //[21] 63 reserved_8a : 10; //[31:22] 64 uint32_t reo_destination_struct_signature: 32; //[31:0] 65 uint32_t reserved_10a : 32; //[31:0] 66 uint32_t reserved_11a : 32; //[31:0] 67 uint32_t reserved_12a : 32; //[31:0] 68 uint32_t reserved_13a : 32; //[31:0] 69 uint32_t reserved_14a : 32; //[31:0] 70 uint32_t reserved_15 : 20, //[19:0] 71 ring_id : 8, //[27:20] 72 looping_count : 4; //[31:28] 73 }; 74 75 /* 76 77 struct buffer_addr_info buf_or_link_desc_addr_info 78 79 Consumer: REO/SW/FW 80 81 Producer: RXDMA 82 83 84 85 Details of the physical address of the a buffer or MSDU 86 link descriptor 87 88 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 89 90 Consumer: REO/SW/FW 91 92 Producer: RXDMA 93 94 95 96 General information related to the MPDU that is passed 97 on from REO entrance ring to the REO destination ring 98 99 struct rx_msdu_desc_info rx_msdu_desc_info_details 100 101 General information related to the MSDU that is passed 102 on from RXDMA all the way to to the REO destination ring. 103 104 rx_reo_queue_desc_addr_31_0 105 106 Consumer: REO 107 108 Producer: RXDMA 109 110 111 112 Address (lower 32 bits) of the REO queue descriptor. 113 114 <legal all> 115 116 rx_reo_queue_desc_addr_39_32 117 118 Consumer: REO 119 120 Producer: RXDMA 121 122 123 124 Address (upper 8 bits) of the REO queue descriptor. 125 126 <legal all> 127 128 reo_dest_buffer_type 129 130 Indicates the type of address provided in the 131 'Buf_or_link_desc_addr_info' 132 133 134 135 <enum 0 MSDU_buf_address> The address of an MSDU buffer 136 137 <enum 1 MSDU_link_desc_address> The address of the MSDU 138 link descriptor. 139 140 141 142 <legal all> 143 144 reo_push_reason 145 146 Indicates why REO pushed the frame to this exit ring 147 148 149 150 <enum 0 reo_error_detected> Reo detected an error an 151 pushed this frame to this queue 152 153 <enum 1 reo_routing_instruction> Reo pushed the frame to 154 this queue per received routing instructions. No error 155 within REO was detected 156 157 158 159 160 161 <legal 0 - 1> 162 163 reo_error_code 164 165 Field only valid when 'Reo_push_reason' set to 166 'reo_error_detected'. 167 168 169 170 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 171 provided in the REO_ENTRANCE ring is set to 0 172 173 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 174 valid bit is NOT set 175 176 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 177 session having been setup. 178 179 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 180 SSN, Retry bit set: duplicate frame 181 182 <enum 4 ba_duplicate> BA session, duplicate frame 183 184 <enum 5 regular_frame_2k_jump> A normal (management/data 185 frame) received with 2K jump in SN 186 187 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 188 in SSN 189 190 <enum 7 regular_frame_OOR> A normal (management/data 191 frame) received with SN falling within the OOR window 192 193 <enum 8 bar_frame_OOR> A bar received with SSN falling 194 within the OOR window 195 196 <enum 9 bar_frame_no_ba_session> A bar received without 197 a BA session 198 199 <enum 10 bar_frame_sn_equals_ssn> A bar received with 200 SSN equal to SN 201 202 <enum 11 pn_check_failed> PN Check Failed packet. 203 204 <enum 12 2k_error_handling_flag_set> Frame is forwarded 205 as a result of the 'Seq_2k_error_detected_flag' been set in 206 the REO Queue descriptor 207 208 <enum 13 pn_error_handling_flag_set> Frame is forwarded 209 as a result of the 'pn_error_detected_flag' been set in the 210 REO Queue descriptor 211 212 <enum 14 queue_descriptor_blocked_set> Frame is 213 forwarded as a result of the queue descriptor(address) being 214 blocked as SW/FW seems to be currently in the process of 215 making updates to this descriptor... 216 217 218 219 <legal 0-14> 220 221 receive_queue_number 222 223 This field in NOT valid (should be set to 0), when 224 SW_exception is set. 225 226 This field indicates the REO MPDU reorder queue ID from 227 which this frame originated. This field is populated from a 228 field with the same name in the RX_REO_QUEUE descriptor. 229 230 <legal all> 231 232 soft_reorder_info_valid 233 234 This field in NOT valid (should be set to 0), when 235 SW_exception is set. 236 237 When set, REO has been instructed to not perform the 238 actual re-ordering of frames for this queue, but just to 239 insert the reorder opcodes 240 241 <legal all> 242 243 reorder_opcode 244 245 Field is valid when 'Soft_reorder_info_valid' is set. 246 This field is always valid for debug purpose as well. 247 248 Details are in the MLD. 249 250 251 252 <enum 0 invalid> 253 254 <enum 1 fwdcur_fwdbuf> 255 256 <enum 2 fwdbuf_fwdcur> 257 258 <enum 3 qcur> 259 260 <enum 4 fwdbuf_qcur> 261 262 <enum 5 fwdbuf_drop> 263 264 <enum 6 fwdall_drop> 265 266 <enum 7 fwdall_qcur> 267 268 <enum 8 reserved_reo_opcode_1> 269 270 <enum 9 dropcur> the error reason code is in 271 reo_error_code field. 272 273 <enum 10 reserved_reo_opcode_2> 274 275 <enum 11 reserved_reo_opcode_3> 276 277 <enum 12 reserved_reo_opcode_4> 278 279 <enum 13 reserved_reo_opcode_5> 280 281 <enum 14 reserved_reo_opcode_6> 282 283 <enum 15 reserved_reo_opcode_7> 284 285 286 287 <legal all> 288 289 reorder_slot_index 290 291 Field only valid when 'Soft_reorder_info_valid' is set. 292 293 294 295 TODO: add description 296 297 298 299 <legal all> 300 301 mpdu_fragment_number 302 303 Field only valid when Rx_mpdu_desc_info_details. 304 Fragment_flag is set. 305 306 307 308 The fragment number from the 802.11 header. 309 310 311 312 Note that the sequence number is embedded in the field: 313 Rx_mpdu_desc_info_details. Mpdu_sequence_number 314 315 316 317 <legal all> 318 319 captured_msdu_data_size 320 321 The number of following REO_DESTINATION STRUCTs that 322 have been replaced with msdu_data extracted from the 323 msdu_buffer and copied into the ring for easy FW/SW access. 324 325 Note that it is possible that these STRUCTs wrap around 326 the end of the ring. 327 328 Feature supported only in HastingsPrime 329 330 <legal 0-4> 331 332 sw_exception 333 334 This field has the same setting as the SW_exception 335 field in the corresponding REO_entrance_ring descriptor. 336 337 When set, the REO entrance descriptor is generated by 338 FW, and the MPDU was processed in the following way: 339 340 - NO re-order function is needed. 341 342 - MPDU delinking is determined by the setting of 343 Entrance ring field: SW_excection_mpdu_delink 344 345 - Destination ring selection is based on the setting of 346 347 Feature supported only in HastingsPrime 348 349 <legal all> 350 351 reserved_8a 352 353 <legal 0> 354 355 reo_destination_struct_signature 356 357 Set to value 0x8888_88888 when msdu capture mode is 358 enabled for this ring (supported only in HastingsPrime) 359 360 <legal 0, 2290649224 > 361 362 reserved_10a 363 364 <legal 0> 365 366 reserved_11a 367 368 <legal 0> 369 370 reserved_12a 371 372 <legal 0> 373 374 reserved_13a 375 376 <legal 0> 377 378 reserved_14a 379 380 <legal 0> 381 382 reserved_15 383 384 <legal 0> 385 386 ring_id 387 388 The buffer pointer ring ID. 389 390 0 refers to the IDLE ring 391 392 1 - N refers to other rings 393 394 395 396 Helps with debugging when dumping ring contents. 397 398 <legal all> 399 400 looping_count 401 402 A count value that indicates the number of times the 403 producer of entries into this Ring has looped around the 404 ring. 405 406 At initialization time, this value is set to 0. On the 407 first loop, this value is set to 1. After the max value is 408 reached allowed by the number of bits for this field, the 409 count value continues with 0 again. 410 411 In case SW is the consumer of the ring entries, it can 412 use this field to figure out up to where the producer of 413 entries has created new entries. This eliminates the need to 414 check where the head pointer' of the ring is located once 415 the SW starts processing an interrupt indicating that new 416 entries have been put into this ring... 417 418 419 420 Also note that SW if it wants only needs to look at the 421 LSB bit of this count value. 422 423 <legal all> 424 */ 425 426 427 /* EXTERNAL REFERENCE : struct buffer_addr_info buf_or_link_desc_addr_info */ 428 429 430 /* Description REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 431 432 Address (lower 32 bits) of the MSDU buffer OR 433 MSDU_EXTENSION descriptor OR Link Descriptor 434 435 436 437 In case of 'NULL' pointer, this field is set to 0 438 439 <legal all> 440 */ 441 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 442 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 443 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 444 445 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 446 447 Address (upper 8 bits) of the MSDU buffer OR 448 MSDU_EXTENSION descriptor OR Link Descriptor 449 450 451 452 In case of 'NULL' pointer, this field is set to 0 453 454 <legal all> 455 */ 456 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 457 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 458 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 459 460 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 461 462 Consumer: WBM 463 464 Producer: SW/FW 465 466 467 468 In case of 'NULL' pointer, this field is set to 0 469 470 471 472 Indicates to which buffer manager the buffer OR 473 MSDU_EXTENSION descriptor OR link descriptor that is being 474 pointed to shall be returned after the frame has been 475 processed. It is used by WBM for routing purposes. 476 477 478 479 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 480 to the WMB buffer idle list 481 482 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 483 returned to the WMB idle link descriptor idle list 484 485 <enum 2 FW_BM> This buffer shall be returned to the FW 486 487 <enum 3 SW0_BM> This buffer shall be returned to the SW, 488 ring 0 489 490 <enum 4 SW1_BM> This buffer shall be returned to the SW, 491 ring 1 492 493 <enum 5 SW2_BM> This buffer shall be returned to the SW, 494 ring 2 495 496 <enum 6 SW3_BM> This buffer shall be returned to the SW, 497 ring 3 498 499 <enum 7 SW4_BM> This buffer shall be returned to the SW, 500 ring 4 501 502 503 504 <legal all> 505 */ 506 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 507 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 508 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 509 510 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 511 512 Cookie field exclusively used by SW. 513 514 515 516 In case of 'NULL' pointer, this field is set to 0 517 518 519 520 HW ignores the contents, accept that it passes the 521 programmed value on to other descriptors together with the 522 physical address 523 524 525 526 Field can be used by SW to for example associate the 527 buffers physical address with the virtual address 528 529 The bit definitions as used by SW are within SW HLD 530 specification 531 532 533 534 NOTE1: 535 536 The three most significant bits can have a special 537 meaning in case this struct is embedded in a TX_MPDU_DETAILS 538 STRUCT, and field transmit_bw_restriction is set 539 540 541 542 In case of NON punctured transmission: 543 544 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 545 546 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 547 548 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 549 550 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 551 552 553 554 In case of punctured transmission: 555 556 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 557 558 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 559 560 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 561 562 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 563 564 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 565 566 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 567 568 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 569 570 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 571 572 573 574 Note: a punctured transmission is indicated by the 575 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 576 TLV 577 578 579 580 NOTE 2:The five most significant bits can have a special 581 meaning in case this struct is embedded in an 582 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 583 configured for passing on the additional info 584 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 585 (FR56821). This is not supported in HastingsPrime, Pine or 586 Moselle. 587 588 589 590 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 591 control field 592 593 594 595 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 596 indicates MPDUs with a QoS control field. 597 598 599 600 601 602 <legal all> 603 */ 604 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 605 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 606 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 607 608 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 609 610 611 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 612 613 Consumer: REO/SW/FW 614 615 Producer: RXDMA 616 617 618 619 The number of MSDUs within the MPDU 620 621 <legal all> 622 */ 623 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 624 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 625 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 626 627 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 628 629 Consumer: REO/SW/FW 630 631 Producer: RXDMA 632 633 634 635 The field can have two different meanings based on the 636 setting of field 'BAR_frame': 637 638 639 640 'BAR_frame' is NOT set: 641 642 The MPDU sequence number of the received frame. 643 644 645 646 'BAR_frame' is set. 647 648 The MPDU Start sequence number from the BAR frame 649 650 <legal all> 651 */ 652 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 653 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 654 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 655 656 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 657 658 Consumer: REO/SW/FW 659 660 Producer: RXDMA 661 662 663 664 When set, this MPDU is a fragment and REO should forward 665 this fragment MPDU to the REO destination ring without any 666 reorder checks, pn checks or bitmap update. This implies 667 that REO is forwarding the pointer to the MSDU link 668 descriptor. The destination ring is coming from a 669 programmable register setting in REO 670 671 672 673 <legal all> 674 */ 675 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 676 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 677 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 678 679 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 680 681 Consumer: REO/SW/FW 682 683 Producer: RXDMA 684 685 686 687 The retry bit setting from the MPDU header of the 688 received frame 689 690 <legal all> 691 */ 692 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 693 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 694 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 695 696 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 697 698 Consumer: REO/SW/FW 699 700 Producer: RXDMA 701 702 703 704 When set, the MPDU was received as part of an A-MPDU. 705 706 <legal all> 707 */ 708 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 709 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 710 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 711 712 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 713 714 Consumer: REO/SW/FW 715 716 Producer: RXDMA 717 718 719 720 When set, the received frame is a BAR frame. After 721 processing, this frame shall be pushed to SW or deleted. 722 723 <legal all> 724 */ 725 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 726 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 727 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 728 729 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 730 731 Consumer: REO/SW/FW 732 733 Producer: RXDMA 734 735 736 737 Copied here by RXDMA from RX_MPDU_END 738 739 When not set, REO will Not perform a PN sequence number 740 check 741 */ 742 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 743 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 744 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 745 746 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 747 748 When set, OLE found a valid SA entry for all MSDUs in 749 this MPDU 750 751 <legal all> 752 */ 753 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 754 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 755 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 756 757 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 758 759 When set, at least 1 MSDU within the MPDU has an 760 unsuccessful MAC source address search due to the expiration 761 of the search timer. 762 763 <legal all> 764 */ 765 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 766 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 767 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 768 769 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 770 771 When set, OLE found a valid DA entry for all MSDUs in 772 this MPDU 773 774 <legal all> 775 */ 776 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 777 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 778 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 779 780 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 781 782 Field Only valid if da_is_valid is set 783 784 785 786 When set, at least one of the DA addresses is a 787 Multicast or Broadcast address. 788 789 <legal all> 790 */ 791 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 792 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 793 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 794 795 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 796 797 When set, at least 1 MSDU within the MPDU has an 798 unsuccessful MAC destination address search due to the 799 expiration of the search timer. 800 801 <legal all> 802 */ 803 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 804 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 805 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 806 807 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 808 809 Field only valid when first_msdu_in_mpdu_flag is set. 810 811 812 813 When set, the contents in the MSDU buffer contains a 814 'RAW' MPDU. This 'RAW' MPDU might be spread out over 815 multiple MSDU buffers. 816 817 <legal all> 818 */ 819 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 820 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 821 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 822 823 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 824 825 The More Fragment bit setting from the MPDU header of 826 the received frame 827 828 829 830 <legal all> 831 */ 832 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 833 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 834 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 835 836 /* Description REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 837 838 Meta data that SW has programmed in the Peer table entry 839 of the transmitting STA. 840 841 <legal all> 842 */ 843 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 844 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 845 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 846 847 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 848 849 850 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 851 852 Parsed from RX_MSDU_END TLV . In the case MSDU spans 853 over multiple buffers, this field will be valid in the Last 854 buffer used by the MSDU 855 856 857 858 <enum 0 Not_first_msdu> This is not the first MSDU in 859 the MPDU. 860 861 <enum 1 first_msdu> This MSDU is the first one in the 862 MPDU. 863 864 865 866 <legal all> 867 */ 868 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 869 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 870 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 871 872 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 873 874 Consumer: WBM/REO/SW/FW 875 876 Producer: RXDMA 877 878 879 880 Parsed from RX_MSDU_END TLV . In the case MSDU spans 881 over multiple buffers, this field will be valid in the Last 882 buffer used by the MSDU 883 884 885 886 <enum 0 Not_last_msdu> There are more MSDUs linked to 887 this MSDU that belongs to this MPDU 888 889 <enum 1 Last_msdu> this MSDU is the last one in the 890 MPDU. This setting is only allowed in combination with 891 'Msdu_continuation' set to 0. This implies that when an msdu 892 is spread out over multiple buffers and thus 893 msdu_continuation is set, only for the very last buffer of 894 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 895 896 897 898 When both first_msdu_in_mpdu_flag and 899 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 900 belongs to only contains a single MSDU. 901 902 903 904 905 906 <legal all> 907 */ 908 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 909 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 910 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 911 912 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 913 914 When set, this MSDU buffer was not able to hold the 915 entire MSDU. The next buffer will therefor contain 916 additional information related to this MSDU. 917 918 919 920 <legal all> 921 */ 922 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 923 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 924 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 925 926 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 927 928 Parsed from RX_MSDU_START TLV . In the case MSDU spans 929 over multiple buffers, this field will be valid in the First 930 buffer used by MSDU. 931 932 933 934 Full MSDU length in bytes after decapsulation. 935 936 937 938 This field is still valid for MPDU frames without 939 A-MSDU. It still represents MSDU length after decapsulation 940 941 942 943 Or in case of RAW MPDUs, it indicates the length of the 944 entire MPDU (without FCS field) 945 946 <legal all> 947 */ 948 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 949 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 950 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 951 952 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 953 954 Parsed from RX_MSDU_END TLV . In the case MSDU spans 955 over multiple buffers, this field will be valid in the Last 956 buffer used by the MSDU 957 958 959 960 The ID of the REO exit ring where the MSDU frame shall 961 push after (MPDU level) reordering has finished. 962 963 964 965 <enum 0 reo_destination_tcl> Reo will push the frame 966 into the REO2TCL ring 967 968 <enum 1 reo_destination_sw1> Reo will push the frame 969 into the REO2SW1 ring 970 971 <enum 2 reo_destination_sw2> Reo will push the frame 972 into the REO2SW2 ring 973 974 <enum 3 reo_destination_sw3> Reo will push the frame 975 into the REO2SW3 ring 976 977 <enum 4 reo_destination_sw4> Reo will push the frame 978 into the REO2SW4 ring 979 980 <enum 5 reo_destination_release> Reo will push the frame 981 into the REO_release ring 982 983 <enum 6 reo_destination_fw> Reo will push the frame into 984 the REO2FW ring 985 986 <enum 7 reo_destination_sw5> Reo will push the frame 987 into the REO2SW5 ring (REO remaps this in chips without 988 REO2SW5 ring, e.g. Pine) 989 990 <enum 8 reo_destination_sw6> Reo will push the frame 991 into the REO2SW6 ring (REO remaps this in chips without 992 REO2SW6 ring, e.g. Pine) 993 994 <enum 9 reo_destination_9> REO remaps this <enum 10 995 reo_destination_10> REO remaps this 996 997 <enum 11 reo_destination_11> REO remaps this 998 999 <enum 12 reo_destination_12> REO remaps this <enum 13 1000 reo_destination_13> REO remaps this 1001 1002 <enum 14 reo_destination_14> REO remaps this 1003 1004 <enum 15 reo_destination_15> REO remaps this 1005 1006 <enum 16 reo_destination_16> REO remaps this 1007 1008 <enum 17 reo_destination_17> REO remaps this 1009 1010 <enum 18 reo_destination_18> REO remaps this 1011 1012 <enum 19 reo_destination_19> REO remaps this 1013 1014 <enum 20 reo_destination_20> REO remaps this 1015 1016 <enum 21 reo_destination_21> REO remaps this 1017 1018 <enum 22 reo_destination_22> REO remaps this 1019 1020 <enum 23 reo_destination_23> REO remaps this 1021 1022 <enum 24 reo_destination_24> REO remaps this 1023 1024 <enum 25 reo_destination_25> REO remaps this 1025 1026 <enum 26 reo_destination_26> REO remaps this 1027 1028 <enum 27 reo_destination_27> REO remaps this 1029 1030 <enum 28 reo_destination_28> REO remaps this 1031 1032 <enum 29 reo_destination_29> REO remaps this 1033 1034 <enum 30 reo_destination_30> REO remaps this 1035 1036 <enum 31 reo_destination_31> REO remaps this 1037 1038 1039 1040 <legal all> 1041 */ 1042 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 1043 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1044 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1045 1046 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1047 1048 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1049 over multiple buffers, this field will be valid in the Last 1050 buffer used by the MSDU 1051 1052 1053 1054 When set, REO shall drop this MSDU and not forward it to 1055 any other ring... 1056 1057 <legal all> 1058 */ 1059 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 1060 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1061 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1062 1063 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1064 1065 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1066 over multiple buffers, this field will be valid in the Last 1067 buffer used by the MSDU 1068 1069 1070 1071 Indicates that OLE found a valid SA entry for this MSDU 1072 1073 <legal all> 1074 */ 1075 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 1076 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1077 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1078 1079 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1080 1081 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1082 over multiple buffers, this field will be valid in the Last 1083 buffer used by the MSDU 1084 1085 1086 1087 Indicates an unsuccessful MAC source address search due 1088 to the expiring of the search timer for this MSDU 1089 1090 <legal all> 1091 */ 1092 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 1093 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1094 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1095 1096 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1097 1098 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1099 over multiple buffers, this field will be valid in the Last 1100 buffer used by the MSDU 1101 1102 1103 1104 Indicates that OLE found a valid DA entry for this MSDU 1105 1106 <legal all> 1107 */ 1108 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 1109 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1110 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1111 1112 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1113 1114 Field Only valid if da_is_valid is set 1115 1116 1117 1118 Indicates the DA address was a Multicast of Broadcast 1119 address for this MSDU 1120 1121 <legal all> 1122 */ 1123 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 1124 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1125 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1126 1127 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1128 1129 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1130 over multiple buffers, this field will be valid in the Last 1131 buffer used by the MSDU 1132 1133 1134 1135 Indicates an unsuccessful MAC destination address search 1136 due to the expiring of the search timer for this MSDU 1137 1138 <legal all> 1139 */ 1140 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 1141 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1142 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1143 1144 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 1145 1146 Passed on from 'RX_MSDU_END' TLV (only the MSB is 1147 reported as the LSB is always zero) 1148 1149 Number of bytes padded to make sure that the L3 header 1150 will always start of a Dword boundary 1151 1152 <legal all> 1153 */ 1154 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 1155 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 1156 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 1157 1158 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 1159 1160 Passed on from 'RX_ATTENTION' TLV 1161 1162 Indicates that the computed checksum did not match the 1163 checksum in the TCP/UDP header. 1164 1165 <legal all> 1166 */ 1167 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 1168 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 1169 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 1170 1171 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 1172 1173 Passed on from 'RX_ATTENTION' TLV 1174 1175 Indicates that the computed checksum did not match the 1176 checksum in the IP header. 1177 1178 <legal all> 1179 */ 1180 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 1181 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 1182 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 1183 1184 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 1185 1186 Passed on from 'RX_MPDU_INFO' structure in 1187 'RX_MPDU_START' TLV 1188 1189 Set to 1 by RXOLE when it has not performed any 802.11 1190 to Ethernet/Natvie WiFi header conversion on this MPDU. 1191 1192 <legal all> 1193 */ 1194 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010 1195 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 1196 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 1197 1198 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 1199 1200 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 1201 1202 Based on a register configuration in RXDMA, this field 1203 will contain: 1204 1205 The offset in the address search table which matches the 1206 MAC source address 1207 1208 OR 1209 1210 1211 1212 'sw_peer_id' from the address search entry corresponding 1213 to the source address of the MSDU 1214 1215 <legal all> 1216 */ 1217 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 1218 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 1219 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 1220 1221 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 1222 1223 Passed on from 'RX_MPDU_INFO' structure in 1224 'RX_MPDU_START' TLV (one MSB is omitted) 1225 1226 1227 1228 Based on a register configuration in RXDMA, this field 1229 will contain: 1230 1231 The index of the address search entry corresponding to 1232 this MPDU (a value of 0xFFFF indicates an invalid AST index, 1233 meaning that no AST entry was found or no AST search was 1234 performed) 1235 1236 1237 1238 OR: 1239 1240 1241 1242 'sw_peer_id' from the address search entry corresponding 1243 to this MPDU (in case of ndp or phy_err or 1244 AST_based_lookup_valid == 0, this field will be set to 0) 1245 1246 <legal all> 1247 */ 1248 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 1249 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 1250 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 1251 1252 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS 1253 1254 Passed on from 'RX_MPDU_INFO' structure in 1255 'RX_MPDU_START' TLV 1256 1257 Set if the 'from DS' bit is set in the frame control. 1258 1259 <legal all> 1260 */ 1261 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 1262 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 1263 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 1264 1265 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS 1266 1267 Passed on from 'RX_MPDU_INFO' structure in 1268 'RX_MPDU_START' TLV 1269 1270 Set if the 'to DS' bit is set in the frame control. 1271 1272 <legal all> 1273 */ 1274 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 1275 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 1276 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 1277 1278 /* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 1279 1280 Consumer: REO 1281 1282 Producer: RXDMA 1283 1284 1285 1286 Address (lower 32 bits) of the REO queue descriptor. 1287 1288 <legal all> 1289 */ 1290 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 1291 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1292 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1293 1294 /* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 1295 1296 Consumer: REO 1297 1298 Producer: RXDMA 1299 1300 1301 1302 Address (upper 8 bits) of the REO queue descriptor. 1303 1304 <legal all> 1305 */ 1306 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c 1307 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1308 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1309 1310 /* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE 1311 1312 Indicates the type of address provided in the 1313 'Buf_or_link_desc_addr_info' 1314 1315 1316 1317 <enum 0 MSDU_buf_address> The address of an MSDU buffer 1318 1319 <enum 1 MSDU_link_desc_address> The address of the MSDU 1320 link descriptor. 1321 1322 1323 1324 <legal all> 1325 */ 1326 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 1327 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 1328 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 1329 1330 /* Description REO_DESTINATION_RING_7_REO_PUSH_REASON 1331 1332 Indicates why REO pushed the frame to this exit ring 1333 1334 1335 1336 <enum 0 reo_error_detected> Reo detected an error an 1337 pushed this frame to this queue 1338 1339 <enum 1 reo_routing_instruction> Reo pushed the frame to 1340 this queue per received routing instructions. No error 1341 within REO was detected 1342 1343 1344 1345 1346 1347 <legal 0 - 1> 1348 */ 1349 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c 1350 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 1351 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 1352 1353 /* Description REO_DESTINATION_RING_7_REO_ERROR_CODE 1354 1355 Field only valid when 'Reo_push_reason' set to 1356 'reo_error_detected'. 1357 1358 1359 1360 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 1361 provided in the REO_ENTRANCE ring is set to 0 1362 1363 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 1364 valid bit is NOT set 1365 1366 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 1367 session having been setup. 1368 1369 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 1370 SSN, Retry bit set: duplicate frame 1371 1372 <enum 4 ba_duplicate> BA session, duplicate frame 1373 1374 <enum 5 regular_frame_2k_jump> A normal (management/data 1375 frame) received with 2K jump in SN 1376 1377 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 1378 in SSN 1379 1380 <enum 7 regular_frame_OOR> A normal (management/data 1381 frame) received with SN falling within the OOR window 1382 1383 <enum 8 bar_frame_OOR> A bar received with SSN falling 1384 within the OOR window 1385 1386 <enum 9 bar_frame_no_ba_session> A bar received without 1387 a BA session 1388 1389 <enum 10 bar_frame_sn_equals_ssn> A bar received with 1390 SSN equal to SN 1391 1392 <enum 11 pn_check_failed> PN Check Failed packet. 1393 1394 <enum 12 2k_error_handling_flag_set> Frame is forwarded 1395 as a result of the 'Seq_2k_error_detected_flag' been set in 1396 the REO Queue descriptor 1397 1398 <enum 13 pn_error_handling_flag_set> Frame is forwarded 1399 as a result of the 'pn_error_detected_flag' been set in the 1400 REO Queue descriptor 1401 1402 <enum 14 queue_descriptor_blocked_set> Frame is 1403 forwarded as a result of the queue descriptor(address) being 1404 blocked as SW/FW seems to be currently in the process of 1405 making updates to this descriptor... 1406 1407 1408 1409 <legal 0-14> 1410 */ 1411 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c 1412 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 1413 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 1414 1415 /* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER 1416 1417 This field in NOT valid (should be set to 0), when 1418 SW_exception is set. 1419 1420 This field indicates the REO MPDU reorder queue ID from 1421 which this frame originated. This field is populated from a 1422 field with the same name in the RX_REO_QUEUE descriptor. 1423 1424 <legal all> 1425 */ 1426 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c 1427 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 1428 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 1429 1430 /* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID 1431 1432 This field in NOT valid (should be set to 0), when 1433 SW_exception is set. 1434 1435 When set, REO has been instructed to not perform the 1436 actual re-ordering of frames for this queue, but just to 1437 insert the reorder opcodes 1438 1439 <legal all> 1440 */ 1441 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 1442 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 1443 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 1444 1445 /* Description REO_DESTINATION_RING_8_REORDER_OPCODE 1446 1447 Field is valid when 'Soft_reorder_info_valid' is set. 1448 This field is always valid for debug purpose as well. 1449 1450 Details are in the MLD. 1451 1452 1453 1454 <enum 0 invalid> 1455 1456 <enum 1 fwdcur_fwdbuf> 1457 1458 <enum 2 fwdbuf_fwdcur> 1459 1460 <enum 3 qcur> 1461 1462 <enum 4 fwdbuf_qcur> 1463 1464 <enum 5 fwdbuf_drop> 1465 1466 <enum 6 fwdall_drop> 1467 1468 <enum 7 fwdall_qcur> 1469 1470 <enum 8 reserved_reo_opcode_1> 1471 1472 <enum 9 dropcur> the error reason code is in 1473 reo_error_code field. 1474 1475 <enum 10 reserved_reo_opcode_2> 1476 1477 <enum 11 reserved_reo_opcode_3> 1478 1479 <enum 12 reserved_reo_opcode_4> 1480 1481 <enum 13 reserved_reo_opcode_5> 1482 1483 <enum 14 reserved_reo_opcode_6> 1484 1485 <enum 15 reserved_reo_opcode_7> 1486 1487 1488 1489 <legal all> 1490 */ 1491 #define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 1492 #define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 1493 #define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e 1494 1495 /* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX 1496 1497 Field only valid when 'Soft_reorder_info_valid' is set. 1498 1499 1500 1501 TODO: add description 1502 1503 1504 1505 <legal all> 1506 */ 1507 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 1508 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 1509 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 1510 1511 /* Description REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER 1512 1513 Field only valid when Rx_mpdu_desc_info_details. 1514 Fragment_flag is set. 1515 1516 1517 1518 The fragment number from the 802.11 header. 1519 1520 1521 1522 Note that the sequence number is embedded in the field: 1523 Rx_mpdu_desc_info_details. Mpdu_sequence_number 1524 1525 1526 1527 <legal all> 1528 */ 1529 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 1530 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 1531 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 1532 1533 /* Description REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE 1534 1535 The number of following REO_DESTINATION STRUCTs that 1536 have been replaced with msdu_data extracted from the 1537 msdu_buffer and copied into the ring for easy FW/SW access. 1538 1539 Note that it is possible that these STRUCTs wrap around 1540 the end of the ring. 1541 1542 Feature supported only in HastingsPrime 1543 1544 <legal 0-4> 1545 */ 1546 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 1547 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 1548 #define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 1549 1550 /* Description REO_DESTINATION_RING_8_SW_EXCEPTION 1551 1552 This field has the same setting as the SW_exception 1553 field in the corresponding REO_entrance_ring descriptor. 1554 1555 When set, the REO entrance descriptor is generated by 1556 FW, and the MPDU was processed in the following way: 1557 1558 - NO re-order function is needed. 1559 1560 - MPDU delinking is determined by the setting of 1561 Entrance ring field: SW_excection_mpdu_delink 1562 1563 - Destination ring selection is based on the setting of 1564 1565 Feature supported only in HastingsPrime 1566 1567 <legal all> 1568 */ 1569 #define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 1570 #define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 1571 #define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 1572 1573 /* Description REO_DESTINATION_RING_8_RESERVED_8A 1574 1575 <legal 0> 1576 */ 1577 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 1578 #define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 1579 #define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 1580 1581 /* Description REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE 1582 1583 Set to value 0x8888_88888 when msdu capture mode is 1584 enabled for this ring (supported only in HastingsPrime) 1585 1586 <legal 0, 2290649224 > 1587 */ 1588 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 1589 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 1590 #define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff 1591 1592 /* Description REO_DESTINATION_RING_10_RESERVED_10A 1593 1594 <legal 0> 1595 */ 1596 #define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 1597 #define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 1598 #define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff 1599 1600 /* Description REO_DESTINATION_RING_11_RESERVED_11A 1601 1602 <legal 0> 1603 */ 1604 #define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c 1605 #define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 1606 #define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff 1607 1608 /* Description REO_DESTINATION_RING_12_RESERVED_12A 1609 1610 <legal 0> 1611 */ 1612 #define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 1613 #define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 1614 #define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff 1615 1616 /* Description REO_DESTINATION_RING_13_RESERVED_13A 1617 1618 <legal 0> 1619 */ 1620 #define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 1621 #define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 1622 #define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff 1623 1624 /* Description REO_DESTINATION_RING_14_RESERVED_14A 1625 1626 <legal 0> 1627 */ 1628 #define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 1629 #define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 1630 #define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff 1631 1632 /* Description REO_DESTINATION_RING_15_RESERVED_15 1633 1634 <legal 0> 1635 */ 1636 #define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c 1637 #define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 1638 #define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff 1639 1640 /* Description REO_DESTINATION_RING_15_RING_ID 1641 1642 The buffer pointer ring ID. 1643 1644 0 refers to the IDLE ring 1645 1646 1 - N refers to other rings 1647 1648 1649 1650 Helps with debugging when dumping ring contents. 1651 1652 <legal all> 1653 */ 1654 #define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c 1655 #define REO_DESTINATION_RING_15_RING_ID_LSB 20 1656 #define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 1657 1658 /* Description REO_DESTINATION_RING_15_LOOPING_COUNT 1659 1660 A count value that indicates the number of times the 1661 producer of entries into this Ring has looped around the 1662 ring. 1663 1664 At initialization time, this value is set to 0. On the 1665 first loop, this value is set to 1. After the max value is 1666 reached allowed by the number of bits for this field, the 1667 count value continues with 0 again. 1668 1669 In case SW is the consumer of the ring entries, it can 1670 use this field to figure out up to where the producer of 1671 entries has created new entries. This eliminates the need to 1672 check where the head pointer' of the ring is located once 1673 the SW starts processing an interrupt indicating that new 1674 entries have been put into this ring... 1675 1676 1677 1678 Also note that SW if it wants only needs to look at the 1679 LSB bit of this count value. 1680 1681 <legal all> 1682 */ 1683 #define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c 1684 #define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 1685 #define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 1686 1687 1688 #endif // _REO_DESTINATION_RING_H_ 1689