1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_PKT_END_INFO_H_ 18 #define _PHYRX_PKT_END_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_location_info.h" 23 #include "rx_timing_offset_info.h" 24 #include "receive_rssi_info.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] 30 // 1 phy_timestamp_1_lower_32[31:0] 31 // 2 phy_timestamp_1_upper_32[31:0] 32 // 3 phy_timestamp_2_lower_32[31:0] 33 // 4 phy_timestamp_2_upper_32[31:0] 34 // 5-13 struct rx_location_info rx_location_info_details; 35 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 36 // 15-30 struct receive_rssi_info post_rssi_info_details; 37 // 31 phy_sw_status_31_0[31:0] 38 // 32 phy_sw_status_63_32[31:0] 39 // 40 // ################ END SUMMARY ################# 41 42 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 43 44 struct phyrx_pkt_end_info { 45 uint32_t phy_internal_nap : 1, //[0] 46 location_info_valid : 1, //[1] 47 timing_info_valid : 1, //[2] 48 rssi_info_valid : 1, //[3] 49 rx_frame_correction_needed : 1, //[4] 50 frameless_frame_received : 1, //[5] 51 reserved_0a : 6, //[11:6] 52 dl_ofdma_info_valid : 1, //[12] 53 dl_ofdma_ru_start_index : 7, //[19:13] 54 dl_ofdma_ru_width : 7, //[26:20] 55 reserved_0b : 5; //[31:27] 56 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 57 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 58 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 59 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 60 struct rx_location_info rx_location_info_details; 61 struct rx_timing_offset_info rx_timing_offset_info_details; 62 struct receive_rssi_info post_rssi_info_details; 63 uint32_t phy_sw_status_31_0 : 32; //[31:0] 64 uint32_t phy_sw_status_63_32 : 32; //[31:0] 65 }; 66 67 /* 68 69 phy_internal_nap 70 71 When set, PHY RX entered an internal NAP state, as PHY 72 determined that this reception was not destined to this 73 device 74 75 location_info_valid 76 77 Indicates that the RX_LOCATION_INFO structure later on 78 in the TLV contains valid info 79 80 timing_info_valid 81 82 Indicates that the RX_TIMING_OFFSET_INFO structure later 83 on in the TLV contains valid info 84 85 rssi_info_valid 86 87 Indicates that the RECEIVE_RSSI_INFO structure later on 88 in the TLV contains valid info 89 90 rx_frame_correction_needed 91 92 When clear, no action is needed in the MAC. 93 94 95 96 When set, the falling edge of the rx_frame happened 4us 97 too late. MAC will need to compensate for this delay in 98 order to maintain proper SIFS timing and/or not to get 99 de-slotted. 100 101 102 103 PHY uses this for very short 11a frames. 104 105 106 107 When set, PHY will have passed this TLV to the MAC up to 108 8 us into the 'real SIFS' time, and thus within 4us from the 109 falling edge of the rx_frame. 110 111 112 113 <legal all> 114 115 frameless_frame_received 116 117 When set, PHY has received the 'frameless frame' . Can 118 be used in the 'MU-RTS -CTS exchange where CTS reception can 119 be problematic. 120 121 <legal all> 122 123 reserved_0a 124 125 <legal 0> 126 127 dl_ofdma_info_valid 128 129 When set, the following DL_ofdma_... fields are valid. 130 131 It provides the MAC insight into which RU was allocated 132 to this device. 133 134 <legal all> 135 136 dl_ofdma_ru_start_index 137 138 RU index number to which User is assigned 139 140 RU numbering is over the entire BW, starting from 0 and 141 in increasing frequency order and not primary-secondary 142 order 143 144 <legal 0-73> 145 146 dl_ofdma_ru_width 147 148 The size of the RU for this user. 149 150 In units of 1 (26 tone) RU 151 152 <legal 1-74> 153 154 reserved_0b 155 156 <legal 0> 157 158 phy_timestamp_1_lower_32 159 160 TODO PHY: cleanup descriptionThe PHY timestamp in the 161 AMPI of the first rising edge of rx_clear_pri after 162 TX_PHY_DESC. . This field should set to 0 by the PHY and 163 should be updated by the AMPI before being forwarded to the 164 rest of the MAC. This field indicates the lower 32 bits of 165 the timestamp 166 167 phy_timestamp_1_upper_32 168 169 TODO PHY: cleanup description 170 171 The PHY timestamp in the AMPI of the first rising edge 172 of rx_clear_pri after TX_PHY_DESC. This field should set to 173 0 by the PHY and should be updated by the AMPI before being 174 forwarded to the rest of the MAC. This field indicates the 175 upper 32 bits of the timestamp 176 177 phy_timestamp_2_lower_32 178 179 TODO PHY: cleanup description 180 181 The PHY timestamp in the AMPI of the rising edge of 182 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 183 0 by the PHY and should be updated by the AMPI before being 184 forwarded to the rest of the MAC. This field indicates the 185 lower 32 bits of the timestamp 186 187 phy_timestamp_2_upper_32 188 189 TODO PHY: cleanup description 190 191 The PHY timestamp in the AMPI of the rising edge of 192 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 193 0 by the PHY and should be updated by the AMPI before being 194 forwarded to the rest of the MAC. This field indicates the 195 upper 32 bits of the timestamp 196 197 struct rx_location_info rx_location_info_details 198 199 Overview of location related info 200 201 struct rx_timing_offset_info rx_timing_offset_info_details 202 203 Overview of timing offset related info 204 205 struct receive_rssi_info post_rssi_info_details 206 207 Overview of the post-RSSI values. 208 209 phy_sw_status_31_0 210 211 Some PHY micro code status that can be put in here. 212 Details of definition within SW specification 213 214 This field can be used for debugging, FW - SW message 215 exchange, etc. 216 217 It could for example be a pointer to a DDR memory 218 location where PHY FW put some debug info. 219 220 <legal all> 221 222 phy_sw_status_63_32 223 224 Some PHY micro code status that can be put in here. 225 Details of definition within SW specification 226 227 This field can be used for debugging, FW - SW message 228 exchange, etc. 229 230 It could for example be a pointer to a DDR memory 231 location where PHY FW put some debug info. 232 233 <legal all> 234 */ 235 236 237 /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 238 239 When set, PHY RX entered an internal NAP state, as PHY 240 determined that this reception was not destined to this 241 device 242 */ 243 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 244 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 245 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 246 247 /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 248 249 Indicates that the RX_LOCATION_INFO structure later on 250 in the TLV contains valid info 251 */ 252 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 253 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 254 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 255 256 /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 257 258 Indicates that the RX_TIMING_OFFSET_INFO structure later 259 on in the TLV contains valid info 260 */ 261 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 262 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 263 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 264 265 /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 266 267 Indicates that the RECEIVE_RSSI_INFO structure later on 268 in the TLV contains valid info 269 */ 270 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 271 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 272 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 273 274 /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 275 276 When clear, no action is needed in the MAC. 277 278 279 280 When set, the falling edge of the rx_frame happened 4us 281 too late. MAC will need to compensate for this delay in 282 order to maintain proper SIFS timing and/or not to get 283 de-slotted. 284 285 286 287 PHY uses this for very short 11a frames. 288 289 290 291 When set, PHY will have passed this TLV to the MAC up to 292 8 us into the 'real SIFS' time, and thus within 4us from the 293 falling edge of the rx_frame. 294 295 296 297 <legal all> 298 */ 299 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 300 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 301 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 302 303 /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 304 305 When set, PHY has received the 'frameless frame' . Can 306 be used in the 'MU-RTS -CTS exchange where CTS reception can 307 be problematic. 308 309 <legal all> 310 */ 311 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 312 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 313 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 314 315 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 316 317 <legal 0> 318 */ 319 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 320 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 321 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 322 323 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID 324 325 When set, the following DL_ofdma_... fields are valid. 326 327 It provides the MAC insight into which RU was allocated 328 to this device. 329 330 <legal all> 331 */ 332 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 333 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 334 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 335 336 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX 337 338 RU index number to which User is assigned 339 340 RU numbering is over the entire BW, starting from 0 and 341 in increasing frequency order and not primary-secondary 342 order 343 344 <legal 0-73> 345 */ 346 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 347 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 348 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 349 350 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH 351 352 The size of the RU for this user. 353 354 In units of 1 (26 tone) RU 355 356 <legal 1-74> 357 */ 358 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 359 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 360 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 361 362 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0B 363 364 <legal 0> 365 */ 366 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 367 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 368 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 369 370 /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 371 372 TODO PHY: cleanup descriptionThe PHY timestamp in the 373 AMPI of the first rising edge of rx_clear_pri after 374 TX_PHY_DESC. . This field should set to 0 by the PHY and 375 should be updated by the AMPI before being forwarded to the 376 rest of the MAC. This field indicates the lower 32 bits of 377 the timestamp 378 */ 379 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 380 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 381 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 382 383 /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 384 385 TODO PHY: cleanup description 386 387 The PHY timestamp in the AMPI of the first rising edge 388 of rx_clear_pri after TX_PHY_DESC. This field should set to 389 0 by the PHY and should be updated by the AMPI before being 390 forwarded to the rest of the MAC. This field indicates the 391 upper 32 bits of the timestamp 392 */ 393 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 394 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 395 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 396 397 /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 398 399 TODO PHY: cleanup description 400 401 The PHY timestamp in the AMPI of the rising edge of 402 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 403 0 by the PHY and should be updated by the AMPI before being 404 forwarded to the rest of the MAC. This field indicates the 405 lower 32 bits of the timestamp 406 */ 407 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 408 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 409 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 410 411 /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 412 413 TODO PHY: cleanup description 414 415 The PHY timestamp in the AMPI of the rising edge of 416 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 417 0 by the PHY and should be updated by the AMPI before being 418 forwarded to the rest of the MAC. This field indicates the 419 upper 32 bits of the timestamp 420 */ 421 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 422 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 423 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 424 425 /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ 426 427 428 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY 429 430 For 20/40/80, this field shows the RTT first arrival 431 correction value computed from L-LTF on the first selected 432 Rx chain 433 434 435 436 For 80+80, this field shows the RTT first arrival 437 correction value computed from L-LTF on pri80 on the 438 selected pri80 Rx chain 439 440 441 442 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 443 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 444 interpolation 445 446 447 448 clock unit is 320MHz 449 450 <legal all> 451 */ 452 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 453 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 454 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff 455 456 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 457 458 For 20/40/80, this field shows the RTT first arrival 459 correction value computed from L-LTF on the second selected 460 Rx chain 461 462 463 464 For 80+80, this field shows the RTT first arrival 465 correction value computed from L-LTF on ext80 on the 466 selected ext80 Rx chain 467 468 469 470 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 471 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 472 interpolation 473 474 475 476 clock unit is 320MHz 477 478 <legal all> 479 */ 480 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 481 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 482 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 483 484 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT 485 486 For 20/40/80, this field shows the RTT first arrival 487 correction value computed from (V)HT/HE-LTF on the first 488 selected Rx chain 489 490 491 492 For 80+80, this field shows the RTT first arrival 493 correction value computed from (V)HT/HE-LTF on pri80 on the 494 selected pri80 Rx chain 495 496 497 498 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 499 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 500 interpolation 501 502 503 504 clock unit is 320MHz 505 506 <legal all> 507 */ 508 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 509 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 510 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff 511 512 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 513 514 For 20/40/80, this field shows the RTT first arrival 515 correction value computed from (V)HT/HE-LTF on the second 516 selected Rx chain 517 518 519 520 For 80+80, this field shows the RTT first arrival 521 correction value computed from (V)HT/HE-LTF on ext80 on the 522 selected ext80 Rx chain 523 524 525 526 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 527 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 528 interpolation 529 530 531 532 clock unit is 320MHz 533 534 <legal all> 535 */ 536 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 537 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 538 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 539 540 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS 541 542 Status of rtt_fac_legacy 543 544 545 546 <enum 0 location_fac_legacy_status_not_valid> 547 548 <enum 1 location_fac_legacy_status_valid> 549 550 <legal all> 551 */ 552 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c 553 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 554 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 555 556 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS 557 558 Status of rtt_fac_legacy_ext80 559 560 561 562 <enum 0 location_fac_legacy_ext80_status_not_valid> 563 564 <enum 1 location_fac_legacy_ext80_status_valid> 565 566 <legal all> 567 */ 568 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c 569 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 570 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 571 572 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS 573 574 Status of rtt_fac_vht 575 576 577 578 <enum 0 location_fac_vht_status_not_valid> 579 580 <enum 1 location_fac_vht_status_valid> 581 582 <legal all> 583 */ 584 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c 585 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 586 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 587 588 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS 589 590 Status of rtt_fac_vht_ext80 591 592 593 594 <enum 0 location_fac_vht_ext80_status_not_valid> 595 596 <enum 1 location_fac_vht_ext80_status_valid> 597 598 <legal all> 599 */ 600 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c 601 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 602 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 603 604 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS 605 606 To support fine SIFS adjustment, need to provide FAC 607 value @ integer number of 320 MHz clock cycles to MAC. It 608 is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF 609 if it is a (V)HT/HE packet 610 611 612 613 12 bits, signed, no fractional part 614 615 <legal all> 616 */ 617 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c 618 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 619 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 620 621 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS 622 623 Status of rtt_fac_sifs 624 625 0: not valid 626 627 1: valid and from L-LTF 628 629 2: valid and from (V)HT/HE-LTF 630 631 3: reserved 632 633 <legal 0-2> 634 */ 635 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c 636 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 637 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 638 639 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS 640 641 Status of channel frequency response dump 642 643 644 645 <enum 0 location_CFR_dump_not_valid> 646 647 <enum 1 location_CFR_dump_valid> 648 649 <legal all> 650 */ 651 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c 652 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 653 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 654 655 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS 656 657 Status of channel impulse response dump 658 659 660 661 <enum 0 location_CIR_dump_not_valid> 662 663 <enum 1 location_CIR_dump_valid> 664 665 <legal all> 666 */ 667 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c 668 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 669 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 670 671 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE 672 673 Channel dump size. It shows how many tones in CFR in 674 one chain, for example, it will show 52 for Legacy20 and 484 675 for VHT160 676 677 678 679 <legal all> 680 */ 681 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c 682 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 683 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 684 685 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE 686 687 Indicator showing if HW IFFT mode or SW IFFT mode 688 689 690 691 <enum 0 location_sw_ifft_mode> 692 693 <enum 1 location_hw_ifft_mode> 694 695 <legal all> 696 */ 697 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c 698 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 699 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 700 701 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS 702 703 Indicate if BTCF is used to capture the timestamps 704 705 706 707 <enum 0 location_not_BTCF_based_ts> 708 709 <enum 1 location_BTCF_based_ts> 710 711 <legal all> 712 */ 713 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 714 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 715 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 716 717 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE 718 719 Indicate preamble type 720 721 722 723 <enum 0 location_preamble_type_legacy> 724 725 <enum 1 location_preamble_type_ht> 726 727 <enum 2 location_preamble_type_vht> 728 729 <enum 3 location_preamble_type_he_su_4xltf> 730 731 <enum 4 location_preamble_type_he_su_2xltf> 732 733 <enum 5 location_preamble_type_he_su_1xltf> 734 735 <enum 6 736 location_preamble_type_he_trigger_based_ul_4xltf> 737 738 <enum 7 739 location_preamble_type_he_trigger_based_ul_2xltf> 740 741 <enum 8 742 location_preamble_type_he_trigger_based_ul_1xltf> 743 744 <enum 9 location_preamble_type_he_mu_4xltf> 745 746 <enum 10 location_preamble_type_he_mu_2xltf> 747 748 <enum 11 location_preamble_type_he_mu_1xltf> 749 750 <enum 12 751 location_preamble_type_he_extended_range_su_4xltf> 752 753 <enum 13 754 location_preamble_type_he_extended_range_su_2xltf> 755 756 <enum 14 757 location_preamble_type_he_extended_range_su_1xltf> 758 759 <legal 0-14> 760 */ 761 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 762 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 763 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e 764 765 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG 766 767 Indicate the bandwidth of L-LTF 768 769 770 771 <enum 0 location_pkt_bw_20MHz> 772 773 <enum 1 location_pkt_bw_40MHz> 774 775 <enum 2 location_pkt_bw_80MHz> 776 777 <enum 3 location_pkt_bw_160MHz> 778 779 <legal all> 780 */ 781 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 782 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 783 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 784 785 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT 786 787 Indicate the bandwidth of (V)HT/HE-LTF 788 789 790 791 <enum 0 location_pkt_bw_20MHz> 792 793 <enum 1 location_pkt_bw_40MHz> 794 795 <enum 2 location_pkt_bw_80MHz> 796 797 <enum 3 location_pkt_bw_160MHz> 798 799 <legal all> 800 */ 801 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 802 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 803 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 804 805 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE 806 807 Indicate GI (guard interval) type 808 809 810 811 <enum 0 gi_0_8_us > HE related GI. Can also be used 812 for HE 813 814 <enum 1 gi_0_4_us > HE related GI. Can also be used 815 for HE 816 817 <enum 2 gi_1_6_us > HE related GI 818 819 <enum 3 gi_3_2_us > HE related GI 820 821 <legal 0 - 3> 822 */ 823 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 824 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 825 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 826 827 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE 828 829 Bits 0~4 indicate MCS rate, if Legacy, 830 831 0: 48 Mbps, 832 833 1: 24 Mbps, 834 835 2: 12 Mbps, 836 837 3: 6 Mbps, 838 839 4: 54 Mbps, 840 841 5: 36 Mbps, 842 843 6: 18 Mbps, 844 845 7: 9 Mbps, 846 847 848 849 if HT, 0-7: MCS0-MCS7, 850 851 if VHT, 0-9: MCS0-MCS9, 852 853 854 <legal all> 855 */ 856 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 857 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 858 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 859 860 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN 861 862 For 20/40/80, this field shows the first selected Rx 863 chain that is used in HW IFFT mode 864 865 866 867 For 80+80, this field shows the selected pri80 Rx chain 868 that is used in HW IFFT mode 869 870 871 872 <enum 0 location_strongest_chain_is_0> 873 874 <enum 1 location_strongest_chain_is_1> 875 876 <enum 2 location_strongest_chain_is_2> 877 878 <enum 3 location_strongest_chain_is_3> 879 880 <enum 4 location_strongest_chain_is_4> 881 882 <enum 5 location_strongest_chain_is_5> 883 884 <enum 6 location_strongest_chain_is_6> 885 886 <enum 7 location_strongest_chain_is_7> 887 888 <legal all> 889 */ 890 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 891 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 892 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 893 894 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 895 896 For 20/40/80, this field shows the second selected Rx 897 chain that is used in HW IFFT mode 898 899 900 901 For 80+80, this field shows the selected ext80 Rx chain 902 that is used in HW IFFT mode 903 904 905 906 <enum 0 location_strongest_chain_is_0> 907 908 <enum 1 location_strongest_chain_is_1> 909 910 <enum 2 location_strongest_chain_is_2> 911 912 <enum 3 location_strongest_chain_is_3> 913 914 <enum 4 location_strongest_chain_is_4> 915 916 <enum 5 location_strongest_chain_is_5> 917 918 <enum 6 location_strongest_chain_is_6> 919 920 <enum 7 location_strongest_chain_is_7> 921 922 <legal all> 923 */ 924 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 925 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 926 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 927 928 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK 929 930 Rx chain mask, each bit is a Rx chain 931 932 0: the Rx chain is not used 933 934 1: the Rx chain is used 935 936 Support up to 8 Rx chains 937 938 <legal all> 939 */ 940 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 941 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 942 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 943 944 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3 945 946 <legal 0> 947 */ 948 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 949 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 950 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 951 952 /* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS 953 954 RX packet start timestamp 955 956 957 958 It reports the time the first L-STF ADC sample arrived 959 at RX antenna 960 961 962 963 clock unit is 480MHz 964 965 <legal all> 966 */ 967 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 968 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 969 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff 970 971 /* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS 972 973 RX packet end timestamp 974 975 976 977 It reports the time the last symbol's last ADC sample 978 arrived at RX antenna 979 980 981 982 clock unit is 480MHz 983 984 <legal all> 985 */ 986 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 987 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 988 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff 989 990 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START 991 992 The phase of the SFO of the first symbol's first FFT 993 input sample 994 995 996 997 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 998 66.7ns, and 6 bits fraction to provide a resolution of 999 0.03ns 1000 1001 1002 1003 clock unit is 480MHz 1004 1005 <legal all> 1006 */ 1007 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c 1008 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 1009 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff 1010 1011 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END 1012 1013 The phase of the SFO of the last symbol's last FFT input 1014 sample 1015 1016 1017 1018 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1019 66.7ns, and 6 bits fraction to provide a resolution of 1020 0.03ns 1021 1022 1023 1024 clock unit is 480MHz 1025 1026 <legal all> 1027 */ 1028 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c 1029 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 1030 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 1031 1032 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 1033 1034 The high 8 bits of the 40 bits pointer pointed to the 1035 external RTT channel information buffer 1036 1037 1038 1039 8 bits 1040 1041 <legal all> 1042 */ 1043 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c 1044 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 1045 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 1046 1047 /* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 1048 1049 The low 32 bits of the 40 bits pointer pointed to the 1050 external RTT channel information buffer 1051 1052 1053 1054 32 bits 1055 1056 <legal all> 1057 */ 1058 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 1059 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 1060 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff 1061 1062 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT 1063 1064 CFO measurement. Needed for passive locationing 1065 1066 1067 1068 14 bits, signed 1.13. 13 bits fraction to provide a 1069 resolution of 153 Hz 1070 1071 1072 1073 In units of cycles/800 ns 1074 1075 <legal all> 1076 */ 1077 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 1078 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 1079 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff 1080 1081 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD 1082 1083 Channel delay spread measurement. Needed for selecting 1084 GI length 1085 1086 1087 1088 8 bits, unsigned. At 25 ns step. Can represent up to 1089 6375 ns 1090 1091 1092 1093 In units of cycles @ 40 MHz 1094 1095 <legal all> 1096 */ 1097 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 1098 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 1099 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 1100 1101 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL 1102 1103 Indicate which timing backoff value is used 1104 1105 1106 1107 <enum 0 timing_backoff_low_rssi> 1108 1109 <enum 1 timing_backoff_mid_rssi> 1110 1111 <enum 2 timing_backoff_high_rssi> 1112 1113 <enum 3 reserved> 1114 1115 <legal all> 1116 */ 1117 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 1118 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 1119 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 1120 1121 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8 1122 1123 <legal 0> 1124 */ 1125 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 1126 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 1127 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 1128 1129 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID 1130 1131 <enum 0 rx_location_info_is_not_valid> 1132 1133 <enum 1 rx_location_info_is_valid> 1134 1135 <legal all> 1136 */ 1137 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 1138 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 1139 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 1140 1141 /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ 1142 1143 1144 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET 1145 1146 Cumulative reference frequency error at end of RX 1147 1148 <legal all> 1149 */ 1150 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 1151 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 1152 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 1153 1154 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED 1155 1156 <legal 0> 1157 */ 1158 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 1159 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 1160 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 1161 1162 /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ 1163 1164 1165 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 1166 1167 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1168 1169 Value of 0x80 indicates invalid. 1170 */ 1171 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c 1172 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1173 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 1174 1175 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 1176 1177 RSSI of RX PPDU on chain 0 of extension 20 MHz 1178 bandwidth. 1179 1180 Value of 0x80 indicates invalid. 1181 */ 1182 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c 1183 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1184 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 1185 1186 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 1187 1188 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 1189 bandwidth. 1190 1191 Value of 0x80 indicates invalid. 1192 */ 1193 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c 1194 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1195 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 1196 1197 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 1198 1199 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1200 bandwidth. 1201 1202 Value of 0x80 indicates invalid. 1203 */ 1204 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c 1205 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1206 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 1207 1208 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 1209 1210 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 1211 bandwidth. 1212 1213 Value of 0x80 indicates invalid. 1214 */ 1215 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 1216 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 1217 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 1218 1219 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 1220 1221 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1222 MHz bandwidth. 1223 1224 Value of 0x80 indicates invalid. 1225 */ 1226 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 1227 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 1228 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 1229 1230 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 1231 1232 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1233 MHz bandwidth. 1234 1235 Value of 0x80 indicates invalid. 1236 */ 1237 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 1238 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 1239 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 1240 1241 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 1242 1243 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1244 bandwidth. 1245 1246 Value of 0x80 indicates invalid. 1247 */ 1248 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 1249 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 1250 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 1251 1252 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 1253 1254 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1255 1256 Value of 0x80 indicates invalid. 1257 */ 1258 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 1259 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1260 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 1261 1262 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 1263 1264 RSSI of RX PPDU on chain 1 of extension 20 MHz 1265 bandwidth. 1266 1267 Value of 0x80 indicates invalid. 1268 */ 1269 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 1270 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1271 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 1272 1273 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 1274 1275 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 1276 bandwidth. 1277 1278 Value of 0x80 indicates invalid. 1279 */ 1280 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 1281 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1282 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 1283 1284 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 1285 1286 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1287 bandwidth. 1288 1289 Value of 0x80 indicates invalid. 1290 */ 1291 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 1292 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1293 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 1294 1295 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 1296 1297 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 1298 bandwidth. 1299 1300 Value of 0x80 indicates invalid. 1301 */ 1302 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 1303 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 1304 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 1305 1306 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 1307 1308 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1309 MHz bandwidth. 1310 1311 Value of 0x80 indicates invalid. 1312 */ 1313 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 1314 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 1315 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 1316 1317 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 1318 1319 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1320 MHz bandwidth. 1321 1322 Value of 0x80 indicates invalid. 1323 */ 1324 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 1325 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 1326 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 1327 1328 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 1329 1330 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1331 bandwidth. 1332 1333 Value of 0x80 indicates invalid. 1334 */ 1335 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 1336 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 1337 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 1338 1339 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 1340 1341 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1342 1343 Value of 0x80 indicates invalid. 1344 */ 1345 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c 1346 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1347 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 1348 1349 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 1350 1351 RSSI of RX PPDU on chain 2 of extension 20 MHz 1352 bandwidth. 1353 1354 Value of 0x80 indicates invalid. 1355 */ 1356 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c 1357 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1358 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 1359 1360 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 1361 1362 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 1363 bandwidth. 1364 1365 Value of 0x80 indicates invalid. 1366 */ 1367 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c 1368 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1369 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 1370 1371 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 1372 1373 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1374 bandwidth. 1375 1376 Value of 0x80 indicates invalid. 1377 */ 1378 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c 1379 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1380 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 1381 1382 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 1383 1384 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 1385 bandwidth. 1386 1387 Value of 0x80 indicates invalid. 1388 */ 1389 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 1390 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 1391 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 1392 1393 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 1394 1395 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1396 MHz bandwidth. 1397 1398 Value of 0x80 indicates invalid. 1399 */ 1400 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 1401 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 1402 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 1403 1404 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 1405 1406 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1407 MHz bandwidth. 1408 1409 Value of 0x80 indicates invalid. 1410 */ 1411 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 1412 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 1413 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 1414 1415 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 1416 1417 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1418 bandwidth. 1419 1420 Value of 0x80 indicates invalid. 1421 */ 1422 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 1423 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 1424 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 1425 1426 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 1427 1428 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1429 1430 Value of 0x80 indicates invalid. 1431 */ 1432 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 1433 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1434 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 1435 1436 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 1437 1438 RSSI of RX PPDU on chain 3 of extension 20 MHz 1439 bandwidth. 1440 1441 Value of 0x80 indicates invalid. 1442 */ 1443 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 1444 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1445 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 1446 1447 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 1448 1449 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 1450 bandwidth. 1451 1452 Value of 0x80 indicates invalid. 1453 */ 1454 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 1455 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1456 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 1457 1458 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 1459 1460 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1461 bandwidth. 1462 1463 Value of 0x80 indicates invalid. 1464 */ 1465 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 1466 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1467 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1468 1469 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1470 1471 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1472 bandwidth. 1473 1474 Value of 0x80 indicates invalid. 1475 */ 1476 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 1477 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1478 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1479 1480 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1481 1482 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1483 MHz bandwidth. 1484 1485 Value of 0x80 indicates invalid. 1486 */ 1487 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 1488 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1489 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1490 1491 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1492 1493 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1494 MHz bandwidth. 1495 1496 Value of 0x80 indicates invalid. 1497 */ 1498 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 1499 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1500 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1501 1502 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1503 1504 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1505 bandwidth. 1506 1507 Value of 0x80 indicates invalid. 1508 */ 1509 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 1510 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1511 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1512 1513 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1514 1515 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1516 1517 Value of 0x80 indicates invalid. 1518 */ 1519 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c 1520 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1521 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1522 1523 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1524 1525 RSSI of RX PPDU on chain 4 of extension 20 MHz 1526 bandwidth. 1527 1528 Value of 0x80 indicates invalid. 1529 */ 1530 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c 1531 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1532 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1533 1534 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1535 1536 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1537 bandwidth. 1538 1539 Value of 0x80 indicates invalid. 1540 */ 1541 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c 1542 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1543 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1544 1545 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1546 1547 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1548 bandwidth. 1549 1550 Value of 0x80 indicates invalid. 1551 */ 1552 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c 1553 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1554 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1555 1556 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1557 1558 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1559 bandwidth. 1560 1561 Value of 0x80 indicates invalid. 1562 */ 1563 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 1564 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1565 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1566 1567 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1568 1569 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1570 MHz bandwidth. 1571 1572 Value of 0x80 indicates invalid. 1573 */ 1574 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 1575 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1576 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1577 1578 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1579 1580 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1581 MHz bandwidth. 1582 1583 Value of 0x80 indicates invalid. 1584 */ 1585 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 1586 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1587 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1588 1589 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1590 1591 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1592 bandwidth. 1593 1594 Value of 0x80 indicates invalid. 1595 */ 1596 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 1597 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1598 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1599 1600 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1601 1602 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1603 1604 Value of 0x80 indicates invalid. 1605 */ 1606 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 1607 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1608 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1609 1610 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1611 1612 RSSI of RX PPDU on chain 5 of extension 20 MHz 1613 bandwidth. 1614 1615 Value of 0x80 indicates invalid. 1616 */ 1617 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 1618 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1619 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1620 1621 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1622 1623 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1624 bandwidth. 1625 1626 Value of 0x80 indicates invalid. 1627 */ 1628 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 1629 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1630 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1631 1632 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1633 1634 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1635 bandwidth. 1636 1637 Value of 0x80 indicates invalid. 1638 */ 1639 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 1640 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1641 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1642 1643 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1644 1645 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1646 bandwidth. 1647 1648 Value of 0x80 indicates invalid. 1649 */ 1650 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 1651 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1652 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1653 1654 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1655 1656 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1657 MHz bandwidth. 1658 1659 Value of 0x80 indicates invalid. 1660 */ 1661 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 1662 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1663 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1664 1665 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1666 1667 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1668 MHz bandwidth. 1669 1670 Value of 0x80 indicates invalid. 1671 */ 1672 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 1673 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1674 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1675 1676 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1677 1678 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1679 bandwidth. 1680 1681 Value of 0x80 indicates invalid. 1682 */ 1683 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 1684 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1685 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1686 1687 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1688 1689 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1690 1691 Value of 0x80 indicates invalid. 1692 */ 1693 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c 1694 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1695 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1696 1697 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1698 1699 RSSI of RX PPDU on chain 6 of extension 20 MHz 1700 bandwidth. 1701 1702 Value of 0x80 indicates invalid. 1703 */ 1704 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c 1705 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1706 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1707 1708 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1709 1710 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1711 bandwidth. 1712 1713 Value of 0x80 indicates invalid. 1714 */ 1715 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c 1716 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1717 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1718 1719 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1720 1721 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1722 bandwidth. 1723 1724 Value of 0x80 indicates invalid. 1725 */ 1726 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c 1727 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1728 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1729 1730 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1731 1732 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1733 bandwidth. 1734 1735 Value of 0x80 indicates invalid. 1736 */ 1737 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 1738 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1739 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1740 1741 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1742 1743 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1744 MHz bandwidth. 1745 1746 Value of 0x80 indicates invalid. 1747 */ 1748 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 1749 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1750 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1751 1752 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1753 1754 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1755 MHz bandwidth. 1756 1757 Value of 0x80 indicates invalid. 1758 */ 1759 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 1760 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1761 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1762 1763 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 1764 1765 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 1766 bandwidth. 1767 1768 Value of 0x80 indicates invalid. 1769 */ 1770 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 1771 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 1772 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 1773 1774 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 1775 1776 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 1777 1778 Value of 0x80 indicates invalid. 1779 */ 1780 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 1781 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 1782 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 1783 1784 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 1785 1786 RSSI of RX PPDU on chain 7 of extension 20 MHz 1787 bandwidth. 1788 1789 Value of 0x80 indicates invalid. 1790 */ 1791 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 1792 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 1793 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 1794 1795 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 1796 1797 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 1798 bandwidth. 1799 1800 Value of 0x80 indicates invalid. 1801 */ 1802 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 1803 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 1804 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 1805 1806 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 1807 1808 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 1809 bandwidth. 1810 1811 Value of 0x80 indicates invalid. 1812 */ 1813 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 1814 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 1815 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 1816 1817 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 1818 1819 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 1820 bandwidth. 1821 1822 Value of 0x80 indicates invalid. 1823 */ 1824 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 1825 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 1826 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 1827 1828 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 1829 1830 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 1831 MHz bandwidth. 1832 1833 Value of 0x80 indicates invalid. 1834 */ 1835 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 1836 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 1837 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 1838 1839 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 1840 1841 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 1842 MHz bandwidth. 1843 1844 Value of 0x80 indicates invalid. 1845 */ 1846 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 1847 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 1848 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 1849 1850 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 1851 1852 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 1853 bandwidth. 1854 1855 Value of 0x80 indicates invalid. 1856 */ 1857 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 1858 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 1859 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 1860 1861 /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 1862 1863 Some PHY micro code status that can be put in here. 1864 Details of definition within SW specification 1865 1866 This field can be used for debugging, FW - SW message 1867 exchange, etc. 1868 1869 It could for example be a pointer to a DDR memory 1870 location where PHY FW put some debug info. 1871 1872 <legal all> 1873 */ 1874 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 1875 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 1876 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 1877 1878 /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 1879 1880 Some PHY micro code status that can be put in here. 1881 Details of definition within SW specification 1882 1883 This field can be used for debugging, FW - SW message 1884 exchange, etc. 1885 1886 It could for example be a pointer to a DDR memory 1887 location where PHY FW put some debug info. 1888 1889 <legal all> 1890 */ 1891 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 1892 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 1893 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 1894 1895 1896 #endif // _PHYRX_PKT_END_INFO_H_ 1897