1 /*
2  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
19 #define _UNIFORM_DESCRIPTOR_HEADER_H_
20 
21 #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
22 
23 struct uniform_descriptor_header {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t owner                                                   :  4,
26                       buffer_type                                             :  4,
27                       tx_mpdu_queue_number                                    : 20,
28                       reserved_0a                                             :  4;
29 #else
30              uint32_t reserved_0a                                             :  4,
31                       tx_mpdu_queue_number                                    : 20,
32                       buffer_type                                             :  4,
33                       owner                                                   :  4;
34 #endif
35 };
36 
37 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET                                      0x00000000
38 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB                                         0
39 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB                                         3
40 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK                                        0x0000000f
41 
42 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                                0x00000000
43 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                                   4
44 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                                   7
45 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                                  0x000000f0
46 
47 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                       0x00000000
48 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                          8
49 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
50 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
51 
52 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
53 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
54 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
55 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
56 
57 #endif
58