1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _TX_MPDU_START_H_ 19 #define _TX_MPDU_START_H_ 20 21 #define NUM_OF_DWORDS_TX_MPDU_START 9 22 23 struct tx_mpdu_start { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t mpdu_length : 14, 26 frame_not_from_tqm : 1, 27 vht_control_present : 1, 28 mpdu_header_length : 8, 29 retry_count : 7, 30 wds : 1; 31 uint32_t pn_31_0 : 32; 32 uint32_t pn_47_32 : 16, 33 mpdu_sequence_number : 12, 34 raw_already_encrypted : 1, 35 frame_type : 2, 36 txdma_dropped_mpdu_warning : 1; 37 uint32_t iv_byte_0 : 8, 38 iv_byte_1 : 8, 39 iv_byte_2 : 8, 40 iv_byte_3 : 8; 41 uint32_t iv_byte_4 : 8, 42 iv_byte_5 : 8, 43 iv_byte_6 : 8, 44 iv_byte_7 : 8; 45 uint32_t iv_byte_8 : 8, 46 iv_byte_9 : 8, 47 iv_byte_10 : 8, 48 iv_byte_11 : 8; 49 uint32_t iv_byte_12 : 8, 50 iv_byte_13 : 8, 51 iv_byte_14 : 8, 52 iv_byte_15 : 8; 53 uint32_t iv_byte_16 : 8, 54 iv_byte_17 : 8, 55 iv_len : 5, 56 icv_len : 5, 57 vht_control_offset : 6; 58 uint32_t mpdu_type : 1, 59 transmit_bw_restriction : 1, 60 allowed_transmit_bw : 4, 61 tx_notify_frame : 3, 62 reserved_8a : 23; 63 #else 64 uint32_t wds : 1, 65 retry_count : 7, 66 mpdu_header_length : 8, 67 vht_control_present : 1, 68 frame_not_from_tqm : 1, 69 mpdu_length : 14; 70 uint32_t pn_31_0 : 32; 71 uint32_t txdma_dropped_mpdu_warning : 1, 72 frame_type : 2, 73 raw_already_encrypted : 1, 74 mpdu_sequence_number : 12, 75 pn_47_32 : 16; 76 uint32_t iv_byte_3 : 8, 77 iv_byte_2 : 8, 78 iv_byte_1 : 8, 79 iv_byte_0 : 8; 80 uint32_t iv_byte_7 : 8, 81 iv_byte_6 : 8, 82 iv_byte_5 : 8, 83 iv_byte_4 : 8; 84 uint32_t iv_byte_11 : 8, 85 iv_byte_10 : 8, 86 iv_byte_9 : 8, 87 iv_byte_8 : 8; 88 uint32_t iv_byte_15 : 8, 89 iv_byte_14 : 8, 90 iv_byte_13 : 8, 91 iv_byte_12 : 8; 92 uint32_t vht_control_offset : 6, 93 icv_len : 5, 94 iv_len : 5, 95 iv_byte_17 : 8, 96 iv_byte_16 : 8; 97 uint32_t reserved_8a : 23, 98 tx_notify_frame : 3, 99 allowed_transmit_bw : 4, 100 transmit_bw_restriction : 1, 101 mpdu_type : 1; 102 #endif 103 }; 104 105 #define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x00000000 106 #define TX_MPDU_START_MPDU_LENGTH_LSB 0 107 #define TX_MPDU_START_MPDU_LENGTH_MSB 13 108 #define TX_MPDU_START_MPDU_LENGTH_MASK 0x00003fff 109 110 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x00000000 111 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 112 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 113 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x00004000 114 115 #define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x00000000 116 #define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 117 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 118 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x00008000 119 120 #define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x00000000 121 #define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 122 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 123 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x00ff0000 124 125 #define TX_MPDU_START_RETRY_COUNT_OFFSET 0x00000000 126 #define TX_MPDU_START_RETRY_COUNT_LSB 24 127 #define TX_MPDU_START_RETRY_COUNT_MSB 30 128 #define TX_MPDU_START_RETRY_COUNT_MASK 0x7f000000 129 130 #define TX_MPDU_START_WDS_OFFSET 0x00000000 131 #define TX_MPDU_START_WDS_LSB 31 132 #define TX_MPDU_START_WDS_MSB 31 133 #define TX_MPDU_START_WDS_MASK 0x80000000 134 135 #define TX_MPDU_START_PN_31_0_OFFSET 0x00000004 136 #define TX_MPDU_START_PN_31_0_LSB 0 137 #define TX_MPDU_START_PN_31_0_MSB 31 138 #define TX_MPDU_START_PN_31_0_MASK 0xffffffff 139 140 #define TX_MPDU_START_PN_47_32_OFFSET 0x00000008 141 #define TX_MPDU_START_PN_47_32_LSB 0 142 #define TX_MPDU_START_PN_47_32_MSB 15 143 #define TX_MPDU_START_PN_47_32_MASK 0x0000ffff 144 145 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 146 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 147 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 148 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x0fff0000 149 150 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x00000008 151 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 152 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 153 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x10000000 154 155 #define TX_MPDU_START_FRAME_TYPE_OFFSET 0x00000008 156 #define TX_MPDU_START_FRAME_TYPE_LSB 29 157 #define TX_MPDU_START_FRAME_TYPE_MSB 30 158 #define TX_MPDU_START_FRAME_TYPE_MASK 0x60000000 159 160 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000008 161 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 162 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 163 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x80000000 164 165 #define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000c 166 #define TX_MPDU_START_IV_BYTE_0_LSB 0 167 #define TX_MPDU_START_IV_BYTE_0_MSB 7 168 #define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff 169 170 #define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000c 171 #define TX_MPDU_START_IV_BYTE_1_LSB 8 172 #define TX_MPDU_START_IV_BYTE_1_MSB 15 173 #define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff00 174 175 #define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000c 176 #define TX_MPDU_START_IV_BYTE_2_LSB 16 177 #define TX_MPDU_START_IV_BYTE_2_MSB 23 178 #define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff0000 179 180 #define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000c 181 #define TX_MPDU_START_IV_BYTE_3_LSB 24 182 #define TX_MPDU_START_IV_BYTE_3_MSB 31 183 #define TX_MPDU_START_IV_BYTE_3_MASK 0xff000000 184 185 #define TX_MPDU_START_IV_BYTE_4_OFFSET 0x00000010 186 #define TX_MPDU_START_IV_BYTE_4_LSB 0 187 #define TX_MPDU_START_IV_BYTE_4_MSB 7 188 #define TX_MPDU_START_IV_BYTE_4_MASK 0x000000ff 189 190 #define TX_MPDU_START_IV_BYTE_5_OFFSET 0x00000010 191 #define TX_MPDU_START_IV_BYTE_5_LSB 8 192 #define TX_MPDU_START_IV_BYTE_5_MSB 15 193 #define TX_MPDU_START_IV_BYTE_5_MASK 0x0000ff00 194 195 #define TX_MPDU_START_IV_BYTE_6_OFFSET 0x00000010 196 #define TX_MPDU_START_IV_BYTE_6_LSB 16 197 #define TX_MPDU_START_IV_BYTE_6_MSB 23 198 #define TX_MPDU_START_IV_BYTE_6_MASK 0x00ff0000 199 200 #define TX_MPDU_START_IV_BYTE_7_OFFSET 0x00000010 201 #define TX_MPDU_START_IV_BYTE_7_LSB 24 202 #define TX_MPDU_START_IV_BYTE_7_MSB 31 203 #define TX_MPDU_START_IV_BYTE_7_MASK 0xff000000 204 205 #define TX_MPDU_START_IV_BYTE_8_OFFSET 0x00000014 206 #define TX_MPDU_START_IV_BYTE_8_LSB 0 207 #define TX_MPDU_START_IV_BYTE_8_MSB 7 208 #define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff 209 210 #define TX_MPDU_START_IV_BYTE_9_OFFSET 0x00000014 211 #define TX_MPDU_START_IV_BYTE_9_LSB 8 212 #define TX_MPDU_START_IV_BYTE_9_MSB 15 213 #define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff00 214 215 #define TX_MPDU_START_IV_BYTE_10_OFFSET 0x00000014 216 #define TX_MPDU_START_IV_BYTE_10_LSB 16 217 #define TX_MPDU_START_IV_BYTE_10_MSB 23 218 #define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff0000 219 220 #define TX_MPDU_START_IV_BYTE_11_OFFSET 0x00000014 221 #define TX_MPDU_START_IV_BYTE_11_LSB 24 222 #define TX_MPDU_START_IV_BYTE_11_MSB 31 223 #define TX_MPDU_START_IV_BYTE_11_MASK 0xff000000 224 225 #define TX_MPDU_START_IV_BYTE_12_OFFSET 0x00000018 226 #define TX_MPDU_START_IV_BYTE_12_LSB 0 227 #define TX_MPDU_START_IV_BYTE_12_MSB 7 228 #define TX_MPDU_START_IV_BYTE_12_MASK 0x000000ff 229 230 #define TX_MPDU_START_IV_BYTE_13_OFFSET 0x00000018 231 #define TX_MPDU_START_IV_BYTE_13_LSB 8 232 #define TX_MPDU_START_IV_BYTE_13_MSB 15 233 #define TX_MPDU_START_IV_BYTE_13_MASK 0x0000ff00 234 235 #define TX_MPDU_START_IV_BYTE_14_OFFSET 0x00000018 236 #define TX_MPDU_START_IV_BYTE_14_LSB 16 237 #define TX_MPDU_START_IV_BYTE_14_MSB 23 238 #define TX_MPDU_START_IV_BYTE_14_MASK 0x00ff0000 239 240 #define TX_MPDU_START_IV_BYTE_15_OFFSET 0x00000018 241 #define TX_MPDU_START_IV_BYTE_15_LSB 24 242 #define TX_MPDU_START_IV_BYTE_15_MSB 31 243 #define TX_MPDU_START_IV_BYTE_15_MASK 0xff000000 244 245 #define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000001c 246 #define TX_MPDU_START_IV_BYTE_16_LSB 0 247 #define TX_MPDU_START_IV_BYTE_16_MSB 7 248 #define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff 249 250 #define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000001c 251 #define TX_MPDU_START_IV_BYTE_17_LSB 8 252 #define TX_MPDU_START_IV_BYTE_17_MSB 15 253 #define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff00 254 255 #define TX_MPDU_START_IV_LEN_OFFSET 0x0000001c 256 #define TX_MPDU_START_IV_LEN_LSB 16 257 #define TX_MPDU_START_IV_LEN_MSB 20 258 #define TX_MPDU_START_IV_LEN_MASK 0x001f0000 259 260 #define TX_MPDU_START_ICV_LEN_OFFSET 0x0000001c 261 #define TX_MPDU_START_ICV_LEN_LSB 21 262 #define TX_MPDU_START_ICV_LEN_MSB 25 263 #define TX_MPDU_START_ICV_LEN_MASK 0x03e00000 264 265 #define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000001c 266 #define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 26 267 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 31 268 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc000000 269 270 #define TX_MPDU_START_MPDU_TYPE_OFFSET 0x00000020 271 #define TX_MPDU_START_MPDU_TYPE_LSB 0 272 #define TX_MPDU_START_MPDU_TYPE_MSB 0 273 #define TX_MPDU_START_MPDU_TYPE_MASK 0x00000001 274 275 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x00000020 276 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 277 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 278 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x00000002 279 280 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x00000020 281 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 282 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 283 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x0000003c 284 285 #define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x00000020 286 #define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 287 #define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 288 #define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x000001c0 289 290 #define TX_MPDU_START_RESERVED_8A_OFFSET 0x00000020 291 #define TX_MPDU_START_RESERVED_8A_LSB 9 292 #define TX_MPDU_START_RESERVED_8A_MSB 31 293 #define TX_MPDU_START_RESERVED_8A_MASK 0xfffffe00 294 295 #endif 296