1 /* 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RXPCU_PPDU_END_INFO_H_ 19 #define _RXPCU_PPDU_END_INFO_H_ 20 21 #include "phyrx_abort_request_info.h" 22 #include "macrx_abort_request_info.h" 23 #include "rxpcu_ppdu_end_layout_info.h" 24 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 31 25 26 struct rxpcu_ppdu_end_info { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 uint32_t wb_timestamp_lower_32 : 32; 29 uint32_t wb_timestamp_upper_32 : 32; 30 uint32_t rx_antenna : 24, 31 tx_ht_vht_ack : 1, 32 unsupported_mu_nc : 1, 33 otp_txbf_disable : 1, 34 previous_tlv_corrupted : 1, 35 phyrx_abort_request_info_valid : 1, 36 macrx_abort_request_info_valid : 1, 37 reserved : 2; 38 uint32_t coex_bt_tx_from_start_of_rx : 1, 39 coex_bt_tx_after_start_of_rx : 1, 40 coex_wan_tx_from_start_of_rx : 1, 41 coex_wan_tx_after_start_of_rx : 1, 42 coex_wlan_tx_from_start_of_rx : 1, 43 coex_wlan_tx_after_start_of_rx : 1, 44 mpdu_delimiter_errors_seen : 1, 45 __reserved_g_0012 : 2, 46 dialog_token : 8, 47 follow_up_dialog_token : 8, 48 bb_captured_channel : 1, 49 bb_captured_reason : 3, 50 bb_captured_timeout : 1, 51 coex_uwb_tx_after_start_of_rx : 1, 52 coex_uwb_tx_from_start_of_rx : 1; 53 uint32_t before_mpdu_count_passing_fcs : 10, 54 before_mpdu_count_failing_fcs : 10, 55 after_mpdu_count_passing_fcs : 10, 56 reserved_4 : 2; 57 uint32_t after_mpdu_count_failing_fcs : 10, 58 reserved_5 : 22; 59 uint32_t phy_timestamp_tx_lower_32 : 32; 60 uint32_t phy_timestamp_tx_upper_32 : 32; 61 uint32_t bb_length : 16, 62 bb_data : 1, 63 reserved_8 : 3, 64 first_bt_broadcast_status_details : 12; 65 uint32_t rx_ppdu_duration : 24, 66 reserved_9 : 8; 67 uint32_t ast_index : 16, 68 ast_index_valid : 1, 69 reserved_10 : 3, 70 second_bt_broadcast_status_details : 12; 71 struct phyrx_abort_request_info phyrx_abort_request_info_details; 72 struct macrx_abort_request_info macrx_abort_request_info_details; 73 uint16_t pre_bt_broadcast_status_details : 12, 74 reserved_12a : 4; 75 uint32_t non_qos_sn_info_valid : 1, 76 rts_or_trig_protected_ppdu : 1, 77 rts_or_trig_prot_type : 2, 78 reserved_13a : 2, 79 non_qos_sn_highest : 12, 80 non_qos_sn_highest_retry_setting : 1, 81 non_qos_sn_lowest : 12, 82 non_qos_sn_lowest_retry_setting : 1; 83 uint32_t qos_sn_1_info_valid : 1, 84 reserved_14a : 1, 85 qos_sn_1_tid : 4, 86 qos_sn_1_highest : 12, 87 qos_sn_1_highest_retry_setting : 1, 88 qos_sn_1_lowest : 12, 89 qos_sn_1_lowest_retry_setting : 1; 90 uint32_t qos_sn_2_info_valid : 1, 91 reserved_15a : 1, 92 qos_sn_2_tid : 4, 93 qos_sn_2_highest : 12, 94 qos_sn_2_highest_retry_setting : 1, 95 qos_sn_2_lowest : 12, 96 qos_sn_2_lowest_retry_setting : 1; 97 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 98 uint32_t corrupted_due_to_fifo_delay : 1, 99 qos_sn_1_more_frag_state : 1, 100 qos_sn_1_frag_num_state : 4, 101 qos_sn_2_more_frag_state : 1, 102 qos_sn_2_frag_num_state : 4, 103 rts_or_trig_prot_non_11a : 1, 104 rts_or_trig_prot_rate_mcs : 4, 105 rts_or_trig_prot_peer_addr_15_0 : 16; 106 uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; 107 uint32_t rts_or_trig_rx_count : 32; 108 uint32_t cts_or_null_tx_count : 32; 109 uint32_t rx_ppdu_end_marker : 32; 110 #else 111 uint32_t wb_timestamp_lower_32 : 32; 112 uint32_t wb_timestamp_upper_32 : 32; 113 uint32_t reserved : 2, 114 macrx_abort_request_info_valid : 1, 115 phyrx_abort_request_info_valid : 1, 116 previous_tlv_corrupted : 1, 117 otp_txbf_disable : 1, 118 unsupported_mu_nc : 1, 119 tx_ht_vht_ack : 1, 120 rx_antenna : 24; 121 uint32_t coex_uwb_tx_from_start_of_rx : 1, 122 coex_uwb_tx_after_start_of_rx : 1, 123 bb_captured_timeout : 1, 124 bb_captured_reason : 3, 125 bb_captured_channel : 1, 126 follow_up_dialog_token : 8, 127 dialog_token : 8, 128 __reserved_g_0012 : 2, 129 mpdu_delimiter_errors_seen : 1, 130 coex_wlan_tx_after_start_of_rx : 1, 131 coex_wlan_tx_from_start_of_rx : 1, 132 coex_wan_tx_after_start_of_rx : 1, 133 coex_wan_tx_from_start_of_rx : 1, 134 coex_bt_tx_after_start_of_rx : 1, 135 coex_bt_tx_from_start_of_rx : 1; 136 uint32_t reserved_4 : 2, 137 after_mpdu_count_passing_fcs : 10, 138 before_mpdu_count_failing_fcs : 10, 139 before_mpdu_count_passing_fcs : 10; 140 uint32_t reserved_5 : 22, 141 after_mpdu_count_failing_fcs : 10; 142 uint32_t phy_timestamp_tx_lower_32 : 32; 143 uint32_t phy_timestamp_tx_upper_32 : 32; 144 uint32_t first_bt_broadcast_status_details : 12, 145 reserved_8 : 3, 146 bb_data : 1, 147 bb_length : 16; 148 uint32_t reserved_9 : 8, 149 rx_ppdu_duration : 24; 150 uint32_t second_bt_broadcast_status_details : 12, 151 reserved_10 : 3, 152 ast_index_valid : 1, 153 ast_index : 16; 154 struct phyrx_abort_request_info phyrx_abort_request_info_details; 155 uint32_t reserved_12a : 4, 156 pre_bt_broadcast_status_details : 12; 157 struct macrx_abort_request_info macrx_abort_request_info_details; 158 uint32_t non_qos_sn_lowest_retry_setting : 1, 159 non_qos_sn_lowest : 12, 160 non_qos_sn_highest_retry_setting : 1, 161 non_qos_sn_highest : 12, 162 reserved_13a : 2, 163 rts_or_trig_prot_type : 2, 164 rts_or_trig_protected_ppdu : 1, 165 non_qos_sn_info_valid : 1; 166 uint32_t qos_sn_1_lowest_retry_setting : 1, 167 qos_sn_1_lowest : 12, 168 qos_sn_1_highest_retry_setting : 1, 169 qos_sn_1_highest : 12, 170 qos_sn_1_tid : 4, 171 reserved_14a : 1, 172 qos_sn_1_info_valid : 1; 173 uint32_t qos_sn_2_lowest_retry_setting : 1, 174 qos_sn_2_lowest : 12, 175 qos_sn_2_highest_retry_setting : 1, 176 qos_sn_2_highest : 12, 177 qos_sn_2_tid : 4, 178 reserved_15a : 1, 179 qos_sn_2_info_valid : 1; 180 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 181 uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, 182 rts_or_trig_prot_rate_mcs : 4, 183 rts_or_trig_prot_non_11a : 1, 184 qos_sn_2_frag_num_state : 4, 185 qos_sn_2_more_frag_state : 1, 186 qos_sn_1_frag_num_state : 4, 187 qos_sn_1_more_frag_state : 1, 188 corrupted_due_to_fifo_delay : 1; 189 uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; 190 uint32_t rts_or_trig_rx_count : 32; 191 uint32_t cts_or_null_tx_count : 32; 192 uint32_t rx_ppdu_end_marker : 32; 193 #endif 194 }; 195 196 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 197 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 198 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 199 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff 200 201 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 202 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 0 203 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 31 204 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff 205 206 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x00000008 207 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 208 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 209 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x00ffffff 210 211 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x00000008 212 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 213 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 214 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x01000000 215 216 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x00000008 217 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 218 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 219 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x02000000 220 221 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x00000008 222 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 223 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 224 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x04000000 225 226 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 227 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 228 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 229 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 230 231 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 232 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 233 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 234 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 235 236 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 237 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 238 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 239 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 240 241 #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x00000008 242 #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 243 #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 244 #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0xc0000000 245 246 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c 247 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 0 248 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 0 249 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 250 251 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 252 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 253 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 1 254 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 255 256 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 257 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 258 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 2 259 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 260 261 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 262 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 263 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 3 264 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 265 266 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 267 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 268 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 4 269 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 270 271 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 272 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 273 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 5 274 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 275 276 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c 277 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 278 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 6 279 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 280 281 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000c 282 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 9 283 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 16 284 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe00 285 286 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c 287 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 17 288 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 24 289 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 290 291 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c 292 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 25 293 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 25 294 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x02000000 295 296 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000c 297 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 26 298 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 28 299 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c000000 300 301 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c 302 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 29 303 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 29 304 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x20000000 305 306 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 307 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_LSB 30 308 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MSB 30 309 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MASK 0x40000000 310 311 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_OFFSET 0x0000000c 312 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_LSB 31 313 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MSB 31 314 #define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MASK 0x80000000 315 316 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 317 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 318 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 319 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff 320 321 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 322 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 323 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 324 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 325 326 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 327 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 328 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 329 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 330 331 #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x00000010 332 #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 333 #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 334 #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0xc0000000 335 336 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 337 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 338 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 9 339 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff 340 341 #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x00000014 342 #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 10 343 #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 31 344 #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc00 345 346 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 347 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 348 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 349 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff 350 351 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c 352 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 353 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 31 354 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff 355 356 #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x00000020 357 #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 358 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 359 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x0000ffff 360 361 #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x00000020 362 #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 363 #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 364 #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x00010000 365 366 #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x00000020 367 #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 368 #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 369 #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x000e0000 370 371 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 372 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 373 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 374 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 375 376 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x00000024 377 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 0 378 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 23 379 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff 380 381 #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x00000024 382 #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 24 383 #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 31 384 #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff000000 385 386 #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x00000028 387 #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 388 #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 389 #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x0000ffff 390 391 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x00000028 392 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 393 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 394 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x00010000 395 396 #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x00000028 397 #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 398 #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 399 #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x000e0000 400 401 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 402 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 403 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 404 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 405 406 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c 407 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 408 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 7 409 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff 410 411 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c 412 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 413 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 8 414 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 415 416 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c 417 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 418 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 9 419 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 420 421 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000002c 422 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 10 423 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 10 424 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 425 426 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000002c 427 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 11 428 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 11 429 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x00000800 430 431 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000002c 432 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 12 433 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 12 434 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x00001000 435 436 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000002c 437 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 13 438 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 13 439 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x00002000 440 441 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000002c 442 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 14 443 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 14 444 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x00004000 445 446 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c 447 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 15 448 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 449 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x00008000 450 451 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c 452 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 453 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 31 454 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 455 456 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 457 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 458 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 459 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff 460 461 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 462 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 463 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 464 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 465 466 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000030 467 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 468 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 469 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0fff0000 470 471 #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x00000030 472 #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 473 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 474 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0xf0000000 475 476 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x00000034 477 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 0 478 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 0 479 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x00000001 480 481 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x00000034 482 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 1 483 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 1 484 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x00000002 485 486 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x00000034 487 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 2 488 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 3 489 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c 490 491 #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x00000034 492 #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 4 493 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 5 494 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x00000030 495 496 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x00000034 497 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 6 498 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 17 499 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc0 500 501 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x00000034 502 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 18 503 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 18 504 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x00040000 505 506 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x00000034 507 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 19 508 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 30 509 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff80000 510 511 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x00000034 512 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 31 513 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 31 514 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x80000000 515 516 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x00000038 517 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 518 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 519 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x00000001 520 521 #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x00000038 522 #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 523 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 524 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x00000002 525 526 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x00000038 527 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 528 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 529 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x0000003c 530 531 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x00000038 532 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 533 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 534 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x0003ffc0 535 536 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x00000038 537 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 538 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 539 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x00040000 540 541 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x00000038 542 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 543 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 544 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x7ff80000 545 546 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x00000038 547 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 548 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 549 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x80000000 550 551 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000003c 552 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 0 553 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 0 554 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x00000001 555 556 #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000003c 557 #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 1 558 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 1 559 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x00000002 560 561 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000003c 562 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 2 563 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 5 564 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c 565 566 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000003c 567 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 6 568 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 17 569 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc0 570 571 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000003c 572 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 18 573 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 18 574 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x00040000 575 576 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000003c 577 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 19 578 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 30 579 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff80000 580 581 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000003c 582 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 31 583 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 31 584 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x80000000 585 586 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x00000040 587 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 588 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 589 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x00000003 590 591 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x00000040 592 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 593 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 594 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x000000fc 595 596 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x00000040 597 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 598 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 599 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x00003f00 600 601 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x00000040 602 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 603 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 604 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x000fc000 605 606 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x00000040 607 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 608 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 609 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x03f00000 610 611 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000040 612 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 613 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 614 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 615 616 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x00000044 617 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 0 618 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 5 619 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f 620 621 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000044 622 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 6 623 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 11 624 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 625 626 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000044 627 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 12 628 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 17 629 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 630 631 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x00000044 632 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 18 633 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 23 634 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 635 636 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x00000044 637 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 24 638 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 30 639 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f000000 640 641 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x00000044 642 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 31 643 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 31 644 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x80000000 645 646 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000048 647 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 648 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 649 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f 650 651 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000048 652 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 653 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 654 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 655 656 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000048 657 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 658 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 659 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 660 661 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000048 662 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 663 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 664 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 665 666 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x00000048 667 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 668 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 669 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0xf0000000 670 671 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000004c 672 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 0 673 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 6 674 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f 675 676 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000004c 677 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 7 678 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 13 679 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 680 681 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000004c 682 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 14 683 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 20 684 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 685 686 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000004c 687 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 21 688 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 27 689 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 690 691 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000004c 692 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 28 693 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 31 694 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf0000000 695 696 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000050 697 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 698 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 699 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f 700 701 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000050 702 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 703 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 704 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 705 706 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000050 707 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 708 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 709 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 710 711 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000050 712 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 713 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 714 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 715 716 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000050 717 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 718 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 719 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 720 721 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x00000050 722 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 723 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 724 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0xe0000000 725 726 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x00000054 727 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 0 728 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 6 729 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f 730 731 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000054 732 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 7 733 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 14 734 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 735 736 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000054 737 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 738 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 739 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 740 741 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000054 742 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 743 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 744 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 745 746 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000054 747 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 748 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 749 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 750 751 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x00000054 752 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 25 753 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 31 754 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe000000 755 756 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x00000058 757 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 758 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 759 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x000000ff 760 761 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000058 762 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 763 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 764 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 765 766 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x00000058 767 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 768 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 769 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x00ff0000 770 771 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x00000058 772 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 773 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 774 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0xff000000 775 776 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000005c 777 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 8 778 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 15 779 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff00 780 781 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000005c 782 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 16 783 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 23 784 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 785 786 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000005c 787 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 24 788 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 31 789 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff000000 790 791 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x00000060 792 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 793 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 794 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0xffffffff 795 796 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x00000064 797 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 0 798 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 31 799 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff 800 801 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x00000068 802 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 803 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 804 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 805 806 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x00000068 807 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 808 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 809 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x00000002 810 811 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x00000068 812 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 813 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 814 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x0000003c 815 816 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x00000068 817 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 818 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 819 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x00000040 820 821 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x00000068 822 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 823 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 824 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x00000780 825 826 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x00000068 827 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 828 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 829 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x00000800 830 831 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x00000068 832 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 833 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 834 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x0000f000 835 836 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x00000068 837 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 838 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 839 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0xffff0000 840 841 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000006c 842 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 0 843 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 31 844 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff 845 846 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x00000070 847 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 848 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 849 #define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0xffffffff 850 851 #define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x00000074 852 #define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 0 853 #define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 31 854 #define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff 855 856 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x00000078 857 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 0 858 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 31 859 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff 860 861 #endif 862