1  /*
2   * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for any
5   * purpose with or without fee is hereby granted, provided that the above
6   * copyright notice and this permission notice appear in all copies.
7   *
8   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9   * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10   * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11   * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12   * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13   * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15   */
16  
17  
18  #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
19  #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
20  
21  #include "uniform_reo_status_header.h"
22  #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 27
23  
24  struct reo_update_rx_reo_queue_status {
25  #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
26               uint32_t tlv32_ring_padding                                      : 32;
27               struct   uniform_reo_status_header                                 status_header;
28               uint32_t reserved_2a                                             : 32;
29               uint32_t reserved_3a                                             : 32;
30               uint32_t reserved_4a                                             : 32;
31               uint32_t reserved_5a                                             : 32;
32               uint32_t reserved_6a                                             : 32;
33               uint32_t reserved_7a                                             : 32;
34               uint32_t reserved_8a                                             : 32;
35               uint32_t reserved_9a                                             : 32;
36               uint32_t reserved_10a                                            : 32;
37               uint32_t reserved_11a                                            : 32;
38               uint32_t reserved_12a                                            : 32;
39               uint32_t reserved_13a                                            : 32;
40               uint32_t reserved_14a                                            : 32;
41               uint32_t reserved_15a                                            : 32;
42               uint32_t reserved_16a                                            : 32;
43               uint32_t reserved_17a                                            : 32;
44               uint32_t reserved_18a                                            : 32;
45               uint32_t reserved_19a                                            : 32;
46               uint32_t reserved_20a                                            : 32;
47               uint32_t reserved_21a                                            : 32;
48               uint32_t reserved_22a                                            : 32;
49               uint32_t reserved_23a                                            : 32;
50               uint32_t reserved_24a                                            : 32;
51               uint32_t reserved_25a                                            : 28,
52                        looping_count                                           :  4;
53  #else
54               uint32_t tlv32_ring_padding                                      : 32;
55               struct   uniform_reo_status_header                                 status_header;
56               uint32_t reserved_2a                                             : 32;
57               uint32_t reserved_3a                                             : 32;
58               uint32_t reserved_4a                                             : 32;
59               uint32_t reserved_5a                                             : 32;
60               uint32_t reserved_6a                                             : 32;
61               uint32_t reserved_7a                                             : 32;
62               uint32_t reserved_8a                                             : 32;
63               uint32_t reserved_9a                                             : 32;
64               uint32_t reserved_10a                                            : 32;
65               uint32_t reserved_11a                                            : 32;
66               uint32_t reserved_12a                                            : 32;
67               uint32_t reserved_13a                                            : 32;
68               uint32_t reserved_14a                                            : 32;
69               uint32_t reserved_15a                                            : 32;
70               uint32_t reserved_16a                                            : 32;
71               uint32_t reserved_17a                                            : 32;
72               uint32_t reserved_18a                                            : 32;
73               uint32_t reserved_19a                                            : 32;
74               uint32_t reserved_20a                                            : 32;
75               uint32_t reserved_21a                                            : 32;
76               uint32_t reserved_22a                                            : 32;
77               uint32_t reserved_23a                                            : 32;
78               uint32_t reserved_24a                                            : 32;
79               uint32_t looping_count                                           :  4,
80                        reserved_25a                                            : 28;
81  #endif
82  };
83  
84  #define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET                    0x00000000
85  #define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_LSB                       0
86  #define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MSB                       31
87  #define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MASK                      0xffffffff
88  
89  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET       0x00000004
90  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB          0
91  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB          15
92  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK         0x0000ffff
93  
94  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET      0x00000004
95  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB         16
96  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB         25
97  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK        0x03ff0000
98  
99  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
100  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB   26
101  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB   27
102  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK  0x0c000000
103  
104  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET             0x00000004
105  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                28
106  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                31
107  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK               0xf0000000
108  
109  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET               0x00000008
110  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                  0
111  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                  31
112  #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                 0xffffffff
113  
114  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET                           0x0000000c
115  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB                              0
116  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB                              31
117  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK                             0xffffffff
118  
119  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET                           0x00000010
120  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB                              0
121  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB                              31
122  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK                             0xffffffff
123  
124  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET                           0x00000014
125  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB                              0
126  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB                              31
127  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK                             0xffffffff
128  
129  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET                           0x00000018
130  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB                              0
131  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB                              31
132  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK                             0xffffffff
133  
134  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET                           0x0000001c
135  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB                              0
136  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB                              31
137  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK                             0xffffffff
138  
139  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET                           0x00000020
140  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB                              0
141  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB                              31
142  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK                             0xffffffff
143  
144  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET                           0x00000024
145  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB                              0
146  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB                              31
147  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK                             0xffffffff
148  
149  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET                           0x00000028
150  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB                              0
151  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB                              31
152  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK                             0xffffffff
153  
154  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET                          0x0000002c
155  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB                             0
156  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB                             31
157  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK                            0xffffffff
158  
159  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET                          0x00000030
160  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB                             0
161  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB                             31
162  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK                            0xffffffff
163  
164  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET                          0x00000034
165  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB                             0
166  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB                             31
167  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK                            0xffffffff
168  
169  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET                          0x00000038
170  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB                             0
171  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB                             31
172  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK                            0xffffffff
173  
174  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET                          0x0000003c
175  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB                             0
176  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB                             31
177  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK                            0xffffffff
178  
179  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET                          0x00000040
180  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB                             0
181  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB                             31
182  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK                            0xffffffff
183  
184  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET                          0x00000044
185  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB                             0
186  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB                             31
187  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK                            0xffffffff
188  
189  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET                          0x00000048
190  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB                             0
191  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB                             31
192  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK                            0xffffffff
193  
194  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET                          0x0000004c
195  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB                             0
196  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB                             31
197  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK                            0xffffffff
198  
199  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET                          0x00000050
200  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB                             0
201  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB                             31
202  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK                            0xffffffff
203  
204  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET                          0x00000054
205  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB                             0
206  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB                             31
207  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK                            0xffffffff
208  
209  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET                          0x00000058
210  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB                             0
211  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB                             31
212  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK                            0xffffffff
213  
214  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET                          0x0000005c
215  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB                             0
216  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB                             31
217  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK                            0xffffffff
218  
219  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET                          0x00000060
220  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB                             0
221  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB                             31
222  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK                            0xffffffff
223  
224  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET                          0x00000064
225  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB                             0
226  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB                             31
227  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK                            0xffffffff
228  
229  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET                          0x00000068
230  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB                             0
231  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB                             27
232  #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK                            0x0fffffff
233  
234  #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET                         0x00000068
235  #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB                            28
236  #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB                            31
237  #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK                           0xf0000000
238  
239  #endif
240