1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _MACTX_USER_DESC_PER_USER_H_ 19 #define _MACTX_USER_DESC_PER_USER_H_ 20 21 #define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 22 23 struct mactx_user_desc_per_user { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t psdu_length : 24, 26 reserved_0a : 8; 27 uint32_t ru_start_index : 8, 28 ru_size : 4, 29 reserved_1b : 4, 30 ofdma_mu_mimo_enabled : 1, 31 nss : 3, 32 stream_offset : 3, 33 reserved_1c : 1, 34 mcs : 4, 35 dcm : 1, 36 reserved_1d : 3; 37 uint32_t fec_type : 1, 38 reserved_2a : 7, 39 user_bf_type : 2, 40 reserved_2b : 6, 41 drop_user_cbf : 1, 42 reserved_2c : 7, 43 ldpc_extra_symbol : 1, 44 force_extra_symbol : 1, 45 reserved_2d : 6; 46 uint32_t sw_peer_id : 16, 47 per_user_subband_mask : 16; 48 #else 49 uint32_t reserved_0a : 8, 50 psdu_length : 24; 51 uint32_t reserved_1d : 3, 52 dcm : 1, 53 mcs : 4, 54 reserved_1c : 1, 55 stream_offset : 3, 56 nss : 3, 57 ofdma_mu_mimo_enabled : 1, 58 reserved_1b : 4, 59 ru_size : 4, 60 ru_start_index : 8; 61 uint32_t reserved_2d : 6, 62 force_extra_symbol : 1, 63 ldpc_extra_symbol : 1, 64 reserved_2c : 7, 65 drop_user_cbf : 1, 66 reserved_2b : 6, 67 user_bf_type : 2, 68 reserved_2a : 7, 69 fec_type : 1; 70 uint32_t per_user_subband_mask : 16, 71 sw_peer_id : 16; 72 #endif 73 }; 74 75 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x00000000 76 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 77 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 78 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x00ffffff 79 80 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x00000000 81 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 82 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 83 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0xff000000 84 85 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x00000004 86 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 0 87 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 7 88 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff 89 90 #define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x00000004 91 #define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 8 92 #define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 11 93 #define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f00 94 95 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x00000004 96 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 12 97 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 15 98 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f000 99 100 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x00000004 101 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 16 102 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 16 103 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x00010000 104 105 #define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x00000004 106 #define MACTX_USER_DESC_PER_USER_NSS_LSB 17 107 #define MACTX_USER_DESC_PER_USER_NSS_MSB 19 108 #define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e0000 109 110 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x00000004 111 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 20 112 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 22 113 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x00700000 114 115 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x00000004 116 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 23 117 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 23 118 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x00800000 119 120 #define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x00000004 121 #define MACTX_USER_DESC_PER_USER_MCS_LSB 24 122 #define MACTX_USER_DESC_PER_USER_MCS_MSB 27 123 #define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f000000 124 125 #define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x00000004 126 #define MACTX_USER_DESC_PER_USER_DCM_LSB 28 127 #define MACTX_USER_DESC_PER_USER_DCM_MSB 28 128 #define MACTX_USER_DESC_PER_USER_DCM_MASK 0x10000000 129 130 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x00000004 131 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 29 132 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 31 133 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe0000000 134 135 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x00000008 136 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 137 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 138 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x00000001 139 140 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x00000008 141 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 142 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 143 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x000000fe 144 145 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x00000008 146 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 147 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 148 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x00000300 149 150 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x00000008 151 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 152 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 153 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000fc00 154 155 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x00000008 156 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 157 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 158 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x00010000 159 160 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x00000008 161 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 162 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 163 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x00fe0000 164 165 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 166 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 167 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 168 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x01000000 169 170 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x00000008 171 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 172 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 173 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x02000000 174 175 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x00000008 176 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 177 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 178 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0xfc000000 179 180 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000c 181 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 0 182 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 15 183 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff 184 185 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000c 186 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 16 187 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 31 188 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff0000 189 190 #endif 191