1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _TX_FES_STATUS_PROT_H_ 21 #define _TX_FES_STATUS_PROT_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "phytx_abort_request_info.h" 26 #define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 27 28 #define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 29 30 struct tx_fes_status_prot { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t success : 1, 33 phytx_pkt_end_info_valid : 1, 34 phytx_abort_request_info_valid : 1, 35 reserved_0 : 20, 36 pkt_type : 4, 37 dot11ax_su_extended : 1, 38 rate_mcs : 4; 39 uint32_t frame_type : 2, 40 frame_subtype : 4, 41 rx_pwr_mgmt : 1, 42 status : 1, 43 duration_field : 16, 44 reserved_1a : 2, 45 agc_cbw : 3, 46 service_cbw : 3; 47 uint32_t start_of_frame_timestamp_15_0 : 16, 48 start_of_frame_timestamp_31_16 : 16; 49 uint32_t end_of_frame_timestamp_15_0 : 16, 50 end_of_frame_timestamp_31_16 : 16; 51 uint32_t tx_group_delay : 12, 52 timing_status : 2, 53 dpdtrain_done : 1, 54 reserved_4 : 1, 55 transmit_delay : 16; 56 uint32_t tpc_dbg_info_cmn_15_0 : 16, 57 tpc_dbg_info_cmn_31_16 : 16; 58 uint32_t tpc_dbg_info_cmn_47_32 : 16, 59 tpc_dbg_info_chn1_15_0 : 16; 60 uint32_t tpc_dbg_info_chn1_31_16 : 16, 61 tpc_dbg_info_chn1_47_32 : 16; 62 uint32_t tpc_dbg_info_chn1_63_48 : 16, 63 tpc_dbg_info_chn1_79_64 : 16; 64 uint32_t tpc_dbg_info_chn2_15_0 : 16, 65 tpc_dbg_info_chn2_31_16 : 16; 66 uint32_t tpc_dbg_info_chn2_47_32 : 16, 67 tpc_dbg_info_chn2_63_48 : 16; 68 uint32_t tpc_dbg_info_chn2_79_64 : 16; 69 struct phytx_abort_request_info phytx_abort_request_info_details; 70 uint32_t phytx_tx_end_sw_info_15_0 : 16, 71 phytx_tx_end_sw_info_31_16 : 16; 72 uint32_t phytx_tx_end_sw_info_47_32 : 16, 73 phytx_tx_end_sw_info_63_48 : 16; 74 #else 75 uint32_t rate_mcs : 4, 76 dot11ax_su_extended : 1, 77 pkt_type : 4, 78 reserved_0 : 20, 79 phytx_abort_request_info_valid : 1, 80 phytx_pkt_end_info_valid : 1, 81 success : 1; 82 uint32_t service_cbw : 3, 83 agc_cbw : 3, 84 reserved_1a : 2, 85 duration_field : 16, 86 status : 1, 87 rx_pwr_mgmt : 1, 88 frame_subtype : 4, 89 frame_type : 2; 90 uint32_t start_of_frame_timestamp_31_16 : 16, 91 start_of_frame_timestamp_15_0 : 16; 92 uint32_t end_of_frame_timestamp_31_16 : 16, 93 end_of_frame_timestamp_15_0 : 16; 94 uint32_t transmit_delay : 16, 95 reserved_4 : 1, 96 dpdtrain_done : 1, 97 timing_status : 2, 98 tx_group_delay : 12; 99 uint32_t tpc_dbg_info_cmn_31_16 : 16, 100 tpc_dbg_info_cmn_15_0 : 16; 101 uint32_t tpc_dbg_info_chn1_15_0 : 16, 102 tpc_dbg_info_cmn_47_32 : 16; 103 uint32_t tpc_dbg_info_chn1_47_32 : 16, 104 tpc_dbg_info_chn1_31_16 : 16; 105 uint32_t tpc_dbg_info_chn1_79_64 : 16, 106 tpc_dbg_info_chn1_63_48 : 16; 107 uint32_t tpc_dbg_info_chn2_31_16 : 16, 108 tpc_dbg_info_chn2_15_0 : 16; 109 uint32_t tpc_dbg_info_chn2_63_48 : 16, 110 tpc_dbg_info_chn2_47_32 : 16; 111 struct phytx_abort_request_info phytx_abort_request_info_details; 112 uint16_t tpc_dbg_info_chn2_79_64 : 16; 113 uint32_t phytx_tx_end_sw_info_31_16 : 16, 114 phytx_tx_end_sw_info_15_0 : 16; 115 uint32_t phytx_tx_end_sw_info_63_48 : 16, 116 phytx_tx_end_sw_info_47_32 : 16; 117 #endif 118 }; 119 120 #define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 121 #define TX_FES_STATUS_PROT_SUCCESS_LSB 0 122 #define TX_FES_STATUS_PROT_SUCCESS_MSB 0 123 #define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 124 125 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 126 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 127 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 128 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 129 130 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 131 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 132 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 133 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 134 135 #define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 136 #define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 137 #define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 138 #define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 139 140 #define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 141 #define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 142 #define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 143 #define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 144 145 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 146 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 147 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 148 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 149 150 #define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 151 #define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 152 #define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 153 #define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 154 155 #define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 156 #define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 157 #define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 158 #define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 159 160 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 161 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 162 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 163 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 164 165 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 166 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 167 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 168 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 169 170 #define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 171 #define TX_FES_STATUS_PROT_STATUS_LSB 39 172 #define TX_FES_STATUS_PROT_STATUS_MSB 39 173 #define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 174 175 #define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 176 #define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 177 #define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 178 #define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 179 180 #define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 181 #define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 182 #define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 183 #define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 184 185 #define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 186 #define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 187 #define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 188 #define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 189 190 #define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 191 #define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 192 #define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 193 #define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 194 195 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 196 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 197 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 198 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 199 200 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 201 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 202 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 203 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 204 205 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 206 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 207 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 208 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 209 210 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 211 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 212 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 213 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 214 215 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 216 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 217 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 218 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff 219 220 #define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 221 #define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 222 #define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 223 #define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 224 225 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 226 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 227 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 228 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 229 230 #define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 231 #define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 232 #define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 233 #define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 234 235 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 236 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 237 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 238 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 239 240 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 241 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 242 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 243 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 244 245 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 246 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 247 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 248 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 249 250 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 251 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 252 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 253 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff 254 255 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 256 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 257 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 258 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 259 260 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 261 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 262 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 263 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 264 265 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 266 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 267 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 268 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 269 270 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 271 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 272 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 273 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff 274 275 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 276 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 277 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 278 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 279 280 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 281 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 282 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 283 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 284 285 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 286 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 287 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 288 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 289 290 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 291 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 292 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 293 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff 294 295 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 296 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 297 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 298 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 299 300 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 301 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 302 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 303 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 304 305 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 306 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 307 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 308 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 309 310 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 311 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 312 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 313 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 314 315 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 316 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 317 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 318 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 319 320 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 321 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 322 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 323 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 324 325 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 326 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 327 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 328 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 329 330 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 331 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 332 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 333 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 334 335 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 336 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 337 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 338 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 339 340 #endif 341