1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _TCL_GSE_CMD_H_ 23 #define _TCL_GSE_CMD_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_TCL_GSE_CMD 8 28 29 struct tcl_gse_cmd { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t control_buffer_addr_31_0 : 32; 32 uint32_t control_buffer_addr_39_32 : 8, 33 gse_ctrl : 4, 34 gse_sel : 1, 35 status_destination_ring_id : 1, 36 swap : 1, 37 index_search_en : 1, 38 cache_set_num : 4, 39 reserved_1a : 12; 40 uint32_t tcl_cmd_type : 1, 41 reserved_2a : 31; 42 uint32_t cmd_meta_data_31_0 : 32; 43 uint32_t cmd_meta_data_63_32 : 32; 44 uint32_t reserved_5a : 32; 45 uint32_t reserved_6a : 32; 46 uint32_t reserved_7a : 20, 47 ring_id : 8, 48 looping_count : 4; 49 #else 50 uint32_t control_buffer_addr_31_0 : 32; 51 uint32_t reserved_1a : 12, 52 cache_set_num : 4, 53 index_search_en : 1, 54 swap : 1, 55 status_destination_ring_id : 1, 56 gse_sel : 1, 57 gse_ctrl : 4, 58 control_buffer_addr_39_32 : 8; 59 uint32_t reserved_2a : 31, 60 tcl_cmd_type : 1; 61 uint32_t cmd_meta_data_31_0 : 32; 62 uint32_t cmd_meta_data_63_32 : 32; 63 uint32_t reserved_5a : 32; 64 uint32_t reserved_6a : 32; 65 uint32_t looping_count : 4, 66 ring_id : 8, 67 reserved_7a : 20; 68 #endif 69 }; 70 71 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 72 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 73 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 74 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 75 76 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 77 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 78 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 79 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 80 81 #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 82 #define TCL_GSE_CMD_GSE_CTRL_LSB 8 83 #define TCL_GSE_CMD_GSE_CTRL_MSB 11 84 #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 85 86 #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 87 #define TCL_GSE_CMD_GSE_SEL_LSB 12 88 #define TCL_GSE_CMD_GSE_SEL_MSB 12 89 #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 90 91 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 92 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 93 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 94 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 95 96 #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 97 #define TCL_GSE_CMD_SWAP_LSB 14 98 #define TCL_GSE_CMD_SWAP_MSB 14 99 #define TCL_GSE_CMD_SWAP_MASK 0x00004000 100 101 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 102 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 103 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 104 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 105 106 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 107 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 108 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 109 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 110 111 #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 112 #define TCL_GSE_CMD_RESERVED_1A_LSB 20 113 #define TCL_GSE_CMD_RESERVED_1A_MSB 31 114 #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 115 116 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 117 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 118 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 119 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 120 121 #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 122 #define TCL_GSE_CMD_RESERVED_2A_LSB 1 123 #define TCL_GSE_CMD_RESERVED_2A_MSB 31 124 #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe 125 126 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c 127 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 128 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 129 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff 130 131 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 132 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 133 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 134 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff 135 136 #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 137 #define TCL_GSE_CMD_RESERVED_5A_LSB 0 138 #define TCL_GSE_CMD_RESERVED_5A_MSB 31 139 #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff 140 141 #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 142 #define TCL_GSE_CMD_RESERVED_6A_LSB 0 143 #define TCL_GSE_CMD_RESERVED_6A_MSB 31 144 #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff 145 146 #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c 147 #define TCL_GSE_CMD_RESERVED_7A_LSB 0 148 #define TCL_GSE_CMD_RESERVED_7A_MSB 19 149 #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff 150 151 #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c 152 #define TCL_GSE_CMD_RING_ID_LSB 20 153 #define TCL_GSE_CMD_RING_ID_MSB 27 154 #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 155 156 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c 157 #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 158 #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 159 #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 160 161 #endif 162