1 
2 /*
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 
21 
22 #ifndef _REO_FLUSH_QUEUE_H_
23 #define _REO_FLUSH_QUEUE_H_
24 #if !defined(__ASSEMBLER__)
25 #endif
26 
27 #include "uniform_reo_cmd_header.h"
28 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
29 
30 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
31 
32 struct reo_flush_queue {
33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
34              struct   uniform_reo_cmd_header                                    cmd_header;
35              uint32_t flush_desc_addr_31_0                                    : 32;
36              uint32_t flush_desc_addr_39_32                                   :  8,
37                       block_desc_addr_usage_after_flush                       :  1,
38                       block_resource_index                                    :  2,
39                       reserved_2a                                             : 21;
40              uint32_t reserved_3a                                             : 32;
41              uint32_t reserved_4a                                             : 32;
42              uint32_t reserved_5a                                             : 32;
43              uint32_t reserved_6a                                             : 32;
44              uint32_t reserved_7a                                             : 32;
45              uint32_t reserved_8a                                             : 32;
46              uint32_t tlv64_padding                                           : 32;
47 #else
48              struct   uniform_reo_cmd_header                                    cmd_header;
49              uint32_t flush_desc_addr_31_0                                    : 32;
50              uint32_t reserved_2a                                             : 21,
51                       block_resource_index                                    :  2,
52                       block_desc_addr_usage_after_flush                       :  1,
53                       flush_desc_addr_39_32                                   :  8;
54              uint32_t reserved_3a                                             : 32;
55              uint32_t reserved_4a                                             : 32;
56              uint32_t reserved_5a                                             : 32;
57              uint32_t reserved_6a                                             : 32;
58              uint32_t reserved_7a                                             : 32;
59              uint32_t reserved_8a                                             : 32;
60              uint32_t tlv64_padding                                           : 32;
61 #endif
62 };
63 
64 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
65 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
66 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
67 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
68 
69 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
70 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
71 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
72 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
73 
74 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
75 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB                                  17
76 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB                                  31
77 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
78 
79 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET                                 0x0000000000000000
80 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB                                    32
81 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB                                    63
82 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK                                   0xffffffff00000000
83 
84 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET                                0x0000000000000008
85 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB                                   0
86 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB                                   7
87 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK                                  0x00000000000000ff
88 
89 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET                    0x0000000000000008
90 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB                       8
91 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB                       8
92 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK                      0x0000000000000100
93 
94 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET                                 0x0000000000000008
95 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB                                    9
96 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB                                    10
97 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK                                   0x0000000000000600
98 
99 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET                                          0x0000000000000008
100 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB                                             11
101 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB                                             31
102 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK                                            0x00000000fffff800
103 
104 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET                                          0x0000000000000008
105 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB                                             32
106 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB                                             63
107 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK                                            0xffffffff00000000
108 
109 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET                                          0x0000000000000010
110 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB                                             0
111 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB                                             31
112 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK                                            0x00000000ffffffff
113 
114 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET                                          0x0000000000000010
115 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB                                             32
116 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB                                             63
117 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK                                            0xffffffff00000000
118 
119 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET                                          0x0000000000000018
120 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB                                             0
121 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB                                             31
122 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK                                            0x00000000ffffffff
123 
124 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET                                          0x0000000000000018
125 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB                                             32
126 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB                                             63
127 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK                                            0xffffffff00000000
128 
129 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET                                          0x0000000000000020
130 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB                                             0
131 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB                                             31
132 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK                                            0x00000000ffffffff
133 
134 #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET                                        0x0000000000000020
135 #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB                                           32
136 #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB                                           63
137 #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK                                          0xffffffff00000000
138 
139 #endif
140