1 
2 /*
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 
21 
22 #ifndef _RECEIVE_USER_INFO_H_
23 #define _RECEIVE_USER_INFO_H_
24 #if !defined(__ASSEMBLER__)
25 #endif
26 
27 #define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
28 
29 struct receive_user_info {
30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
31              uint32_t phy_ppdu_id                                             : 16,
32                       user_rssi                                               :  8,
33                       pkt_type                                                :  4,
34                       stbc                                                    :  1,
35                       reception_type                                          :  3;
36              uint32_t rate_mcs                                                :  4,
37                       sgi                                                     :  2,
38                       __reserved_g_0004                                          :  1,
39                       reserved_1a                                             :  1,
40                       mimo_ss_bitmap                                          :  8,
41                       receive_bandwidth                                       :  3,
42                       reserved_1b                                             :  5,
43                       dl_ofdma_user_index                                     :  8;
44              uint32_t dl_ofdma_content_channel                                :  1,
45                       reserved_2a                                             :  7,
46                       nss                                                     :  3,
47                       stream_offset                                           :  3,
48                       sta_dcm                                                 :  1,
49                       ldpc                                                    :  1,
50                       ru_type_80_0                                            :  4,
51                       ru_type_80_1                                            :  4,
52                       ru_type_80_2                                            :  4,
53                       ru_type_80_3                                            :  4;
54              uint32_t ru_start_index_80_0                                     :  6,
55                       reserved_3a                                             :  2,
56                       ru_start_index_80_1                                     :  6,
57                       reserved_3b                                             :  2,
58                       ru_start_index_80_2                                     :  6,
59                       reserved_3c                                             :  2,
60                       ru_start_index_80_3                                     :  6,
61                       reserved_3d                                             :  2;
62              uint32_t user_fd_rssi_seg0                                       : 32;
63              uint32_t user_fd_rssi_seg1                                       : 32;
64              uint32_t user_fd_rssi_seg2                                       : 32;
65              uint32_t user_fd_rssi_seg3                                       : 32;
66 #else
67              uint32_t reception_type                                          :  3,
68                       stbc                                                    :  1,
69                       pkt_type                                                :  4,
70                       user_rssi                                               :  8,
71                       phy_ppdu_id                                             : 16;
72              uint32_t dl_ofdma_user_index                                     :  8,
73                       reserved_1b                                             :  5,
74                       receive_bandwidth                                       :  3,
75                       mimo_ss_bitmap                                          :  8,
76                       reserved_1a                                             :  1,
77                       __reserved_g_0004                                          :  1,
78                       sgi                                                     :  2,
79                       rate_mcs                                                :  4;
80              uint32_t ru_type_80_3                                            :  4,
81                       ru_type_80_2                                            :  4,
82                       ru_type_80_1                                            :  4,
83                       ru_type_80_0                                            :  4,
84                       ldpc                                                    :  1,
85                       sta_dcm                                                 :  1,
86                       stream_offset                                           :  3,
87                       nss                                                     :  3,
88                       reserved_2a                                             :  7,
89                       dl_ofdma_content_channel                                :  1;
90              uint32_t reserved_3d                                             :  2,
91                       ru_start_index_80_3                                     :  6,
92                       reserved_3c                                             :  2,
93                       ru_start_index_80_2                                     :  6,
94                       reserved_3b                                             :  2,
95                       ru_start_index_80_1                                     :  6,
96                       reserved_3a                                             :  2,
97                       ru_start_index_80_0                                     :  6;
98              uint32_t user_fd_rssi_seg0                                       : 32;
99              uint32_t user_fd_rssi_seg1                                       : 32;
100              uint32_t user_fd_rssi_seg2                                       : 32;
101              uint32_t user_fd_rssi_seg3                                       : 32;
102 #endif
103 };
104 
105 #define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
106 #define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
107 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
108 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
109 
110 #define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
111 #define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
112 #define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
113 #define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
114 
115 #define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
116 #define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
117 #define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
118 #define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
119 
120 #define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
121 #define RECEIVE_USER_INFO_STBC_LSB                                                  28
122 #define RECEIVE_USER_INFO_STBC_MSB                                                  28
123 #define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
124 
125 #define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
126 #define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
127 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
128 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
129 
130 #define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
131 #define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
132 #define RECEIVE_USER_INFO_RATE_MCS_MSB                                              3
133 #define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000000f
134 
135 #define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
136 #define RECEIVE_USER_INFO_SGI_LSB                                                   4
137 #define RECEIVE_USER_INFO_SGI_MSB                                                   5
138 #define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000030
139 
140 #define RECEIVE_USER_INFO_RESERVED_1A_OFFSET                                        0x00000004
141 #define RECEIVE_USER_INFO_RESERVED_1A_LSB                                           7
142 #define RECEIVE_USER_INFO_RESERVED_1A_MSB                                           7
143 #define RECEIVE_USER_INFO_RESERVED_1A_MASK                                          0x00000080
144 
145 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
146 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
147 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
148 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
149 
150 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
151 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
152 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
153 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
154 
155 #define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
156 #define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
157 #define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
158 #define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
159 
160 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
161 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
162 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
163 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
164 
165 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
166 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
167 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
168 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
169 
170 #define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
171 #define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
172 #define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           7
173 #define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x000000fe
174 
175 #define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
176 #define RECEIVE_USER_INFO_NSS_LSB                                                   8
177 #define RECEIVE_USER_INFO_NSS_MSB                                                   10
178 #define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
179 
180 #define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
181 #define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
182 #define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
183 #define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
184 
185 #define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
186 #define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
187 #define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
188 #define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
189 
190 #define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
191 #define RECEIVE_USER_INFO_LDPC_LSB                                                  15
192 #define RECEIVE_USER_INFO_LDPC_MSB                                                  15
193 #define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
194 
195 #define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
196 #define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
197 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
198 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
199 
200 #define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
201 #define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
202 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
203 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
204 
205 #define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
206 #define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
207 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
208 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
209 
210 #define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
211 #define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
212 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
213 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
214 
215 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
216 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
217 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
218 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
219 
220 #define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
221 #define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
222 #define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
223 #define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
224 
225 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
226 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
227 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
228 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
229 
230 #define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
231 #define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
232 #define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
233 #define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
234 
235 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
236 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
237 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
238 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
239 
240 #define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
241 #define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
242 #define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
243 #define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
244 
245 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
246 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
247 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
248 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
249 
250 #define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
251 #define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           30
252 #define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
253 #define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0xc0000000
254 
255 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
256 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
257 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
258 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
259 
260 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
261 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
262 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
263 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
264 
265 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
266 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
267 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
268 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
269 
270 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
271 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
272 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
273 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
274 
275 #endif
276