1 
2 /*
3  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 
19 
20 #ifndef _PDG_RESPONSE_RATE_SETTING_H_
21 #define _PDG_RESPONSE_RATE_SETTING_H_
22 #if !defined(__ASSEMBLER__)
23 #endif
24 
25 #include "mlo_sta_id_details.h"
26 #define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
27 
28 struct pdg_response_rate_setting {
29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
30              uint32_t reserved_0a                                             :  1,
31                       tx_antenna_sector_ctrl                                  : 24,
32                       pkt_type                                                :  4,
33                       smoothing                                               :  1,
34                       ldpc                                                    :  1,
35                       stbc                                                    :  1;
36              uint32_t alt_tx_pwr                                              :  8,
37                       alt_min_tx_pwr                                          :  8,
38                       alt_nss                                                 :  3,
39                       alt_tx_chain_mask                                       :  8,
40                       alt_bw                                                  :  3,
41                       stf_ltf_3db_boost                                       :  1,
42                       force_extra_symbol                                      :  1;
43              uint32_t alt_rate_mcs                                            :  4,
44                       nss                                                     :  3,
45                       dpd_enable                                              :  1,
46                       tx_pwr                                                  :  8,
47                       min_tx_pwr                                              :  8,
48                       tx_chain_mask                                           :  8;
49              uint32_t reserved_3a                                             :  8,
50                       sgi                                                     :  2,
51                       rate_mcs                                                :  4,
52                       reserved_3b                                             :  2,
53                       tx_pwr_1                                                :  8,
54                       alt_tx_pwr_1                                            :  8;
55              uint32_t aggregation                                             :  1,
56                       dot11ax_bss_color_id                                    :  6,
57                       dot11ax_spatial_reuse                                   :  4,
58                       dot11ax_cp_ltf_size                                     :  2,
59                       dot11ax_dcm                                             :  1,
60                       dot11ax_doppler_indication                              :  1,
61                       dot11ax_su_extended                                     :  1,
62                       dot11ax_min_packet_extension                            :  2,
63                       dot11ax_pe_nss                                          :  3,
64                       dot11ax_pe_content                                      :  1,
65                       dot11ax_pe_ltf_size                                     :  2,
66                       dot11ax_chain_csd_en                                    :  1,
67                       dot11ax_pe_chain_csd_en                                 :  1,
68                       dot11ax_dl_ul_flag                                      :  1,
69                       reserved_4a                                             :  5;
70              uint32_t dot11ax_ext_ru_start_index                              :  4,
71                       dot11ax_ext_ru_size                                     :  4,
72                       eht_duplicate_mode                                      :  2,
73                       he_sigb_dcm                                             :  1,
74                       he_sigb_0_mcs                                           :  3,
75                       num_he_sigb_sym                                         :  5,
76                       required_response_time_source                           :  1,
77                       reserved_5a                                             :  6,
78                       u_sig_puncture_pattern_encoding                         :  6;
79              struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
80              uint16_t required_response_time                                  : 12,
81                       dot11be_params_placeholder                              :  4;
82 #else
83              uint32_t stbc                                                    :  1,
84                       ldpc                                                    :  1,
85                       smoothing                                               :  1,
86                       pkt_type                                                :  4,
87                       tx_antenna_sector_ctrl                                  : 24,
88                       reserved_0a                                             :  1;
89              uint32_t force_extra_symbol                                      :  1,
90                       stf_ltf_3db_boost                                       :  1,
91                       alt_bw                                                  :  3,
92                       alt_tx_chain_mask                                       :  8,
93                       alt_nss                                                 :  3,
94                       alt_min_tx_pwr                                          :  8,
95                       alt_tx_pwr                                              :  8;
96              uint32_t tx_chain_mask                                           :  8,
97                       min_tx_pwr                                              :  8,
98                       tx_pwr                                                  :  8,
99                       dpd_enable                                              :  1,
100                       nss                                                     :  3,
101                       alt_rate_mcs                                            :  4;
102              uint32_t alt_tx_pwr_1                                            :  8,
103                       tx_pwr_1                                                :  8,
104                       reserved_3b                                             :  2,
105                       rate_mcs                                                :  4,
106                       sgi                                                     :  2,
107                       reserved_3a                                             :  8;
108              uint32_t reserved_4a                                             :  5,
109                       dot11ax_dl_ul_flag                                      :  1,
110                       dot11ax_pe_chain_csd_en                                 :  1,
111                       dot11ax_chain_csd_en                                    :  1,
112                       dot11ax_pe_ltf_size                                     :  2,
113                       dot11ax_pe_content                                      :  1,
114                       dot11ax_pe_nss                                          :  3,
115                       dot11ax_min_packet_extension                            :  2,
116                       dot11ax_su_extended                                     :  1,
117                       dot11ax_doppler_indication                              :  1,
118                       dot11ax_dcm                                             :  1,
119                       dot11ax_cp_ltf_size                                     :  2,
120                       dot11ax_spatial_reuse                                   :  4,
121                       dot11ax_bss_color_id                                    :  6,
122                       aggregation                                             :  1;
123              uint32_t u_sig_puncture_pattern_encoding                         :  6,
124                       reserved_5a                                             :  6,
125                       required_response_time_source                           :  1,
126                       num_he_sigb_sym                                         :  5,
127                       he_sigb_0_mcs                                           :  3,
128                       he_sigb_dcm                                             :  1,
129                       eht_duplicate_mode                                      :  2,
130                       dot11ax_ext_ru_size                                     :  4,
131                       dot11ax_ext_ru_start_index                              :  4;
132              uint32_t dot11be_params_placeholder                              :  4,
133                       required_response_time                                  : 12;
134              struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
135 #endif
136 };
137 
138 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET                                0x00000000
139 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB                                   0
140 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB                                   0
141 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK                                  0x00000001
142 
143 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET                     0x00000000
144 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB                        1
145 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB                        24
146 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK                       0x01fffffe
147 
148 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET                                   0x00000000
149 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB                                      25
150 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB                                      28
151 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK                                     0x1e000000
152 
153 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET                                  0x00000000
154 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB                                     29
155 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB                                     29
156 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK                                    0x20000000
157 
158 #define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET                                       0x00000000
159 #define PDG_RESPONSE_RATE_SETTING_LDPC_LSB                                          30
160 #define PDG_RESPONSE_RATE_SETTING_LDPC_MSB                                          30
161 #define PDG_RESPONSE_RATE_SETTING_LDPC_MASK                                         0x40000000
162 
163 #define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET                                       0x00000000
164 #define PDG_RESPONSE_RATE_SETTING_STBC_LSB                                          31
165 #define PDG_RESPONSE_RATE_SETTING_STBC_MSB                                          31
166 #define PDG_RESPONSE_RATE_SETTING_STBC_MASK                                         0x80000000
167 
168 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET                                 0x00000004
169 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB                                    0
170 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB                                    7
171 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK                                   0x000000ff
172 
173 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET                             0x00000004
174 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB                                8
175 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB                                15
176 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK                               0x0000ff00
177 
178 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET                                    0x00000004
179 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB                                       16
180 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB                                       18
181 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK                                      0x00070000
182 
183 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET                          0x00000004
184 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB                             19
185 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB                             26
186 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK                            0x07f80000
187 
188 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET                                     0x00000004
189 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB                                        27
190 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB                                        29
191 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK                                       0x38000000
192 
193 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET                          0x00000004
194 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB                             30
195 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB                             30
196 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK                            0x40000000
197 
198 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000004
199 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB                            31
200 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB                            31
201 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK                           0x80000000
202 
203 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET                               0x00000008
204 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB                                  0
205 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB                                  3
206 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK                                 0x0000000f
207 
208 #define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET                                        0x00000008
209 #define PDG_RESPONSE_RATE_SETTING_NSS_LSB                                           4
210 #define PDG_RESPONSE_RATE_SETTING_NSS_MSB                                           6
211 #define PDG_RESPONSE_RATE_SETTING_NSS_MASK                                          0x00000070
212 
213 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET                                 0x00000008
214 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB                                    7
215 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB                                    7
216 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK                                   0x00000080
217 
218 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET                                     0x00000008
219 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB                                        8
220 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB                                        15
221 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK                                       0x0000ff00
222 
223 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET                                 0x00000008
224 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB                                    16
225 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB                                    23
226 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK                                   0x00ff0000
227 
228 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET                              0x00000008
229 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB                                 24
230 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB                                 31
231 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK                                0xff000000
232 
233 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET                                0x0000000c
234 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB                                   0
235 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB                                   7
236 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK                                  0x000000ff
237 
238 #define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET                                        0x0000000c
239 #define PDG_RESPONSE_RATE_SETTING_SGI_LSB                                           8
240 #define PDG_RESPONSE_RATE_SETTING_SGI_MSB                                           9
241 #define PDG_RESPONSE_RATE_SETTING_SGI_MASK                                          0x00000300
242 
243 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET                                   0x0000000c
244 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB                                      10
245 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB                                      13
246 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK                                     0x00003c00
247 
248 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET                                0x0000000c
249 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB                                   14
250 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB                                   15
251 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK                                  0x0000c000
252 
253 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET                                   0x0000000c
254 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB                                      16
255 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB                                      23
256 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK                                     0x00ff0000
257 
258 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET                               0x0000000c
259 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB                                  24
260 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB                                  31
261 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK                                 0xff000000
262 
263 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET                                0x00000010
264 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB                                   0
265 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB                                   0
266 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK                                  0x00000001
267 
268 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET                       0x00000010
269 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB                          1
270 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB                          6
271 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK                         0x0000007e
272 
273 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET                      0x00000010
274 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB                         7
275 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB                         10
276 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK                        0x00000780
277 
278 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET                        0x00000010
279 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB                           11
280 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB                           12
281 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK                          0x00001800
282 
283 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET                                0x00000010
284 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB                                   13
285 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB                                   13
286 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK                                  0x00002000
287 
288 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET                 0x00000010
289 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB                    14
290 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB                    14
291 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK                   0x00004000
292 
293 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET                        0x00000010
294 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB                           15
295 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB                           15
296 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK                          0x00008000
297 
298 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET               0x00000010
299 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB                  16
300 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB                  17
301 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK                 0x00030000
302 
303 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET                             0x00000010
304 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB                                18
305 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB                                20
306 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK                               0x001c0000
307 
308 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET                         0x00000010
309 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB                            21
310 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB                            21
311 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK                           0x00200000
312 
313 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET                        0x00000010
314 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB                           22
315 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB                           23
316 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK                          0x00c00000
317 
318 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET                       0x00000010
319 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB                          24
320 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB                          24
321 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK                         0x01000000
322 
323 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET                    0x00000010
324 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB                       25
325 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB                       25
326 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK                      0x02000000
327 
328 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000010
329 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB                            26
330 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB                            26
331 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK                           0x04000000
332 
333 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET                                0x00000010
334 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB                                   27
335 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB                                   31
336 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK                                  0xf8000000
337 
338 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET                 0x00000014
339 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB                    0
340 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB                    3
341 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK                   0x0000000f
342 
343 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET                        0x00000014
344 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB                           4
345 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB                           7
346 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK                          0x000000f0
347 
348 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET                         0x00000014
349 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB                            8
350 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB                            9
351 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK                           0x00000300
352 
353 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET                                0x00000014
354 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB                                   10
355 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB                                   10
356 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK                                  0x00000400
357 
358 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET                              0x00000014
359 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB                                 11
360 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB                                 13
361 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK                                0x00003800
362 
363 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET                            0x00000014
364 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB                               14
365 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB                               18
366 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK                              0x0007c000
367 
368 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET              0x00000014
369 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB                 19
370 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB                 19
371 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK                0x00080000
372 
373 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET                                0x00000014
374 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB                                   20
375 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB                                   25
376 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK                                  0x03f00000
377 
378 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000014
379 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
380 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
381 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
382 
383 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000018
384 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
385 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
386 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
387 
388 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000018
389 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
390 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
391 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
392 
393 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
394 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
395 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
396 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
397 
398 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
399 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
400 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
401 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
402 
403 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000018
404 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
405 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
406 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
407 
408 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET                     0x00000018
409 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB                        16
410 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB                        27
411 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK                       0x0fff0000
412 
413 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET                 0x00000018
414 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB                    28
415 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB                    31
416 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK                   0xf0000000
417 
418 #endif
419