1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ 31 #define _RXPCU_PPDU_END_LAYOUT_INFO_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 36 37 38 struct rxpcu_ppdu_end_layout_info { 39 uint32_t rssi_legacy_offset : 2, 40 l_sig_a_offset : 6, 41 l_sig_b_offset : 6, 42 ht_sig_offset : 6, 43 vht_sig_a_offset : 6, 44 repeat_l_sig_a_offset : 6; 45 uint32_t he_sig_a_su_offset : 6, 46 he_sig_a_mu_dl_offset : 6, 47 he_sig_a_mu_ul_offset : 6, 48 generic_u_sig_offset : 6, 49 rssi_ht_offset : 7, 50 reserved_1a : 1; 51 uint32_t vht_sig_b_su20_offset : 7, 52 vht_sig_b_su40_offset : 7, 53 vht_sig_b_su80_offset : 7, 54 vht_sig_b_su160_offset : 7, 55 reserved_2a : 4; 56 uint32_t vht_sig_b_mu20_offset : 7, 57 vht_sig_b_mu40_offset : 7, 58 vht_sig_b_mu80_offset : 7, 59 vht_sig_b_mu160_offset : 7, 60 reserved_3a : 4; 61 uint32_t he_sig_b1_mu_offset : 7, 62 he_sig_b2_mu_offset : 7, 63 he_sig_b2_ofdma_offset : 7, 64 first_generic_eht_sig_offset : 7, 65 multiple_generic_eht_sig_included : 1, 66 reserved_4a : 3; 67 uint32_t common_user_info_offset : 7, 68 first_debug_info_offset : 8, 69 multiple_debug_info_included : 1, 70 first_other_receive_info_offset : 8, 71 multiple_other_receive_info_included : 1, 72 reserved_5a : 7; 73 uint32_t data_done_offset : 8, 74 generated_cbf_details_offset : 8, 75 pkt_end_part1_offset : 8, 76 location_offset : 8; 77 uint32_t az_integrity_data_offset : 8, 78 pkt_end_offset : 8, 79 abort_request_ack_offset : 8, 80 reserved_7a : 8; 81 uint32_t reserved_8a : 32; 82 uint32_t reserved_9a : 32; 83 }; 84 85 86 87 88 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 89 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 90 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 91 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 92 93 94 95 96 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 97 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 98 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 99 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc 100 101 102 103 104 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 105 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 106 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 107 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 108 109 110 111 112 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 113 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 114 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 115 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 116 117 118 119 120 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 121 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 122 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 123 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 124 125 126 127 128 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 129 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 130 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 131 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 132 133 134 135 136 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 137 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 138 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 139 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f 140 141 142 143 144 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 145 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 146 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 147 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 148 149 150 151 152 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 153 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 154 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 155 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 156 157 158 159 160 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 161 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 162 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 163 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 164 165 166 167 168 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 169 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 170 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 171 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 172 173 174 175 176 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 177 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 178 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 179 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 180 181 182 183 184 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 185 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 186 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 187 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f 188 189 190 191 192 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 193 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 194 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 195 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 196 197 198 199 200 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 201 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 202 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 203 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 204 205 206 207 208 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 209 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 210 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 211 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 212 213 214 215 216 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 217 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 218 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 219 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 220 221 222 223 224 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c 225 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 226 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 227 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f 228 229 230 231 232 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c 233 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 234 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 235 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 236 237 238 239 240 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c 241 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 242 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 243 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 244 245 246 247 248 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c 249 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 250 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 251 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 252 253 254 255 256 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c 257 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 258 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 259 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 260 261 262 263 264 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 265 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 266 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 267 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f 268 269 270 271 272 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 273 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 274 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 275 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 276 277 278 279 280 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 281 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 282 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 283 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 284 285 286 287 288 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 289 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 290 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 291 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 292 293 294 295 296 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 297 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 298 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 299 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 300 301 302 303 304 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 305 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 306 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 307 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 308 309 310 311 312 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 313 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 314 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 315 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f 316 317 318 319 320 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 321 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 322 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 323 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 324 325 326 327 328 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 329 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 330 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 331 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 332 333 334 335 336 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 337 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 338 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 339 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 340 341 342 343 344 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 345 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 346 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 347 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 348 349 350 351 352 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 353 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 354 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 355 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 356 357 358 359 360 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 361 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 362 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 363 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff 364 365 366 367 368 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 369 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 370 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 371 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 372 373 374 375 376 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 377 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 378 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 379 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 380 381 382 383 384 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 385 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 386 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 387 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 388 389 390 391 392 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c 393 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0 394 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7 395 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff 396 397 398 399 400 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c 401 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 402 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 403 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 404 405 406 407 408 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c 409 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 410 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 411 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 412 413 414 415 416 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c 417 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 418 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 419 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 420 421 422 423 424 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 425 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 426 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 427 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff 428 429 430 431 432 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 433 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 434 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 435 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff 436 437 438 439 #endif 440