1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_REO_QUEUE_H_ 31 #define _RX_REO_QUEUE_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "uniform_descriptor_header.h" 36 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 37 38 39 struct rx_reo_queue { 40 struct uniform_descriptor_header descriptor_header; 41 uint32_t receive_queue_number : 16, 42 reserved_1b : 16; 43 uint32_t vld : 1, 44 associated_link_descriptor_counter : 2, 45 disable_duplicate_detection : 1, 46 soft_reorder_enable : 1, 47 ac : 2, 48 bar : 1, 49 rty : 1, 50 chk_2k_mode : 1, 51 oor_mode : 1, 52 ba_window_size : 10, 53 pn_check_needed : 1, 54 pn_shall_be_even : 1, 55 pn_shall_be_uneven : 1, 56 pn_handling_enable : 1, 57 pn_size : 2, 58 ignore_ampdu_flag : 1, 59 reserved_2b : 4; 60 uint32_t svld : 1, 61 ssn : 12, 62 current_index : 10, 63 seq_2k_error_detected_flag : 1, 64 pn_error_detected_flag : 1, 65 reserved_3a : 6, 66 pn_valid : 1; 67 uint32_t pn_31_0 : 32; 68 uint32_t pn_63_32 : 32; 69 uint32_t pn_95_64 : 32; 70 uint32_t pn_127_96 : 32; 71 uint32_t last_rx_enqueue_timestamp : 32; 72 uint32_t last_rx_dequeue_timestamp : 32; 73 uint32_t ptr_to_next_aging_queue_31_0 : 32; 74 uint32_t ptr_to_next_aging_queue_39_32 : 8, 75 reserved_11a : 24; 76 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 77 uint32_t ptr_to_previous_aging_queue_39_32 : 8, 78 reserved_13a : 24; 79 uint32_t rx_bitmap_31_0 : 32; 80 uint32_t rx_bitmap_63_32 : 32; 81 uint32_t rx_bitmap_95_64 : 32; 82 uint32_t rx_bitmap_127_96 : 32; 83 uint32_t rx_bitmap_159_128 : 32; 84 uint32_t rx_bitmap_191_160 : 32; 85 uint32_t rx_bitmap_223_192 : 32; 86 uint32_t rx_bitmap_255_224 : 32; 87 uint32_t rx_bitmap_287_256 : 32; 88 uint32_t current_mpdu_count : 7, 89 current_msdu_count : 25; 90 uint32_t last_sn_reg_index : 4, 91 timeout_count : 6, 92 forward_due_to_bar_count : 6, 93 duplicate_count : 16; 94 uint32_t frames_in_order_count : 24, 95 bar_received_count : 8; 96 uint32_t mpdu_frames_processed_count : 32; 97 uint32_t msdu_frames_processed_count : 32; 98 uint32_t total_processed_byte_count : 32; 99 uint32_t late_receive_mpdu_count : 12, 100 window_jump_2k : 4, 101 hole_count : 16; 102 uint32_t reserved_30 : 32; 103 uint32_t reserved_31 : 32; 104 }; 105 106 107 108 109 110 111 112 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 113 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 114 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 115 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 116 117 118 119 120 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 121 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 122 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 123 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 124 125 126 127 128 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 129 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 130 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 131 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 132 133 134 135 136 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 137 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 138 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 139 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 140 141 142 143 144 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 145 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 146 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 147 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 148 149 150 151 152 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 153 #define RX_REO_QUEUE_VLD_LSB 0 154 #define RX_REO_QUEUE_VLD_MSB 0 155 #define RX_REO_QUEUE_VLD_MASK 0x00000001 156 157 158 159 160 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 161 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 162 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 163 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 164 165 166 167 168 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 169 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 170 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 171 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 172 173 174 175 176 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 177 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 178 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 179 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 180 181 182 183 184 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 185 #define RX_REO_QUEUE_AC_LSB 5 186 #define RX_REO_QUEUE_AC_MSB 6 187 #define RX_REO_QUEUE_AC_MASK 0x00000060 188 189 190 191 192 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 193 #define RX_REO_QUEUE_BAR_LSB 7 194 #define RX_REO_QUEUE_BAR_MSB 7 195 #define RX_REO_QUEUE_BAR_MASK 0x00000080 196 197 198 199 200 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 201 #define RX_REO_QUEUE_RTY_LSB 8 202 #define RX_REO_QUEUE_RTY_MSB 8 203 #define RX_REO_QUEUE_RTY_MASK 0x00000100 204 205 206 207 208 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 209 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 210 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 211 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 212 213 214 215 216 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 217 #define RX_REO_QUEUE_OOR_MODE_LSB 10 218 #define RX_REO_QUEUE_OOR_MODE_MSB 10 219 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 220 221 222 223 224 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 225 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 226 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 227 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 228 229 230 231 232 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 233 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 234 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 235 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 236 237 238 239 240 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 241 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 242 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 243 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 244 245 246 247 248 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 249 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 250 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 251 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 252 253 254 255 256 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 257 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 258 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 259 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 260 261 262 263 264 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 265 #define RX_REO_QUEUE_PN_SIZE_LSB 25 266 #define RX_REO_QUEUE_PN_SIZE_MSB 26 267 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 268 269 270 271 272 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 273 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 274 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 275 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 276 277 278 279 280 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 281 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 282 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 283 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 284 285 286 287 288 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 289 #define RX_REO_QUEUE_SVLD_LSB 0 290 #define RX_REO_QUEUE_SVLD_MSB 0 291 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 292 293 294 295 296 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 297 #define RX_REO_QUEUE_SSN_LSB 1 298 #define RX_REO_QUEUE_SSN_MSB 12 299 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 300 301 302 303 304 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 305 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 306 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 307 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 308 309 310 311 312 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 313 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 314 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 315 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 316 317 318 319 320 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 321 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 322 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 323 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 324 325 326 327 328 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 329 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 330 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 331 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 332 333 334 335 336 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 337 #define RX_REO_QUEUE_PN_VALID_LSB 31 338 #define RX_REO_QUEUE_PN_VALID_MSB 31 339 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 340 341 342 343 344 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 345 #define RX_REO_QUEUE_PN_31_0_LSB 0 346 #define RX_REO_QUEUE_PN_31_0_MSB 31 347 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 348 349 350 351 352 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 353 #define RX_REO_QUEUE_PN_63_32_LSB 0 354 #define RX_REO_QUEUE_PN_63_32_MSB 31 355 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 356 357 358 359 360 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 361 #define RX_REO_QUEUE_PN_95_64_LSB 0 362 #define RX_REO_QUEUE_PN_95_64_MSB 31 363 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 364 365 366 367 368 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 369 #define RX_REO_QUEUE_PN_127_96_LSB 0 370 #define RX_REO_QUEUE_PN_127_96_MSB 31 371 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 372 373 374 375 376 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 377 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 378 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 379 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 380 381 382 383 384 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 385 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 386 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 387 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 388 389 390 391 392 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 393 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 394 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 395 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 396 397 398 399 400 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 401 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 402 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 403 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 404 405 406 407 408 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 409 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 410 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 411 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 412 413 414 415 416 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 417 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 418 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 419 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 420 421 422 423 424 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 425 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 426 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 427 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 428 429 430 431 432 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 433 #define RX_REO_QUEUE_RESERVED_13A_LSB 8 434 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 435 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffff00 436 437 438 439 440 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 441 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 442 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 443 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 444 445 446 447 448 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 449 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 450 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 451 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 452 453 454 455 456 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 457 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 458 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 459 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 460 461 462 463 464 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 465 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 466 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 467 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 468 469 470 471 472 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 473 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 474 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 475 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 476 477 478 479 480 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 481 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 482 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 483 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 484 485 486 487 488 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 489 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 490 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 491 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 492 493 494 495 496 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 497 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 498 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 499 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 500 501 502 503 504 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 505 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 506 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 507 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 508 509 510 511 512 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 513 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 514 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 515 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 516 517 518 519 520 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 521 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 522 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 523 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 524 525 526 527 528 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 529 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 530 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 531 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 532 533 534 535 536 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 537 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 538 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 539 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 540 541 542 543 544 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 545 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 546 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 547 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 548 549 550 551 552 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 553 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 554 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 555 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 556 557 558 559 560 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 561 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 562 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 563 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 564 565 566 567 568 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 569 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 570 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 571 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 572 573 574 575 576 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 577 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 578 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 579 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 580 581 582 583 584 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 585 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 586 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 587 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 588 589 590 591 592 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 593 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 594 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 595 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 596 597 598 599 600 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 601 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 602 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 603 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 604 605 606 607 608 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 609 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 610 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 611 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 612 613 614 615 616 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 617 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 618 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 619 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 620 621 622 623 624 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 625 #define RX_REO_QUEUE_RESERVED_30_LSB 0 626 #define RX_REO_QUEUE_RESERVED_30_MSB 31 627 #define RX_REO_QUEUE_RESERVED_30_MASK 0xffffffff 628 629 630 631 632 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 633 #define RX_REO_QUEUE_RESERVED_31_LSB 0 634 #define RX_REO_QUEUE_RESERVED_31_MSB 31 635 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 636 637 638 639 #endif 640