1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 31 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "uniform_reo_status_header.h" 36 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 37 38 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 39 40 41 struct reo_flush_timeout_list_status { 42 struct uniform_reo_status_header status_header; 43 uint32_t error_detected : 1, 44 timout_list_empty : 1, 45 reserved_2a : 30; 46 uint32_t release_desc_count : 16, 47 forward_buf_count : 16; 48 uint32_t reserved_4a : 32; 49 uint32_t reserved_5a : 32; 50 uint32_t reserved_6a : 32; 51 uint32_t reserved_7a : 32; 52 uint32_t reserved_8a : 32; 53 uint32_t reserved_9a : 32; 54 uint32_t reserved_10a : 32; 55 uint32_t reserved_11a : 32; 56 uint32_t reserved_12a : 32; 57 uint32_t reserved_13a : 32; 58 uint32_t reserved_14a : 32; 59 uint32_t reserved_15a : 32; 60 uint32_t reserved_16a : 32; 61 uint32_t reserved_17a : 32; 62 uint32_t reserved_18a : 32; 63 uint32_t reserved_19a : 32; 64 uint32_t reserved_20a : 32; 65 uint32_t reserved_21a : 32; 66 uint32_t reserved_22a : 32; 67 uint32_t reserved_23a : 32; 68 uint32_t reserved_24a : 32; 69 uint32_t reserved_25a : 28, 70 looping_count : 4; 71 }; 72 73 74 75 76 77 78 79 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 80 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 81 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 82 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 83 84 85 86 87 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 88 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 89 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 90 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 91 92 93 94 95 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 96 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 97 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 98 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 99 100 101 102 103 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 104 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 105 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 106 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 107 108 109 110 111 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 112 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 113 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 114 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 115 116 117 118 119 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 120 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 121 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 122 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 123 124 125 126 127 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 128 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 129 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 130 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 131 132 133 134 135 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 136 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 137 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 138 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 139 140 141 142 143 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 144 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 145 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 146 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 147 148 149 150 151 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 152 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 153 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 154 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 155 156 157 158 159 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 160 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 161 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 162 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 163 164 165 166 167 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 168 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 169 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 170 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 171 172 173 174 175 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 176 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 177 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 178 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 179 180 181 182 183 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 184 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 185 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 186 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 187 188 189 190 191 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 192 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 193 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 194 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 195 196 197 198 199 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 200 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 201 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 202 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 203 204 205 206 207 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 208 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 209 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 210 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 211 212 213 214 215 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 216 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 217 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 218 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 219 220 221 222 223 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 224 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 225 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 226 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 227 228 229 230 231 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 232 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 233 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 234 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 235 236 237 238 239 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 240 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 241 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 242 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 243 244 245 246 247 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 248 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 249 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 250 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 251 252 253 254 255 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 256 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 257 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 258 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 259 260 261 262 263 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 264 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 265 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 266 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 267 268 269 270 271 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 272 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 273 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 274 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 275 276 277 278 279 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 280 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 281 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 282 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 283 284 285 286 287 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 288 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 289 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 290 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 291 292 293 294 295 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 296 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 297 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 298 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 299 300 301 302 303 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 304 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 305 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 306 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 307 308 309 310 311 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 312 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 313 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 314 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 315 316 317 318 319 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 320 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 321 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 322 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 323 324 325 326 327 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 328 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 329 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 330 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 331 332 333 334 335 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 336 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 337 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 338 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 339 340 341 342 #endif 343