1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 enum ftr_type {
19 FTR_EXACT, /* Use a predefined safe value */
20 FTR_LOWER_SAFE, /* Smaller value is safe */
21 FTR_HIGHER_SAFE, /* Bigger value is safe */
22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
23 FTR_END, /* Mark the last ftr bits */
24 };
25
26 #define FTR_SIGNED true /* Value should be treated as signed */
27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
28
29 struct reg_ftr_bits {
30 char *name;
31 bool sign;
32 enum ftr_type type;
33 uint8_t shift;
34 uint64_t mask;
35 /*
36 * For FTR_EXACT, safe_val is used as the exact safe value.
37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
38 */
39 int64_t safe_val;
40 };
41
42 struct test_feature_reg {
43 uint32_t reg;
44 const struct reg_ftr_bits *ftr_bits;
45 };
46
47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
48 { \
49 .name = #NAME, \
50 .sign = SIGNED, \
51 .type = TYPE, \
52 .shift = SHIFT, \
53 .mask = MASK, \
54 .safe_val = SAFE_VAL, \
55 }
56
57 #define REG_FTR_BITS(type, reg, field, safe_val) \
58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
59 reg##_##field##_MASK, safe_val)
60
61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
63 reg##_##field##_MASK, safe_val)
64
65 #define REG_FTR_END \
66 { \
67 .type = FTR_END, \
68 }
69
70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
75 REG_FTR_END,
76 };
77
78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
81 REG_FTR_END,
82 };
83
84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
100 REG_FTR_END,
101 };
102
103 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
116 REG_FTR_END,
117 };
118
119 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
123 REG_FTR_END,
124 };
125
126 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
131 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0),
133 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0),
136 REG_FTR_END,
137 };
138
139 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
143 REG_FTR_END,
144 };
145
146 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
149 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
150 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
151 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
152 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
153 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
154 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0),
156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
157 REG_FTR_END,
158 };
159
160 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
161 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
164 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
169 REG_FTR_END,
170 };
171
172 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
176 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
183 REG_FTR_END,
184 };
185
186 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
188 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
195 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
196 REG_FTR_END,
197 };
198
199 #define TEST_REG(id, table) \
200 { \
201 .reg = id, \
202 .ftr_bits = &((table)[0]), \
203 }
204
205 static struct test_feature_reg test_regs[] = {
206 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
207 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
208 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
209 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
210 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
211 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
212 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
213 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
214 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
215 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
216 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
217 };
218
219 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
220
guest_code(void)221 static void guest_code(void)
222 {
223 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
224 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
225 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
226 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
227 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
228 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
229 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
230 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
231 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
232 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
233 GUEST_REG_SYNC(SYS_CTR_EL0);
234
235 GUEST_DONE();
236 }
237
238 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)239 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
240 {
241 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
242
243 if (ftr_bits->sign == FTR_UNSIGNED) {
244 switch (ftr_bits->type) {
245 case FTR_EXACT:
246 ftr = ftr_bits->safe_val;
247 break;
248 case FTR_LOWER_SAFE:
249 if (ftr > ftr_bits->safe_val)
250 ftr--;
251 break;
252 case FTR_HIGHER_SAFE:
253 if (ftr < ftr_max)
254 ftr++;
255 break;
256 case FTR_HIGHER_OR_ZERO_SAFE:
257 if (ftr == ftr_max)
258 ftr = 0;
259 else if (ftr != 0)
260 ftr++;
261 break;
262 default:
263 break;
264 }
265 } else if (ftr != ftr_max) {
266 switch (ftr_bits->type) {
267 case FTR_EXACT:
268 ftr = ftr_bits->safe_val;
269 break;
270 case FTR_LOWER_SAFE:
271 if (ftr > ftr_bits->safe_val)
272 ftr--;
273 break;
274 case FTR_HIGHER_SAFE:
275 if (ftr < ftr_max - 1)
276 ftr++;
277 break;
278 case FTR_HIGHER_OR_ZERO_SAFE:
279 if (ftr != 0 && ftr != ftr_max - 1)
280 ftr++;
281 break;
282 default:
283 break;
284 }
285 }
286
287 return ftr;
288 }
289
290 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)291 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
292 {
293 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
294
295 if (ftr_bits->sign == FTR_UNSIGNED) {
296 switch (ftr_bits->type) {
297 case FTR_EXACT:
298 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
299 break;
300 case FTR_LOWER_SAFE:
301 ftr++;
302 break;
303 case FTR_HIGHER_SAFE:
304 ftr--;
305 break;
306 case FTR_HIGHER_OR_ZERO_SAFE:
307 if (ftr == 0)
308 ftr = ftr_max;
309 else
310 ftr--;
311 break;
312 default:
313 break;
314 }
315 } else if (ftr != ftr_max) {
316 switch (ftr_bits->type) {
317 case FTR_EXACT:
318 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
319 break;
320 case FTR_LOWER_SAFE:
321 ftr++;
322 break;
323 case FTR_HIGHER_SAFE:
324 ftr--;
325 break;
326 case FTR_HIGHER_OR_ZERO_SAFE:
327 if (ftr == 0)
328 ftr = ftr_max - 1;
329 else
330 ftr--;
331 break;
332 default:
333 break;
334 }
335 } else {
336 ftr = 0;
337 }
338
339 return ftr;
340 }
341
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)342 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
343 const struct reg_ftr_bits *ftr_bits)
344 {
345 uint8_t shift = ftr_bits->shift;
346 uint64_t mask = ftr_bits->mask;
347 uint64_t val, new_val, ftr;
348
349 vcpu_get_reg(vcpu, reg, &val);
350 ftr = (val & mask) >> shift;
351
352 ftr = get_safe_value(ftr_bits, ftr);
353
354 ftr <<= shift;
355 val &= ~mask;
356 val |= ftr;
357
358 vcpu_set_reg(vcpu, reg, val);
359 vcpu_get_reg(vcpu, reg, &new_val);
360 TEST_ASSERT_EQ(new_val, val);
361
362 return new_val;
363 }
364
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)365 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
366 const struct reg_ftr_bits *ftr_bits)
367 {
368 uint8_t shift = ftr_bits->shift;
369 uint64_t mask = ftr_bits->mask;
370 uint64_t val, old_val, ftr;
371 int r;
372
373 vcpu_get_reg(vcpu, reg, &val);
374 ftr = (val & mask) >> shift;
375
376 ftr = get_invalid_value(ftr_bits, ftr);
377
378 old_val = val;
379 ftr <<= shift;
380 val &= ~mask;
381 val |= ftr;
382
383 r = __vcpu_set_reg(vcpu, reg, val);
384 TEST_ASSERT(r < 0 && errno == EINVAL,
385 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
386
387 vcpu_get_reg(vcpu, reg, &val);
388 TEST_ASSERT_EQ(val, old_val);
389 }
390
391 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
392
393 #define encoding_to_range_idx(encoding) \
394 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
395 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
396 sys_reg_Op2(encoding))
397
398
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)399 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
400 {
401 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
402 struct reg_mask_range range = {
403 .addr = (__u64)masks,
404 };
405 int ret;
406
407 /* KVM should return error when reserved field is not zero */
408 range.reserved[0] = 1;
409 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
410 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
411
412 /* Get writable masks for feature ID registers */
413 memset(range.reserved, 0, sizeof(range.reserved));
414 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
415
416 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
417 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
418 uint32_t reg_id = test_regs[i].reg;
419 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
420 int idx;
421
422 /* Get the index to masks array for the idreg */
423 idx = encoding_to_range_idx(reg_id);
424
425 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
426 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
427 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
428 ksft_test_result_skip("%s on AARCH64 only system\n",
429 ftr_bits[j].name);
430 continue;
431 }
432
433 /* Make sure the feature field is writable */
434 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
435
436 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
437
438 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
439 &ftr_bits[j]);
440
441 ksft_test_result_pass("%s\n", ftr_bits[j].name);
442 }
443 }
444 }
445
test_guest_reg_read(struct kvm_vcpu * vcpu)446 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
447 {
448 bool done = false;
449 struct ucall uc;
450
451 while (!done) {
452 vcpu_run(vcpu);
453
454 switch (get_ucall(vcpu, &uc)) {
455 case UCALL_ABORT:
456 REPORT_GUEST_ASSERT(uc);
457 break;
458 case UCALL_SYNC:
459 /* Make sure the written values are seen by guest */
460 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
461 uc.args[3]);
462 break;
463 case UCALL_DONE:
464 done = true;
465 break;
466 default:
467 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
468 }
469 }
470 }
471
472 /* Politely lifted from arch/arm64/include/asm/cache.h */
473 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
474 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
475 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
476 #define CLIDR_CTYPE(clidr, level) \
477 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
478
test_clidr(struct kvm_vcpu * vcpu)479 static void test_clidr(struct kvm_vcpu *vcpu)
480 {
481 uint64_t clidr;
482 int level;
483
484 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), &clidr);
485
486 /* find the first empty level in the cache hierarchy */
487 for (level = 1; level < 7; level++) {
488 if (!CLIDR_CTYPE(clidr, level))
489 break;
490 }
491
492 /*
493 * If you have a mind-boggling 7 levels of cache, congratulations, you
494 * get to fix this.
495 */
496 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
497
498 /* stick in a unified cache level */
499 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
500
501 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
502 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
503 }
504
test_ctr(struct kvm_vcpu * vcpu)505 static void test_ctr(struct kvm_vcpu *vcpu)
506 {
507 u64 ctr;
508
509 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), &ctr);
510 ctr &= ~CTR_EL0_DIC_MASK;
511 if (ctr & CTR_EL0_IminLine_MASK)
512 ctr--;
513
514 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
515 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
516 }
517
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)518 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
519 {
520 u64 val;
521
522 test_clidr(vcpu);
523 test_ctr(vcpu);
524
525 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &val);
526 val++;
527 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), val);
528
529 test_reg_vals[encoding_to_range_idx(SYS_MPIDR_EL1)] = val;
530 ksft_test_result_pass("%s\n", __func__);
531 }
532
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)533 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
534 {
535 size_t idx = encoding_to_range_idx(encoding);
536 uint64_t observed;
537
538 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding), &observed);
539 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
540 }
541
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)542 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
543 {
544 /*
545 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
546 * architectural reset of the vCPU.
547 */
548 aarch64_vcpu_setup(vcpu, NULL);
549
550 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
551 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
552
553 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
554 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
555 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
556
557 ksft_test_result_pass("%s\n", __func__);
558 }
559
main(void)560 int main(void)
561 {
562 struct kvm_vcpu *vcpu;
563 struct kvm_vm *vm;
564 bool aarch64_only;
565 uint64_t val, el0;
566 int test_cnt;
567
568 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
569
570 vm = vm_create_with_one_vcpu(&vcpu, guest_code);
571
572 /* Check for AARCH64 only system */
573 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
574 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
575 aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
576
577 ksft_print_header();
578
579 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
580 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
581 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
582 ARRAY_SIZE(ftr_id_aa64pfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
583 ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
584 ARRAY_SIZE(ftr_id_aa64zfr0_el1) - ARRAY_SIZE(test_regs) + 2;
585
586 ksft_set_plan(test_cnt);
587
588 test_vm_ftr_id_regs(vcpu, aarch64_only);
589 test_vcpu_ftr_id_regs(vcpu);
590
591 test_guest_reg_read(vcpu);
592
593 test_reset_preserves_id_regs(vcpu);
594
595 kvm_vm_free(vm);
596
597 ksft_finished();
598 }
599