1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * nau8325.h -- Nuvoton NAU8325 audio codec driver 4 * 5 * Copyright 2023 Nuvoton Technology Crop. 6 * Author: Seven Lee <WTLI@nuvoton.com> 7 * David Lin <CTLIN0@nuvoton.com> 8 */ 9 10 #ifndef __NAU8325_H__ 11 #define __NAU8325_H__ 12 13 #define NAU8325_R00_HARDWARE_RST 0x00 14 #define NAU8325_R01_SOFTWARE_RST 0x01 15 #define NAU8325_R02_DEVICE_ID 0x02 16 #define NAU8325_R03_CLK_CTRL 0x03 17 #define NAU8325_R04_ENA_CTRL 0x04 18 #define NAU8325_R05_INTERRUPT_CTRL 0x05 19 #define NAU8325_R06_INT_CLR_STATUS 0x06 20 #define NAU8325_R09_IRQOUT 0x09 21 #define NAU8325_R0A_IO_CTRL 0x0a 22 #define NAU8325_R0B_PDM_CTRL 0x0b 23 #define NAU8325_R0C_TDM_CTRL 0x0c 24 #define NAU8325_R0D_I2S_PCM_CTRL1 0x0d 25 #define NAU8325_R0E_I2S_PCM_CTRL2 0x0e 26 #define NAU8325_R0F_L_TIME_SLOT 0x0f 27 #define NAU8325_R10_R_TIME_SLOT 0x10 28 #define NAU8325_R11_HPF_CTRL 0x11 29 #define NAU8325_R12_MUTE_CTRL 0x12 30 #define NAU8325_R13_DAC_VOLUME 0x13 31 #define NAU8325_R1D_DEBUG_READ1 0x1d 32 #define NAU8325_R1F_DEBUG_READ2 0x1f 33 #define NAU8325_R22_DEBUG_READ3 0x22 34 #define NAU8325_R29_DAC_CTRL1 0x29 35 #define NAU8325_R2A_DAC_CTRL2 0x2a 36 #define NAU8325_R2C_ALC_CTRL1 0x2c 37 #define NAU8325_R2D_ALC_CTRL2 0x2d 38 #define NAU8325_R2E_ALC_CTRL3 0x2e 39 #define NAU8325_R2F_ALC_CTRL4 0x2f 40 #define NAU8325_R40_CLK_DET_CTRL 0x40 41 #define NAU8325_R49_TEST_STATUS 0x49 42 #define NAU8325_R4A_ANALOG_READ 0x4a 43 #define NAU8325_R50_MIXER_CTRL 0x50 44 #define NAU8325_R55_MISC_CTRL 0x55 45 #define NAU8325_R60_BIAS_ADJ 0x60 46 #define NAU8325_R61_ANALOG_CONTROL_1 0x61 47 #define NAU8325_R62_ANALOG_CONTROL_2 0x62 48 #define NAU8325_R63_ANALOG_CONTROL_3 0x63 49 #define NAU8325_R64_ANALOG_CONTROL_4 0x64 50 #define NAU8325_R65_ANALOG_CONTROL_5 0x65 51 #define NAU8325_R66_ANALOG_CONTROL_6 0x66 52 #define NAU8325_R69_CLIP_CTRL 0x69 53 #define NAU8325_R73_RDAC 0x73 54 #define NAU8325_REG_MAX NAU8325_R73_RDAC 55 56 /* 16-bit control register address, and 16-bits control register data */ 57 #define NAU8325_REG_ADDR_LEN 16 58 #define NAU8325_REG_DATA_LEN 16 59 60 /* CLK_CTRL (0x03) */ 61 #define NAU8325_CLK_DAC_SRC_SFT 12 62 #define NAU8325_CLK_DAC_SRC_MASK (0x3 << NAU8325_CLK_DAC_SRC_SFT) 63 #define NAU8325_CLK_MUL_SRC_SFT 6 64 #define NAU8325_CLK_MUL_SRC_MASK (0x3 << NAU8325_CLK_MUL_SRC_SFT) 65 #define NAU8325_MCLK_SEL_SFT 3 66 #define NAU8325_MCLK_SEL_MASK (0x7 << NAU8325_MCLK_SEL_SFT) 67 #define NAU8325_MCLK_SRC_MASK 0x7 68 69 /* ENA_CTRL (0x04) */ 70 #define NAU8325_DAC_LEFT_CH_EN_SFT 3 71 #define NAU8325_DAC_LEFT_CH_EN (0x1 << NAU8325_DAC_LEFT_CH_EN_SFT) 72 #define NAU8325_DAC_RIGHT_CH_EN_SFT 2 73 #define NAU8325_DAC_RIGHT_CH_EN (0x1 << NAU8325_DAC_RIGHT_CH_EN_SFT) 74 75 /* INTERRUPT_CTRL (0x05) */ 76 #define NAU8325_ARP_DWN_INT_SFT 12 77 #define NAU8325_ARP_DWN_INT_MASK (0x1 << NAU8325_ARP_DWN_INT_SFT) 78 #define NAU8325_CLIP_INT_SFT 11 79 #define NAU8325_CLIP_INT_MASK (0x1 << NAU8325_CLIP_INT_SFT) 80 #define NAU8325_LVD_INT_SFT 10 81 #define NAU8325_LVD_INT_MASK (0x1 << NAU8325_LVD_INT_SFT) 82 #define NAU8325_PWR_INT_DIS_SFT 8 83 #define NAU8325_PWR_INT_DIS (0x1 << NAU8325_PWR_INT_DIS_SFT) 84 #define NAU8325_OCP_OTP_SHTDWN_INT_SFT 4 85 #define NAU8325_OCP_OTP_SHTDWN_INT_MASK (0x1 << NAU8325_OCP_OTP_SHTDWN_INT_SFT) 86 #define NAU8325_CLIP_INT_DIS_SFT 3 87 #define NAU8325_CLIP_INT_DIS (0x1 << NAU8325_CLIP_INT_DIS_SFT) 88 #define NAU8325_LVD_INT_DIS_SFT 2 89 #define NAU8325_LVD_INT_DIS (0x1 << NAU8325_LVD_INT_DIS_SFT) 90 #define NAU8325_PWR_INT_MASK 0x1 91 92 /* INT_CLR_STATUS (0x06) */ 93 #define NAU8325_INT_STATUS_MASK 0x7f 94 95 /* IRQOUT (0x9) */ 96 #define NAU8325_IRQOUT_SEL_SEF 12 97 #define NAU8325_IRQOUT_SEL_MASK (0xf << NAU8325_IRQOUT_SEL_SEF) 98 #define NAU8325_DEM_DITH_SFT 7 99 #define NAU8325_DEM_DITH_EN (0x1 << NAU8325_DEM_DITH_SFT) 100 #define NAU8325_GAINZI3_SFT 5 101 #define NAU8325_GAINZI3_MASK (0x1 << NAU8325_GAINZI3_SFT) 102 #define NAU8325_GAINZI2_MASK 0x1f 103 104 /* IO_CTRL (0x0a) */ 105 #define NAU8325_IRQ_PL_SFT 15 106 #define NAU8325_IRQ_PL_ACT_HIGH (0x1 << NAU8325_IRQ_PL_SFT) 107 #define NAU8325_IRQ_PS_SFT 14 108 #define NAU8325_IRQ_PS_UP (0x1 << NAU8325_IRQ_PS_SFT) 109 #define NAU8325_IRQ_PE_SFT 13 110 #define NAU8325_IRQ_PE_EN (0x1 << NAU8325_IRQ_PE_SFT) 111 #define NAU8325_IRQ_DS_SFT 12 112 #define NAU8325_IRQ_DS_HIGH (0x1 << NAU8325_IRQ_DS_SFT) 113 #define NAU8325_IRQ_OUTPUT_SFT 11 114 #define NAU8325_IRQ_OUTPUT_EN (0x1 << NAU8325_IRQ_OUTPUT_SFT) 115 #define NAU8325_IRQ_PIN_DEBUG_SFT 10 116 #define NAU8325_IRQ_PIN_DEBUG_EN (0x1 << NAU8325_IRQ_PIN_DEBUG_SFT) 117 118 /* PDM_CTRL (0x0b) */ 119 #define NAU8325_PDM_LCH_EDGE_SFT 1 120 #define NAU8325_PDM_LCH_EDGE__MASK (0x1 << NAU8325_PDM_LCH_EDGE_SFT) 121 #define NAU8325_PDM_MODE_EN 0x1 122 123 /* TDM_CTRL (0x0c) */ 124 #define NAU8325_TDM_SFT 15 125 #define NAU8325_TDM_EN (0x1 << NAU8325_TDM_SFT) 126 #define NAU8325_PCM_OFFSET_CTRL_SFT 14 127 #define NAU8325_PCM_OFFSET_CTRL_EN (0x1 << NAU8325_PCM_OFFSET_CTRL_SFT) 128 #define NAU8325_DAC_LEFT_SFT 6 129 #define NAU8325_NAU8325_DAC_LEFT_MASK (0x7 << NAU8325_DAC_LEFT_SFT) 130 #define NAU8325_DAC_RIGHT_SFT 3 131 #define NAU8325_DAC_RIGHT_MASK (0x7 << NAU8325_DAC_RIGHT_SFT) 132 133 /* I2S_PCM_CTRL1 (0x0d) */ 134 #define NAU8325_DACCM_CTL_SFT 14 135 #define NAU8325_DACCM_CTL_MASK (0x3 << NAU8325_DACCM_CTL_SFT) 136 #define NAU8325_CMB8_0_SFT 10 137 #define NAU8325_CMB8_0_MASK (0x1 << NAU8325_CMB8_0_SFT) 138 #define NAU8325_UA_OFFSET_SFT 9 139 #define NAU8325_UA_OFFSET_MASK (0x1 << NAU8325_UA_OFFSET_SFT) 140 #define NAU8325_I2S_BP_SFT 7 141 #define NAU8325_I2S_BP_MASK (0x1 << NAU8325_I2S_BP_SFT) 142 #define NAU8325_I2S_BP_INV (0x1 << NAU8325_I2S_BP_SFT) 143 #define NAU8325_I2S_PCMB_SFT 6 144 #define NAU8325_I2S_PCMB_EN (0x1 << NAU8325_I2S_PCMB_SFT) 145 #define NAU8325_I2S_DACPSHS0_SFT 5 146 #define NAU8325_I2S_DACPSHS0_MASK (0x1 << NAU8325_I2S_DACPSHS0_SFT) 147 #define NAU8325_I2S_DL_SFT 2 148 #define NAU8325_I2S_DL_MASK (0x3 << NAU8325_I2S_DL_SFT) 149 #define NAU8325_I2S_DL_32 (0x3 << NAU8325_I2S_DL_SFT) 150 #define NAU8325_I2S_DL_24 (0x2 << NAU8325_I2S_DL_SFT) 151 #define NAU8325_I2S_DL_20 (0x1 << NAU8325_I2S_DL_SFT) 152 #define NAU8325_I2S_DL_16 (0x0 << NAU8325_I2S_DL_SFT) 153 #define NAU8325_I2S_DF_MASK 0x3 154 #define NAU8325_I2S_DF_RIGTH 0x0 155 #define NAU8325_I2S_DF_LEFT 0x1 156 #define NAU8325_I2S_DF_I2S 0x2 157 #define NAU8325_I2S_DF_PCM_AB 0x3 158 159 /* I2S_PCM_CTRL2 (0x0e) */ 160 #define NAU8325_PCM_TS_SFT 10 161 #define NAU8325_PCM_TS_EN (0x1 << NAU8325_PCM_TS_SFT) 162 #define NAU8325_PCM8BIT0_SFT 8 163 #define NAU8325_PCM8BIT0_MASK (0x1 << NAU8325_PCM8BIT0_SFT) 164 165 /* L_TIME_SLOT (0x0f)*/ 166 #define NAU8325_SHORT_FS_DET_SFT 13 167 #define NAU8325_SHORT_FS_DET_DIS (0x1 << NAU8325_SHORT_FS_DET_SFT) 168 #define NAU8325_TSLOT_L0_MASK 0x3ff 169 170 /* R_TIME_SLOT (0x10)*/ 171 #define NAU8325_TSLOT_R0_MASK 0x3ff 172 173 /* HPF_CTRL (0x11)*/ 174 #define NAU8325_DAC_HPF_SFT 15 175 #define NAU8325_DAC_HPF_EN (0x1 << NAU8325_DAC_HPF_SFT) 176 #define NAU8325_DAC_HPF_APP_SFT 14 177 #define NAU8325_DAC_HPF_APP_MASK (0x1 << NAU8325_DAC_HPF_APP_SFT) 178 #define NAU8325_DAC_HPF_FCUT_SFT 11 179 #define NAU8325_DAC_HPF_FCUT_MASK (0x7 << NAU8325_DAC_HPF_FCUT_SFT) 180 181 /* MUTE_CTRL (0x12)*/ 182 #define NAU8325_SOFT_MUTE_SFT 15 183 #define NAU8325_SOFT_MUTE (0x1 << NAU8325_SOFT_MUTE_SFT) 184 #define NAU8325_DAC_ZC_SFT 8 185 #define NAU8325_DAC_ZC_EN (0x1 << NAU8325_DAC_ZC_SFT) 186 #define NAU8325_UNMUTE_CTL_SFT 6 187 #define NAU8325_UNMUTE_CTL_MASK (0x3 << NAU8325_UNMUTE_CTL_SFT) 188 #define NAU8325_ANA_MUTE_SFT 4 189 #define NAU8325_ANA_MUTE_MASK (0x3 << NAU8325_ANA_MUTE_SFT) 190 #define NAU8325_AUTO_MUTE_SFT 3 191 #define NAU8325_AUTO_MUTE_DIS (0x1 << NAU8325_AUTO_MUTE_SFT) 192 193 /* DAC_VOLUME (0x13) */ 194 #define NAU8325_DAC_VOLUME_L_SFT 8 195 #define NAU8325_DAC_VOLUME_L_EN (0xff << NAU8325_DAC_VOLUME_L_SFT) 196 #define NAU8325_DAC_VOLUME_R_SFT 0 197 #define NAU8325_DAC_VOLUME_R_EN (0xff << NAU8325_DAC_VOLUME_R_SFT) 198 #define NAU8325_DAC_VOL_MAX 0xff 199 200 /* DEBUG_READ1 (0x1d)*/ 201 #define NAU8325_OSR100_MASK (0x1 << 6) 202 #define NAU8325_MIPS500_MASK (0x1 << 5) 203 #define NAU8325_SHUTDWNDRVR_R_MASK (0x1 << 4) 204 #define NAU8325_SHUTDWNDRVR_L_MASK (0x1 << 3) 205 #define NAU8325_MUTEB_MASK (0x1 << 2) 206 #define NAU8325_PDOSCB_MASK (0x1 << 1) 207 #define NAU8325_POWERDOWN1B_D_MASK 0x1 208 209 /* DEBUG_READ2 (0x1f)*/ 210 #define NAU8325_R_CHANNEL_Vol_SFT 8 211 #define NAU8325_R_CHANNEL_Vol_MASK (0xff << NAU8325_R_CHANNEL_Vol_SFT) 212 #define NAU8325_L_CHANNEL_Vol_MASK 0xff 213 214 /* DEBUG_READ3(0x22)*/ 215 #define NAU8325_PGAL_GAIN_MASK (0x3f << 7) 216 #define NAU8325_CLIP_MASK (0x1 << 6) 217 #define NAU8325_SCAN_MODE_MASK (0x1 << 5) 218 #define NAU8325_SDB_MASK (0x1 << 4) 219 #define NAU8325_TALARM_MASK (0x1 << 3) 220 #define NAU8325_SHORTR_MASK (0x1 << 2) 221 #define NAU8325_SHORTL_MASK (0x1 << 1) 222 #define NAU8325_TMDET_MASK 0x1 223 224 /* DAC_CTRL1 (0x29) */ 225 #define NAU8325_DAC_OVERSAMPLE_SFT 0 226 #define NAU8325_DAC_OVERSAMPLE_MASK 0x7 227 #define NAU8325_DAC_OVERSAMPLE_256 1 228 #define NAU8325_DAC_OVERSAMPLE_128 2 229 #define NAU8325_DAC_OVERSAMPLE_64 0 230 #define NAU8325_DAC_OVERSAMPLE_32 4 231 232 /* ALC_CTRL1 (0x2c) */ 233 #define NAU8325_ALC_MAXGAIN_SFT 5 234 #define NAU8325_ALC_MAXGAIN_MAX 0x7 235 #define NAU8325_ALC_MAXGAIN_MASK (0x7 << NAU8325_ALC_MAXGAIN_SFT) 236 #define NAU8325_ALC_MINGAIN_MAX 4 237 #define NAU8325_ALC_MINGAIN_SFT 1 238 #define NAU8325_ALC_MINGAIN_MASK (0x7 << NAU8325_ALC_MINGAIN_SFT) 239 240 /* ALC_CTRL2 (0x2d) */ 241 #define NAU8325_ALC_DCY_SFT 12 242 #define NAU8325_ALC_DCY_MAX 0xb 243 #define NAU8325_ALC_DCY_MASK (0xf << NAU8325_ALC_DCY_SFT) 244 #define NAU8325_ALC_ATK_SFT 8 245 #define NAU8325_ALC_ATK_MAX 0xb 246 #define NAU8325_ALC_ATK_MASK (0xf << NAU8325_ALC_ATK_SFT) 247 #define NAU8325_ALC_HLD_SFT 4 248 #define NAU8325_ALC_HLD_MAX 0xa 249 #define NAU8325_ALC_HLD_MASK (0xf << NAU8325_ALC_HLD_SFT) 250 #define NAU8325_ALC_LVL_SFT 0 251 #define NAU8325_ALC_LVL_MAX 0xf 252 #define NAU8325_ALC_LVL_MASK 0xf 253 254 /* ALC_CTRL3 (0x2e) */ 255 #define NAU8325_ALC_EN_SFT 15 256 #define NAU8325_ALC_EN (0x1 << NAU8325_ALC_EN_SFT) 257 258 /* TEMP_COMP_CTRL (0x30) */ 259 #define NAU8325_TEMP_COMP_ACT2_MASK 0xff 260 261 /* LPF_CTRL (0x33) */ 262 #define NAU8325_LPF_IN1_EN_SFT 15 263 #define NAU8325_LPF_IN1_EN (0x1 << NAU8325_LPF_IN1_EN_SFT) 264 #define NAU8325_LPF_IN1_TC_SFT 11 265 #define NAU8325_LPF_IN1_TC_MASK (0xf << NAU8325_LPF_IN1_TC_SFT) 266 #define NAU8325_LPF_IN2_EN_SFT 10 267 #define NAU8325_LPF_IN2_EN (0x1 << NAU8325_LPF_IN2_EN_SFT) 268 #define NAU8325_LPF_IN2_TC_SFT 6 269 #define NAU8325_LPF_IN2_TC_MASK (0xf << NAU8325_LPF_IN2_TC_SFT) 270 271 /* CLK_DET_CTRL (0x40) */ 272 #define NAU8325_APWRUP_SFT 15 273 #define NAU8325_APWRUP_EN (0x1 << NAU8325_APWRUP_SFT) 274 #define NAU8325_CLKPWRUP_SFT 14 275 #define NAU8325_CLKPWRUP_DIS (0x1 << NAU8325_CLKPWRUP_SFT) 276 #define NAU8325_PWRUP_DFT_SFT 13 277 #define NAU8325_PWRUP_DFT (0x1 << NAU8325_PWRUP_DFT_SFT) 278 #define NAU8325_REG_SRATE_SFT 10 279 #define NAU8325_REG_SRATE_MASK (0x7 << NAU8325_REG_SRATE_SFT) 280 #define NAU8325_REG_ALT_SRATE_SFT 9 281 #define NAU8325_REG_ALT_SRATE_EN (0x1 << NAU8325_REG_ALT_SRATE_SFT) 282 #define NAU8325_REG_DIV_MAX 0x1 283 284 /* BIAS_ADJ (0x60) */ 285 #define NAU8325_BIAS_VMID_SEL_SFT 4 286 #define NAU8325_BIAS_VMID_SEL_MASK (0x3 << NAU8325_BIAS_VMID_SEL_SFT) 287 288 /* ANALOG_CONTROL_1 (0x61) */ 289 #define NAU8325_VMDFSTENB_SFT 14 290 #define NAU8325_VMDFSTENB_MASK (0x3 << NAU8325_VMDFSTENB_SFT) 291 #define NAU8325_CLASSDEN_SFT 12 292 #define NAU8325_CLASSDEN_MASK (0x3 << NAU8325_CLASSDEN_SFT) 293 #define NAU8325_DACCLKEN_R_SFT 10 294 #define NAU8325_DACCLKEN_R_MASK (0x3 << NAU8325_DACCLKEN_R_SFT) 295 #define NAU8325_DACEN_R_SFT 8 296 #define NAU8325_DACEN_R_MASK (0x3 << NAU8325_DACEN_R_SFT) 297 #define NAU8325_DACCLKEN_SFT 6 298 #define NAU8325_DACCLKEN_MASK (0x3 << NAU8325_DACCLKEN_SFT) 299 #define NAU8325_DACEN_SFT 4 300 #define NAU8325_DACEN_MASK (0x3 << NAU8325_DACEN_SFT) 301 #define NAU8325_BIASEN_SFT 2 302 #define NAU8325_BIASEN_MASK (0x3 << NAU8325_BIASEN_SFT) 303 #define NAU8325_VMIDEN_MASK 0x3 304 305 /* ANALOG_CONTROL_2 (0x62) */ 306 #define NAU8325_PWMMOD_SFT 14 307 #define NAU8325_PWMMOD_MASK (0x1 << NAU8325_PWMMOD_SFT) 308 #define NAU8325_DACTEST_SFT 6 309 #define NAU8325_DACTEST_MASK (0x3 << NAU8325_DACTEST_SFT) 310 #define NAU8325_DACREFCAP_SFT 4 311 #define NAU8325_DACREFCAP_MASK (0x3 << NAU8325_DACREFCAP_SFT) 312 313 /* ANALOG_CONTROL_3 (0x63) */ 314 #define NAU8325_POWER_DOWN_L_SFT 12 315 #define NAU8325_POWER_DOWN_L_MASK (0x3 << NAU8325_POWER_DOWN_L_SFT) 316 #define NAU8325_POWER_DOWN_R_SFT 11 317 #define NAU8325_POWER_DOWN_R_MASK (0x3 << NAU8325_DACREFCAP_SFT) 318 #define NAU8325_CLASSD_FINE_SFT 5 319 #define NAU8325_CLASSD_FINE_MASK (0x3 << NAU8325_CLASSD_FINE_SFT) 320 #define NAU8325_CLASSD_COARSE_GAIN_MASK 0xf 321 322 /* ANALOG_CONTROL_4 (0x64) */ 323 #define NAU8325_CLASSD_OCPN_SFT 12 324 #define NAU8325_CLASSD_OCPN_MASK (0xf << NAU8325_CLASSD_OCPN_SFT) 325 #define NAU8325_CLASSD_OCPP_SFT 8 326 #define NAU8325_CLASSD_OCPP_MASK (0xf << NAU8325_CLASSD_OCPP_SFT) 327 #define NAU8325_CLASSD_SLEWN_MASK 0xff 328 329 /* ANALOG_CONTROL_5 (0x65) */ 330 #define NAU8325_MCLK_RANGE_SFT 2 331 #define NAU8325_MCLK_RANGE_EN (0x1 << NAU8325_MCLK_RANGE_SFT) 332 #define NAU8325_MCLK8XEN_SFT 1 333 #define NAU8325_MCLK8XEN_EN (0x1 << NAU8325_MCLK8XEN_SFT) 334 #define NAU8325_MCLK4XEN_EN 0x1 335 336 /* ANALOG_CONTROL_6 (0x66) */ 337 #define NAU8325_VBATLOW_SFT 4 338 #define NAU8325_VBATLOW_MASK (0x1 << NAU8325_VBATLOW_SFT) 339 #define NAU8325_VDDSPK_LIM_SFT 3 340 #define NAU8325_VDDSPK_LIM_EN (0x1 << NAU8325_VDDSPK_LIM_SFT) 341 #define NAU8325_VDDSPK_LIM_MASK 0x7 342 343 /* CLIP_CTRL (0x69)*/ 344 #define NAU8325_ANTI_CLIP_SFT 4 345 #define NAU8325_ANTI_CLIP_EN (0x1 << NAU8325_ANTI_CLIP_SFT) 346 347 /* RDAC (0x73) */ 348 #define NAU8325_CLK_DAC_DELAY_SFT 4 349 #define NAU8325_CLK_DAC_DELAY_EN (0x7 << NAU8325_CLK_DAC_DELAY_SFT) 350 #define NAU8325_DACVREFSEL_SFT 2 351 #define NAU8325_DACVREFSEL_MASK (0x3 << NAU8325_DACVREFSEL_SFT) 352 353 #define NAU8325_CODEC_DAI "nau8325-hifi" 354 355 struct nau8325 { 356 struct device *dev; 357 struct regmap *regmap; 358 int mclk; 359 int fs; 360 int vref_impedance_ohms; 361 int dac_vref_microvolt; 362 int clock_detection; 363 int clock_det_data; 364 int alc_enable; 365 }; 366 367 struct nau8325_src_attr { 368 int param; 369 unsigned int val; 370 }; 371 372 enum { 373 NAU8325_MCLK_FS_RATIO_256, 374 NAU8325_MCLK_FS_RATIO_400, 375 NAU8325_MCLK_FS_RATIO_500, 376 NAU8325_MCLK_FS_RATIO_NUM, 377 }; 378 379 struct nau8325_srate_attr { 380 int fs; 381 int range; 382 bool max; 383 unsigned int mclk_src[NAU8325_MCLK_FS_RATIO_NUM]; 384 }; 385 386 struct nau8325_osr_attr { 387 unsigned int osr; 388 unsigned int clk_src; 389 }; 390 391 #endif /* __NAU8325_H__ */ 392