1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4  */
5 
6 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
7 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
8 #include <dt-bindings/gpio/meson-a1-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/meson-a1-power.h>
12 #include <dt-bindings/reset/amlogic,meson-a1-reset.h>
13 
14 / {
15 	compatible = "amlogic,a1";
16 
17 	interrupt-parent = <&gic>;
18 	#address-cells = <2>;
19 	#size-cells = <2>;
20 
21 	cpus {
22 		#address-cells = <2>;
23 		#size-cells = <0>;
24 
25 		cpu0: cpu@0 {
26 			device_type = "cpu";
27 			compatible = "arm,cortex-a35";
28 			reg = <0x0 0x0>;
29 			enable-method = "psci";
30 			next-level-cache = <&l2>;
31 			#cooling-cells = <2>;
32 		};
33 
34 		cpu1: cpu@1 {
35 			device_type = "cpu";
36 			compatible = "arm,cortex-a35";
37 			reg = <0x0 0x1>;
38 			enable-method = "psci";
39 			next-level-cache = <&l2>;
40 			#cooling-cells = <2>;
41 		};
42 
43 		l2: l2-cache0 {
44 			compatible = "cache";
45 			cache-level = <2>;
46 			cache-unified;
47 		};
48 	};
49 
50 	efuse: efuse {
51 		compatible = "amlogic,meson-gxbb-efuse";
52 		clocks = <&clkc_periphs CLKID_OTP>;
53 		#address-cells = <1>;
54 		#size-cells = <1>;
55 		secure-monitor = <&sm>;
56 		power-domains = <&pwrc PWRC_OTP_ID>;
57 	};
58 
59 	psci {
60 		compatible = "arm,psci-1.0";
61 		method = "smc";
62 	};
63 
64 	reserved-memory {
65 		#address-cells = <2>;
66 		#size-cells = <2>;
67 		ranges;
68 
69 		linux,cma {
70 			compatible = "shared-dma-pool";
71 			reusable;
72 			size = <0x0 0x800000>;
73 			alignment = <0x0 0x400000>;
74 			linux,cma-default;
75 		};
76 	};
77 
78 	sm: secure-monitor {
79 		compatible = "amlogic,meson-gxbb-sm";
80 
81 		pwrc: power-controller {
82 			compatible = "amlogic,meson-a1-pwrc";
83 			#power-domain-cells = <1>;
84 		};
85 	};
86 
87 	soc {
88 		compatible = "simple-bus";
89 		#address-cells = <2>;
90 		#size-cells = <2>;
91 		ranges;
92 
93 		spifc: spi@fd000400 {
94 			compatible = "amlogic,a1-spifc";
95 			reg = <0x0 0xfd000400 0x0 0x290>;
96 			clocks = <&clkc_periphs CLKID_SPIFC>;
97 			#address-cells = <1>;
98 			#size-cells = <0>;
99 			power-domains = <&pwrc PWRC_SPIFC_ID>;
100 			status = "disabled";
101 		};
102 
103 		apb: bus@fe000000 {
104 			compatible = "simple-bus";
105 			reg = <0x0 0xfe000000 0x0 0x1000000>;
106 			#address-cells = <2>;
107 			#size-cells = <2>;
108 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
109 
110 			reset: reset-controller@0 {
111 				compatible = "amlogic,meson-a1-reset";
112 				reg = <0x0 0x0 0x0 0x8c>;
113 				#reset-cells = <1>;
114 			};
115 
116 			periphs_pinctrl: pinctrl@400 {
117 				compatible = "amlogic,meson-a1-periphs-pinctrl";
118 				#address-cells = <2>;
119 				#size-cells = <2>;
120 				ranges;
121 
122 				gpio: bank@400 {
123 					reg = <0x0 0x0400 0x0 0x003c>,
124 					      <0x0 0x0480 0x0 0x0118>;
125 					reg-names = "mux", "gpio";
126 					gpio-controller;
127 					#gpio-cells = <2>;
128 					gpio-ranges = <&periphs_pinctrl 0 0 62>;
129 				};
130 
131 				i2c0_f11_pins: i2c0-f11 {
132 					mux {
133 						groups = "i2c0_sck_f11",
134 							 "i2c0_sda_f12";
135 						function = "i2c0";
136 						bias-pull-up;
137 						drive-strength-microamp = <3000>;
138 					};
139 				};
140 
141 				i2c0_f9_pins: i2c0-f9 {
142 					mux {
143 						groups = "i2c0_sck_f9",
144 							 "i2c0_sda_f10";
145 						function = "i2c0";
146 						bias-pull-up;
147 						drive-strength-microamp = <3000>;
148 					};
149 				};
150 
151 				i2c1_x_pins: i2c1-x {
152 					mux {
153 						groups = "i2c1_sck_x",
154 							 "i2c1_sda_x";
155 						function = "i2c1";
156 						bias-pull-up;
157 						drive-strength-microamp = <3000>;
158 					};
159 				};
160 
161 				i2c1_a_pins: i2c1-a {
162 					mux {
163 						groups = "i2c1_sck_a",
164 							 "i2c1_sda_a";
165 						function = "i2c1";
166 						bias-pull-up;
167 						drive-strength-microamp = <3000>;
168 					};
169 				};
170 
171 				i2c2_x0_pins: i2c2-x0 {
172 					mux {
173 						groups = "i2c2_sck_x0",
174 							 "i2c2_sda_x1";
175 						function = "i2c2";
176 						bias-pull-up;
177 						drive-strength-microamp = <3000>;
178 					};
179 				};
180 
181 				i2c2_x15_pins: i2c2-x15 {
182 					mux {
183 						groups = "i2c2_sck_x15",
184 							 "i2c2_sda_x16";
185 						function = "i2c2";
186 						bias-pull-up;
187 						drive-strength-microamp = <3000>;
188 					};
189 				};
190 
191 				i2c2_a4_pins: i2c2-a4 {
192 					mux {
193 						groups = "i2c2_sck_a4",
194 							 "i2c2_sda_a5";
195 						function = "i2c2";
196 						bias-pull-up;
197 						drive-strength-microamp = <3000>;
198 					};
199 				};
200 
201 				i2c2_a8_pins: i2c2-a8 {
202 					mux {
203 						groups = "i2c2_sck_a8",
204 							 "i2c2_sda_a9";
205 						function = "i2c2";
206 						bias-pull-up;
207 						drive-strength-microamp = <3000>;
208 					};
209 				};
210 
211 				i2c3_x_pins: i2c3-x {
212 					mux {
213 						groups = "i2c3_sck_x",
214 							 "i2c3_sda_x";
215 						function = "i2c3";
216 						bias-pull-up;
217 						drive-strength-microamp = <3000>;
218 					};
219 				};
220 
221 				i2c3_f_pins: i2c3-f {
222 					mux {
223 						groups = "i2c3_sck_f",
224 							 "i2c3_sda_f";
225 						function = "i2c3";
226 						bias-pull-up;
227 						drive-strength-microamp = <3000>;
228 					};
229 				};
230 
231 				uart_a_pins: uart-a {
232 					mux {
233 						groups = "uart_a_tx",
234 							 "uart_a_rx";
235 						function = "uart_a";
236 					};
237 				};
238 
239 				uart_a_cts_rts_pins: uart-a-cts-rts {
240 					mux {
241 						groups = "uart_a_cts",
242 							 "uart_a_rts";
243 						function = "uart_a";
244 						bias-pull-down;
245 					};
246 				};
247 
248 				sdio_pins: sdio {
249 					mux0 {
250 						groups = "sdcard_d0_x",
251 							 "sdcard_d1_x",
252 							 "sdcard_d2_x",
253 							 "sdcard_d3_x",
254 							 "sdcard_cmd_x";
255 						function = "sdcard";
256 						bias-pull-up;
257 					};
258 
259 					mux1 {
260 						groups = "sdcard_clk_x";
261 						function = "sdcard";
262 						bias-disable;
263 					};
264 				};
265 
266 				sdio_clk_gate_pins: sdio-clk-gate {
267 					mux {
268 						groups = "sdcard_clk_x";
269 						function = "sdcard";
270 						bias-pull-down;
271 					};
272 				};
273 
274 				spifc_pins: spifc {
275 					mux {
276 						groups = "spif_mo",
277 							 "spif_mi",
278 							 "spif_clk",
279 							 "spif_cs",
280 							 "spif_hold_n",
281 							 "spif_wp_n";
282 						function = "spif";
283 					};
284 				};
285 			};
286 
287 			gpio_intc: interrupt-controller@440 {
288 				compatible = "amlogic,meson-a1-gpio-intc",
289 					     "amlogic,meson-gpio-intc";
290 				reg = <0x0 0x0440 0x0 0x14>;
291 				interrupt-controller;
292 				#interrupt-cells = <2>;
293 				amlogic,channel-interrupts =
294 					<49 50 51 52 53 54 55 56>;
295 			};
296 
297 			clkc_periphs: clock-controller@800 {
298 				compatible = "amlogic,a1-peripherals-clkc";
299 				reg = <0 0x800 0 0x104>;
300 				#clock-cells = <1>;
301 				clocks = <&clkc_pll CLKID_FCLK_DIV2>,
302 					 <&clkc_pll CLKID_FCLK_DIV3>,
303 					 <&clkc_pll CLKID_FCLK_DIV5>,
304 					 <&clkc_pll CLKID_FCLK_DIV7>,
305 					 <&clkc_pll CLKID_HIFI_PLL>,
306 					 <&xtal>;
307 				clock-names = "fclk_div2", "fclk_div3",
308 					      "fclk_div5", "fclk_div7",
309 					      "hifi_pll", "xtal";
310 			};
311 
312 			i2c0: i2c@1400 {
313 				compatible = "amlogic,meson-axg-i2c";
314 				status = "disabled";
315 				reg = <0x0 0x1400 0x0 0x20>;
316 				interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
317 				#address-cells = <1>;
318 				#size-cells = <0>;
319 				clocks = <&clkc_periphs CLKID_I2C_M_A>;
320 				power-domains = <&pwrc PWRC_I2C_ID>;
321 			};
322 
323 			uart_AO: serial@1c00 {
324 				compatible = "amlogic,meson-a1-uart",
325 					     "amlogic,meson-ao-uart";
326 				reg = <0x0 0x1c00 0x0 0x18>;
327 				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
328 				clocks = <&xtal>, <&xtal>, <&xtal>;
329 				clock-names = "xtal", "pclk", "baud";
330 				status = "disabled";
331 			};
332 
333 			uart_AO_B: serial@2000 {
334 				compatible = "amlogic,meson-a1-uart",
335 					     "amlogic,meson-ao-uart";
336 				reg = <0x0 0x2000 0x0 0x18>;
337 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
338 				clocks = <&xtal>, <&xtal>, <&xtal>;
339 				clock-names = "xtal", "pclk", "baud";
340 				status = "disabled";
341 			};
342 
343 			saradc: adc@2c00 {
344 				compatible = "amlogic,meson-g12a-saradc",
345 					"amlogic,meson-saradc";
346 				reg = <0x0 0x2c00 0x0 0x48>;
347 				#io-channel-cells = <1>;
348 				power-domains = <&pwrc PWRC_I2C_ID>;
349 				interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
350 				clocks = <&xtal>,
351 					<&clkc_periphs CLKID_SARADC_EN>,
352 					<&clkc_periphs CLKID_SARADC>,
353 					<&clkc_periphs CLKID_SARADC_SEL>;
354 				clock-names = "clkin", "core",
355 					"adc_clk", "adc_sel";
356 				status = "disabled";
357 			};
358 
359 			i2c1: i2c@5c00 {
360 				compatible = "amlogic,meson-axg-i2c";
361 				status = "disabled";
362 				reg = <0x0 0x5c00 0x0 0x20>;
363 				interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
364 				#address-cells = <1>;
365 				#size-cells = <0>;
366 				clocks = <&clkc_periphs CLKID_I2C_M_B>;
367 				power-domains = <&pwrc PWRC_I2C_ID>;
368 			};
369 
370 			i2c2: i2c@6800 {
371 				compatible = "amlogic,meson-axg-i2c";
372 				status = "disabled";
373 				reg = <0x0 0x6800 0x0 0x20>;
374 				interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
375 				#address-cells = <1>;
376 				#size-cells = <0>;
377 				clocks = <&clkc_periphs CLKID_I2C_M_C>;
378 				power-domains = <&pwrc PWRC_I2C_ID>;
379 			};
380 
381 			i2c3: i2c@6c00 {
382 				compatible = "amlogic,meson-axg-i2c";
383 				status = "disabled";
384 				reg = <0x0 0x6c00 0x0 0x20>;
385 				interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
386 				#address-cells = <1>;
387 				#size-cells = <0>;
388 				clocks = <&clkc_periphs CLKID_I2C_M_D>;
389 				power-domains = <&pwrc PWRC_I2C_ID>;
390 			};
391 
392 			usb2_phy1: phy@4000 {
393 				compatible = "amlogic,a1-usb2-phy";
394 				clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
395 				clock-names = "xtal";
396 				reg = <0x0 0x4000 0x0 0x60>;
397 				resets = <&reset RESET_USBPHY>;
398 				reset-names = "phy";
399 				#phy-cells = <0>;
400 				power-domains = <&pwrc PWRC_USB_ID>;
401 			};
402 
403 			cpu_temp: temperature-sensor@4c00 {
404 				compatible = "amlogic,a1-cpu-thermal";
405 				reg = <0x0 0x4c00 0x0 0x50>;
406 				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
407 				clocks = <&clkc_periphs CLKID_TS>;
408 				assigned-clocks = <&clkc_periphs CLKID_TS>;
409 				assigned-clock-rates = <500000>;
410 				#thermal-sensor-cells = <0>;
411 				amlogic,ao-secure = <&sec_AO>;
412 			};
413 
414 			hwrng: rng@5118 {
415 				compatible = "amlogic,meson-rng";
416 				reg = <0x0 0x5118 0x0 0x4>;
417 				power-domains = <&pwrc PWRC_OTP_ID>;
418 			};
419 
420 			sec_AO: ao-secure@5a20 {
421 				compatible = "amlogic,meson-gx-ao-secure", "syscon";
422 				reg = <0x0 0x5a20 0x0 0x140>;
423 				amlogic,has-chip-id;
424 			};
425 
426 			clkc_pll: pll-clock-controller@7c80 {
427 				compatible = "amlogic,a1-pll-clkc";
428 				reg = <0 0x7c80 0 0x18c>;
429 				#clock-cells = <1>;
430 				clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
431 					 <&clkc_periphs CLKID_HIFIPLL_IN>;
432 				clock-names = "fixpll_in", "hifipll_in";
433 			};
434 
435 			sd_emmc: mmc@10000 {
436 				compatible = "amlogic,meson-axg-mmc";
437 				reg = <0x0 0x10000 0x0 0x800>;
438 				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
439 				clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
440 					 <&clkc_periphs CLKID_SD_EMMC>,
441 					 <&clkc_pll CLKID_FCLK_DIV2>;
442 				clock-names = "core",
443 					      "clkin0",
444 					      "clkin1";
445 				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
446 				assigned-clock-parents = <&xtal>;
447 				resets = <&reset RESET_SD_EMMC_A>;
448 				power-domains = <&pwrc PWRC_SD_EMMC_ID>;
449 				status = "disabled";
450 			};
451 		};
452 
453 		usb: usb@fe004400 {
454 			status = "disabled";
455 			compatible = "amlogic,meson-a1-usb-ctrl";
456 			reg = <0x0 0xfe004400 0x0 0xa0>;
457 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
458 			#address-cells = <2>;
459 			#size-cells = <2>;
460 			ranges;
461 
462 			clocks = <&clkc_periphs CLKID_USB_CTRL>,
463 				 <&clkc_periphs CLKID_USB_BUS>,
464 				 <&clkc_periphs CLKID_USB_CTRL_IN>;
465 			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
466 			assigned-clocks = <&clkc_periphs CLKID_USB_BUS>;
467 			assigned-clock-rates = <64000000>;
468 			resets = <&reset RESET_USBCTRL>;
469 
470 			dr_mode = "otg";
471 
472 			phys = <&usb2_phy1>;
473 			phy-names = "usb2-phy1";
474 
475 			dwc3: usb@ff400000 {
476 				compatible = "snps,dwc3";
477 				reg = <0x0 0xff400000 0x0 0x100000>;
478 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
479 				dr_mode = "host";
480 				snps,dis_u2_susphy_quirk;
481 				snps,quirk-frame-length-adjustment = <0x20>;
482 				snps,parkmode-disable-ss-quirk;
483 			};
484 
485 			dwc2: usb@ff500000 {
486 				compatible = "amlogic,meson-a1-usb", "snps,dwc2";
487 				reg = <0x0 0xff500000 0x0 0x40000>;
488 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
489 				phys = <&usb2_phy1>;
490 				phy-names = "usb2-phy";
491 				clocks = <&clkc_periphs CLKID_USB_PHY>;
492 				clock-names = "otg";
493 				dr_mode = "peripheral";
494 				g-rx-fifo-size = <192>;
495 				g-np-tx-fifo-size = <128>;
496 				g-tx-fifo-size = <128 128 16 16 16>;
497 			};
498 		};
499 
500 		gic: interrupt-controller@ff901000 {
501 			compatible = "arm,gic-400";
502 			reg = <0x0 0xff901000 0x0 0x1000>,
503 			      <0x0 0xff902000 0x0 0x2000>,
504 			      <0x0 0xff904000 0x0 0x2000>,
505 			      <0x0 0xff906000 0x0 0x2000>;
506 			interrupt-controller;
507 			interrupts = <GIC_PPI 9
508 				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
509 			#interrupt-cells = <3>;
510 			#address-cells = <0>;
511 		};
512 	};
513 
514 	timer {
515 		compatible = "arm,armv8-timer";
516 		interrupts = <GIC_PPI 13
517 			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
518 			     <GIC_PPI 14
519 			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
520 			     <GIC_PPI 11
521 			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
522 			     <GIC_PPI 10
523 			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
524 	};
525 
526 	xtal: xtal-clk {
527 		compatible = "fixed-clock";
528 		clock-frequency = <24000000>;
529 		clock-output-names = "xtal";
530 		#clock-cells = <0>;
531 	};
532 };
533