1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2011 - 2014 Xilinx 4 */ 5 6 / { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 compatible = "arm,cortex-a9"; 17 device_type = "cpu"; 18 reg = <0>; 19 clocks = <&clkc 3>; 20 clock-latency = <1000>; 21 cpu0-supply = <®ulator_vccpint>; 22 operating-points = < 23 /* kHz uV */ 24 666667 1000000 25 333334 1000000 26 >; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <1>; 33 clocks = <&clkc 3>; 34 }; 35 }; 36 37 fpga_full: fpga-full { 38 compatible = "fpga-region"; 39 fpga-mgr = <&devcfg>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges; 43 }; 44 45 pmu@f8891000 { 46 compatible = "arm,cortex-a9-pmu"; 47 interrupts = <0 5 4>, <0 6 4>; 48 interrupt-parent = <&intc>; 49 reg = <0xf8891000 0x1000>, 50 <0xf8893000 0x1000>; 51 }; 52 53 regulator_vccpint: fixedregulator { 54 compatible = "regulator-fixed"; 55 regulator-name = "VCCPINT"; 56 regulator-min-microvolt = <1000000>; 57 regulator-max-microvolt = <1000000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 replicator { 63 compatible = "arm,coresight-static-replicator"; 64 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 65 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 66 67 out-ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 /* replicator output ports */ 72 port@0 { 73 reg = <0>; 74 replicator_out_port0: endpoint { 75 remote-endpoint = <&tpiu_in_port>; 76 }; 77 }; 78 port@1 { 79 reg = <1>; 80 replicator_out_port1: endpoint { 81 remote-endpoint = <&etb_in_port>; 82 }; 83 }; 84 }; 85 in-ports { 86 /* replicator input port */ 87 port { 88 replicator_in_port0: endpoint { 89 remote-endpoint = <&funnel_out_port>; 90 }; 91 }; 92 }; 93 }; 94 95 amba: axi { 96 compatible = "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 interrupt-parent = <&intc>; 100 ranges; 101 102 adc: adc@f8007100 { 103 compatible = "xlnx,zynq-xadc-1.00.a"; 104 reg = <0xf8007100 0x20>; 105 interrupts = <0 7 4>; 106 interrupt-parent = <&intc>; 107 clocks = <&clkc 12>; 108 }; 109 110 can0: can@e0008000 { 111 compatible = "xlnx,zynq-can-1.0"; 112 status = "disabled"; 113 clocks = <&clkc 19>, <&clkc 36>; 114 clock-names = "can_clk", "pclk"; 115 reg = <0xe0008000 0x1000>; 116 interrupts = <0 28 4>; 117 interrupt-parent = <&intc>; 118 tx-fifo-depth = <0x40>; 119 rx-fifo-depth = <0x40>; 120 }; 121 122 can1: can@e0009000 { 123 compatible = "xlnx,zynq-can-1.0"; 124 status = "disabled"; 125 clocks = <&clkc 20>, <&clkc 37>; 126 clock-names = "can_clk", "pclk"; 127 reg = <0xe0009000 0x1000>; 128 interrupts = <0 51 4>; 129 interrupt-parent = <&intc>; 130 tx-fifo-depth = <0x40>; 131 rx-fifo-depth = <0x40>; 132 }; 133 134 gpio0: gpio@e000a000 { 135 compatible = "xlnx,zynq-gpio-1.0"; 136 #gpio-cells = <2>; 137 clocks = <&clkc 42>; 138 gpio-controller; 139 interrupt-controller; 140 #interrupt-cells = <2>; 141 interrupt-parent = <&intc>; 142 interrupts = <0 20 4>; 143 reg = <0xe000a000 0x1000>; 144 }; 145 146 i2c0: i2c@e0004000 { 147 compatible = "cdns,i2c-r1p10"; 148 status = "disabled"; 149 clocks = <&clkc 38>; 150 interrupt-parent = <&intc>; 151 interrupts = <0 25 4>; 152 clock-frequency = <400000>; 153 reg = <0xe0004000 0x1000>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 }; 157 158 i2c1: i2c@e0005000 { 159 compatible = "cdns,i2c-r1p10"; 160 status = "disabled"; 161 clocks = <&clkc 39>; 162 interrupt-parent = <&intc>; 163 interrupts = <0 48 4>; 164 clock-frequency = <400000>; 165 reg = <0xe0005000 0x1000>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 }; 169 170 intc: interrupt-controller@f8f01000 { 171 compatible = "arm,cortex-a9-gic"; 172 #interrupt-cells = <3>; 173 interrupt-controller; 174 reg = <0xF8F01000 0x1000>, 175 <0xF8F00100 0x100>; 176 }; 177 178 L2: cache-controller@f8f02000 { 179 compatible = "arm,pl310-cache"; 180 reg = <0xF8F02000 0x1000>; 181 interrupts = <0 2 4>; 182 arm,data-latency = <3 2 2>; 183 arm,tag-latency = <2 2 2>; 184 cache-unified; 185 cache-level = <2>; 186 }; 187 188 mc: memory-controller@f8006000 { 189 compatible = "xlnx,zynq-ddrc-a05"; 190 reg = <0xf8006000 0x1000>; 191 }; 192 193 uart0: serial@e0000000 { 194 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 195 status = "disabled"; 196 clocks = <&clkc 23>, <&clkc 40>; 197 clock-names = "uart_clk", "pclk"; 198 reg = <0xE0000000 0x1000>; 199 interrupts = <0 27 4>; 200 }; 201 202 uart1: serial@e0001000 { 203 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 204 status = "disabled"; 205 clocks = <&clkc 24>, <&clkc 41>; 206 clock-names = "uart_clk", "pclk"; 207 reg = <0xE0001000 0x1000>; 208 interrupts = <0 50 4>; 209 }; 210 211 spi0: spi@e0006000 { 212 compatible = "xlnx,zynq-spi-r1p6"; 213 reg = <0xe0006000 0x1000>; 214 status = "disabled"; 215 interrupt-parent = <&intc>; 216 interrupts = <0 26 4>; 217 clocks = <&clkc 25>, <&clkc 34>; 218 clock-names = "ref_clk", "pclk"; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 }; 222 223 spi1: spi@e0007000 { 224 compatible = "xlnx,zynq-spi-r1p6"; 225 reg = <0xe0007000 0x1000>; 226 status = "disabled"; 227 interrupt-parent = <&intc>; 228 interrupts = <0 49 4>; 229 clocks = <&clkc 26>, <&clkc 35>; 230 clock-names = "ref_clk", "pclk"; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 235 qspi: spi@e000d000 { 236 compatible = "xlnx,zynq-qspi-1.0"; 237 reg = <0xe000d000 0x1000>; 238 interrupt-parent = <&intc>; 239 interrupts = <0 19 4>; 240 clocks = <&clkc 10>, <&clkc 43>; 241 clock-names = "ref_clk", "pclk"; 242 status = "disabled"; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 }; 246 247 gem0: ethernet@e000b000 { 248 compatible = "xlnx,zynq-gem", "cdns,gem"; 249 reg = <0xe000b000 0x1000>; 250 status = "disabled"; 251 interrupts = <0 22 4>; 252 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 253 clock-names = "pclk", "hclk", "tx_clk"; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 }; 257 258 gem1: ethernet@e000c000 { 259 compatible = "xlnx,zynq-gem", "cdns,gem"; 260 reg = <0xe000c000 0x1000>; 261 status = "disabled"; 262 interrupts = <0 45 4>; 263 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 264 clock-names = "pclk", "hclk", "tx_clk"; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 smcc: memory-controller@e000e000 { 270 compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 271 reg = <0xe000e000 0x0001000>; 272 status = "disabled"; 273 clock-names = "memclk", "apb_pclk"; 274 clocks = <&clkc 11>, <&clkc 44>; 275 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 276 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 277 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 278 #address-cells = <2>; 279 #size-cells = <1>; 280 281 nfc0: nand-controller@0,0 { 282 compatible = "arm,pl353-nand-r2p1"; 283 reg = <0 0 0x1000000>; 284 status = "disabled"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 }; 288 }; 289 290 sdhci0: mmc@e0100000 { 291 compatible = "arasan,sdhci-8.9a"; 292 status = "disabled"; 293 clock-names = "clk_xin", "clk_ahb"; 294 clocks = <&clkc 21>, <&clkc 32>; 295 interrupt-parent = <&intc>; 296 interrupts = <0 24 4>; 297 reg = <0xe0100000 0x1000>; 298 }; 299 300 sdhci1: mmc@e0101000 { 301 compatible = "arasan,sdhci-8.9a"; 302 status = "disabled"; 303 clock-names = "clk_xin", "clk_ahb"; 304 clocks = <&clkc 22>, <&clkc 33>; 305 interrupt-parent = <&intc>; 306 interrupts = <0 47 4>; 307 reg = <0xe0101000 0x1000>; 308 }; 309 310 slcr: slcr@f8000000 { 311 #address-cells = <1>; 312 #size-cells = <1>; 313 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 314 reg = <0xF8000000 0x1000>; 315 ranges; 316 clkc: clkc@100 { 317 #clock-cells = <1>; 318 compatible = "xlnx,ps7-clkc"; 319 fclk-enable = <0>; 320 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 321 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 322 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 323 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 324 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 325 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 326 "gem1_aper", "sdio0_aper", "sdio1_aper", 327 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 328 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 329 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 330 "dbg_trc", "dbg_apb"; 331 reg = <0x100 0x100>; 332 }; 333 334 rstc: rstc@200 { 335 compatible = "xlnx,zynq-reset"; 336 reg = <0x200 0x48>; 337 #reset-cells = <1>; 338 syscon = <&slcr>; 339 }; 340 341 pinctrl0: pinctrl@700 { 342 compatible = "xlnx,pinctrl-zynq"; 343 reg = <0x700 0x200>; 344 syscon = <&slcr>; 345 }; 346 }; 347 348 dmac_s: dma-controller@f8003000 { 349 compatible = "arm,pl330", "arm,primecell"; 350 reg = <0xf8003000 0x1000>; 351 interrupt-parent = <&intc>; 352 /* 353 * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 354 * "dma4", "dma5", "dma6", "dma7"; 355 */ 356 interrupts = <0 13 4>, 357 <0 14 4>, <0 15 4>, 358 <0 16 4>, <0 17 4>, 359 <0 40 4>, <0 41 4>, 360 <0 42 4>, <0 43 4>; 361 #dma-cells = <1>; 362 clocks = <&clkc 27>; 363 clock-names = "apb_pclk"; 364 }; 365 366 devcfg: devcfg@f8007000 { 367 compatible = "xlnx,zynq-devcfg-1.0"; 368 reg = <0xf8007000 0x100>; 369 interrupt-parent = <&intc>; 370 interrupts = <0 8 4>; 371 clocks = <&clkc 12>; 372 clock-names = "ref_clk"; 373 syscon = <&slcr>; 374 }; 375 376 global_timer: timer@f8f00200 { 377 compatible = "arm,cortex-a9-global-timer"; 378 reg = <0xf8f00200 0x20>; 379 interrupts = <1 11 0x301>; 380 interrupt-parent = <&intc>; 381 clocks = <&clkc 4>; 382 }; 383 384 ttc0: timer@f8001000 { 385 interrupt-parent = <&intc>; 386 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 387 compatible = "cdns,ttc"; 388 clocks = <&clkc 6>; 389 reg = <0xF8001000 0x1000>; 390 }; 391 392 ttc1: timer@f8002000 { 393 interrupt-parent = <&intc>; 394 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 395 compatible = "cdns,ttc"; 396 clocks = <&clkc 6>; 397 reg = <0xF8002000 0x1000>; 398 }; 399 400 scutimer: timer@f8f00600 { 401 interrupt-parent = <&intc>; 402 interrupts = <1 13 0x301>; 403 compatible = "arm,cortex-a9-twd-timer"; 404 reg = <0xf8f00600 0x20>; 405 clocks = <&clkc 4>; 406 }; 407 408 usb0: usb@e0002000 { 409 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 410 status = "disabled"; 411 clocks = <&clkc 28>; 412 interrupt-parent = <&intc>; 413 interrupts = <0 21 4>; 414 reg = <0xe0002000 0x1000>; 415 phy_type = "ulpi"; 416 }; 417 418 usb1: usb@e0003000 { 419 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 420 status = "disabled"; 421 clocks = <&clkc 29>; 422 interrupt-parent = <&intc>; 423 interrupts = <0 44 4>; 424 reg = <0xe0003000 0x1000>; 425 phy_type = "ulpi"; 426 }; 427 428 watchdog0: watchdog@f8005000 { 429 clocks = <&clkc 45>; 430 compatible = "cdns,wdt-r1p2"; 431 interrupt-parent = <&intc>; 432 interrupts = <0 9 1>; 433 reg = <0xf8005000 0x1000>; 434 timeout-sec = <10>; 435 }; 436 437 etb@f8801000 { 438 compatible = "arm,coresight-etb10", "arm,primecell"; 439 reg = <0xf8801000 0x1000>; 440 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 441 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 442 in-ports { 443 port { 444 etb_in_port: endpoint { 445 remote-endpoint = <&replicator_out_port1>; 446 }; 447 }; 448 }; 449 }; 450 451 tpiu@f8803000 { 452 compatible = "arm,coresight-tpiu", "arm,primecell"; 453 reg = <0xf8803000 0x1000>; 454 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 455 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 456 in-ports { 457 port { 458 tpiu_in_port: endpoint { 459 remote-endpoint = <&replicator_out_port0>; 460 }; 461 }; 462 }; 463 }; 464 465 funnel@f8804000 { 466 compatible = "arm,coresight-static-funnel", "arm,primecell"; 467 reg = <0xf8804000 0x1000>; 468 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 469 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 470 471 /* funnel output ports */ 472 out-ports { 473 port { 474 funnel_out_port: endpoint { 475 remote-endpoint = 476 <&replicator_in_port0>; 477 }; 478 }; 479 }; 480 481 in-ports { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 /* funnel input ports */ 486 port@0 { 487 reg = <0>; 488 funnel0_in_port0: endpoint { 489 remote-endpoint = <&ptm0_out_port>; 490 }; 491 }; 492 493 port@1 { 494 reg = <1>; 495 funnel0_in_port1: endpoint { 496 remote-endpoint = <&ptm1_out_port>; 497 }; 498 }; 499 500 port@2 { 501 reg = <2>; 502 funnel0_in_port2: endpoint { 503 }; 504 }; 505 /* The other input ports are not connect to anything */ 506 }; 507 }; 508 509 ptm@f889c000 { 510 compatible = "arm,coresight-etm3x", "arm,primecell"; 511 reg = <0xf889c000 0x1000>; 512 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 513 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 514 cpu = <&cpu0>; 515 out-ports { 516 port { 517 ptm0_out_port: endpoint { 518 remote-endpoint = <&funnel0_in_port0>; 519 }; 520 }; 521 }; 522 }; 523 524 ptm@f889d000 { 525 compatible = "arm,coresight-etm3x", "arm,primecell"; 526 reg = <0xf889d000 0x1000>; 527 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 528 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 529 cpu = <&cpu1>; 530 out-ports { 531 port { 532 ptm1_out_port: endpoint { 533 remote-endpoint = <&funnel0_in_port1>; 534 }; 535 }; 536 }; 537 }; 538 }; 539 }; 540