1 /*
2  * Support for CompuLab CL-SOM-iMX7 System-on-Module
3  *
4  * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
5  * Author: Ilya Ledvich <ilya@compulab.co.il>
6  *
7  * This file is dual-licensed: you can use it either under the terms
8  * of the GPL or the X11 license, at your option. Note that this dual
9  * licensing only applies to this file, and not this project as a
10  * whole.
11  */
12 
13 /dts-v1/;
14 
15 #include "imx7d.dtsi"
16 
17 / {
18 	model = "CompuLab CL-SOM-iMX7";
19 	compatible = "compulab,cl-som-imx7", "fsl,imx7d";
20 
21 	memory@80000000 {
22 		device_type = "memory";
23 		reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
24 	};
25 
26 	reg_usb_otg1_vbus: regulator-vbus {
27 		compatible = "regulator-fixed";
28 		regulator-name = "usb_otg1_vbus";
29 		regulator-min-microvolt = <5000000>;
30 		regulator-max-microvolt = <5000000>;
31 		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
32 		enable-active-high;
33 	};
34 };
35 
36 &cpu0 {
37 	cpu-supply = <&sw1a_reg>;
38 };
39 
40 &cpu1 {
41 	cpu-supply = <&sw1a_reg>;
42 };
43 
44 &fec1 {
45 	pinctrl-names = "default";
46 	pinctrl-0 = <&pinctrl_enet1>;
47 	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
48 			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
49 	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 	assigned-clock-rates = <0>, <100000000>;
51 	phy-mode = "rgmii-id";
52 	phy-handle = <&ethphy0>;
53 	fsl,magic-packet;
54 	status = "okay";
55 
56 	mdio {
57 		#address-cells = <1>;
58 		#size-cells = <0>;
59 
60 		ethphy0: ethernet-phy@0 {
61 			compatible = "ethernet-phy-ieee802.3-c22";
62 			reg = <0>;
63 		};
64 
65 		ethphy1: ethernet-phy@1 {
66 			compatible = "ethernet-phy-ieee802.3-c22";
67 			reg = <1>;
68 		};
69 	};
70 };
71 
72 &fec2 {
73 	pinctrl-names = "default";
74 	pinctrl-0 = <&pinctrl_enet2>;
75 	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
76 			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
77 	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 	assigned-clock-rates = <0>, <100000000>;
79 	phy-mode = "rgmii-id";
80 	phy-handle = <&ethphy1>;
81 	fsl,magic-packet;
82 	status = "okay";
83 };
84 
85 &i2c2 {
86 	pinctrl-names = "default";
87 	pinctrl-0 = <&pinctrl_i2c2>;
88 	status = "okay";
89 
90 	pmic: pmic@8 {
91 		compatible = "fsl,pfuze3000";
92 		reg = <0x8>;
93 
94 		regulators {
95 			sw1a_reg: sw1a {
96 				regulator-min-microvolt = <700000>;
97 				regulator-max-microvolt = <3300000>;
98 				regulator-boot-on;
99 				regulator-always-on;
100 				regulator-ramp-delay = <6250>;
101 			};
102 
103 			/* use sw1c_reg to align with pfuze100/pfuze200 */
104 			sw1c_reg: sw1b {
105 				regulator-min-microvolt = <700000>;
106 				regulator-max-microvolt = <1475000>;
107 				regulator-boot-on;
108 				regulator-always-on;
109 				regulator-ramp-delay = <6250>;
110 			};
111 
112 			sw2_reg: sw2 {
113 				regulator-min-microvolt = <1500000>;
114 				regulator-max-microvolt = <1850000>;
115 				regulator-boot-on;
116 				regulator-always-on;
117 			};
118 
119 			sw3a_reg: sw3 {
120 				regulator-min-microvolt = <900000>;
121 				regulator-max-microvolt = <1650000>;
122 				regulator-boot-on;
123 				regulator-always-on;
124 			};
125 
126 			swbst_reg: swbst {
127 				regulator-min-microvolt = <5000000>;
128 				regulator-max-microvolt = <5150000>;
129 			};
130 
131 			snvs_reg: vsnvs {
132 				regulator-min-microvolt = <1000000>;
133 				regulator-max-microvolt = <3000000>;
134 				regulator-boot-on;
135 				regulator-always-on;
136 			};
137 
138 			vref_reg: vrefddr {
139 				regulator-boot-on;
140 				regulator-always-on;
141 			};
142 
143 			vgen1_reg: vldo1 {
144 				regulator-min-microvolt = <1800000>;
145 				regulator-max-microvolt = <3300000>;
146 				regulator-always-on;
147 			};
148 
149 			vgen2_reg: vldo2 {
150 				regulator-min-microvolt = <800000>;
151 				regulator-max-microvolt = <1550000>;
152 			};
153 
154 			vgen3_reg: vccsd {
155 				regulator-min-microvolt = <2850000>;
156 				regulator-max-microvolt = <3300000>;
157 				regulator-always-on;
158 			};
159 
160 			vgen4_reg: v33 {
161 				regulator-min-microvolt = <2850000>;
162 				regulator-max-microvolt = <3300000>;
163 				regulator-always-on;
164 			};
165 
166 			vgen5_reg: vldo3 {
167 				regulator-min-microvolt = <1800000>;
168 				regulator-max-microvolt = <3300000>;
169 				regulator-always-on;
170 			};
171 
172 			vgen6_reg: vldo4 {
173 				regulator-min-microvolt = <1800000>;
174 				regulator-max-microvolt = <3300000>;
175 				regulator-always-on;
176 			};
177 		};
178 	};
179 
180 	pca9555: pca9555@20 {
181 		compatible = "nxp,pca9555";
182 		gpio-controller;
183 		#gpio-cells = <2>;
184 		reg = <0x20>;
185 	};
186 
187 	eeprom@50 {
188 		compatible = "atmel,24c08";
189 		reg = <0x50>;
190 		pagesize = <16>;
191 	};
192 };
193 
194 &uart1 {
195 	pinctrl-names = "default";
196 	pinctrl-0 = <&pinctrl_uart1>;
197 	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
199 	status = "okay";
200 };
201 
202 &usbotg1 {
203 	pinctrl-names = "default";
204 	pinctrl-0 = <&pinctrl_usbotg1>;
205 	vbus-supply = <&reg_usb_otg1_vbus>;
206 	status = "okay";
207 };
208 
209 &usdhc3 {
210 	pinctrl-names = "default";
211 	pinctrl-0 = <&pinctrl_usdhc3>;
212 	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 	assigned-clock-rates = <400000000>;
214 	bus-width = <8>;
215 	fsl,tuning-step = <2>;
216 	non-removable;
217 	status = "okay";
218 };
219 
220 &iomuxc {
221 	pinctrl_enet1: enet1grp {
222 		fsl,pins = <
223 			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x30
224 			MX7D_PAD_SD2_WP__ENET1_MDC			0x30
225 			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x11
226 			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x11
227 			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x11
228 			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x11
229 			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x11
230 			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x11
231 			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x11
232 			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x11
233 			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x11
234 			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x11
235 			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x11
236 			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x11
237 		>;
238 	};
239 
240 	pinctrl_enet2: enet2grp {
241 		fsl,pins = <
242 			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x11
243 			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x11
244 			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x11
245 			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x11
246 			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x11
247 			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x11
248 			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x11
249 			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x11
250 			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x11
251 			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x11
252 			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x11
253 			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x11
254 		>;
255 	};
256 
257 	pinctrl_i2c2: i2c2grp {
258 		fsl,pins = <
259 			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
260 			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
261 		>;
262 	};
263 
264 	pinctrl_uart1: uart1grp {
265 		fsl,pins = <
266 			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
267 			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
268 		>;
269 	};
270 
271 	pinctrl_usdhc3: usdhc3grp {
272 		fsl,pins = <
273 			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
274 			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
275 			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
276 			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
277 			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
278 			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
279 			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
280 			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
281 			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
282 			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
283 			MX7D_PAD_SD3_STROBE__SD3_STROBE		0x19
284 		>;
285 	};
286 };
287 
288 &iomuxc_lpsr {
289 	pinctrl_usbotg1: usbotg1grp {
290 		fsl,pins = <
291 			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x14 /* OTG PWREN */
292 		>;
293 	};
294 };
295