1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2012 Sascha Hauer, Pengutronix
4 
5 #include "imx27-pinfunc.h"
6 
7 #include <dt-bindings/clock/imx27-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 
12 / {
13 	#address-cells = <1>;
14 	#size-cells = <1>;
15 	/*
16 	 * The decompressor and also some bootloaders rely on a
17 	 * pre-existing /chosen node to be available to insert the
18 	 * command line and merge other ATAGS info.
19 	 */
20 	chosen {};
21 
22 	aliases {
23 		ethernet0 = &fec;
24 		gpio0 = &gpio1;
25 		gpio1 = &gpio2;
26 		gpio2 = &gpio3;
27 		gpio3 = &gpio4;
28 		gpio4 = &gpio5;
29 		gpio5 = &gpio6;
30 		i2c0 = &i2c1;
31 		i2c1 = &i2c2;
32 		serial0 = &uart1;
33 		serial1 = &uart2;
34 		serial2 = &uart3;
35 		serial3 = &uart4;
36 		serial4 = &uart5;
37 		serial5 = &uart6;
38 		spi0 = &cspi1;
39 		spi1 = &cspi2;
40 		spi2 = &cspi3;
41 	};
42 
43 	aitc: aitc-interrupt-controller@10040000 {
44 		compatible = "fsl,imx27-aitc", "fsl,avic";
45 		interrupt-controller;
46 		#interrupt-cells = <1>;
47 		reg = <0x10040000 0x1000>;
48 	};
49 
50 	clocks {
51 		clk_osc26m: osc26m {
52 			compatible = "fsl,imx-osc26m", "fixed-clock";
53 			#clock-cells = <0>;
54 			clock-frequency = <26000000>;
55 		};
56 	};
57 
58 	cpus {
59 		#size-cells = <0>;
60 		#address-cells = <1>;
61 
62 		cpu: cpu@0 {
63 			device_type = "cpu";
64 			reg = <0>;
65 			compatible = "arm,arm926ej-s";
66 			operating-points = <
67 				/* kHz uV */
68 				266000 1300000
69 				399000 1450000
70 			>;
71 			clock-latency = <62500>;
72 			clocks = <&clks IMX27_CLK_CPU_DIV>;
73 			voltage-tolerance = <5>;
74 		};
75 	};
76 
77 	soc: soc {
78 		#address-cells = <1>;
79 		#size-cells = <1>;
80 		compatible = "simple-bus";
81 		interrupt-parent = <&aitc>;
82 		ranges;
83 
84 		aipi1: bus@10000000 { /* AIPI1 */
85 			compatible = "fsl,aipi-bus", "simple-bus";
86 			#address-cells = <1>;
87 			#size-cells = <1>;
88 			reg = <0x10000000 0x20000>;
89 			ranges;
90 
91 			dma: dma-controller@10001000 {
92 				compatible = "fsl,imx27-dma";
93 				reg = <0x10001000 0x1000>;
94 				interrupts = <32>;
95 				clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
96 					 <&clks IMX27_CLK_DMA_AHB_GATE>;
97 				clock-names = "ipg", "ahb";
98 				#dma-cells = <1>;
99 				dma-channels = <16>;
100 			};
101 
102 			wdog: watchdog@10002000 {
103 				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
104 				reg = <0x10002000 0x1000>;
105 				interrupts = <27>;
106 				clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
107 			};
108 
109 			gpt1: timer@10003000 {
110 				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
111 				reg = <0x10003000 0x1000>;
112 				interrupts = <26>;
113 				clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
114 					 <&clks IMX27_CLK_PER1_GATE>;
115 				clock-names = "ipg", "per";
116 			};
117 
118 			gpt2: timer@10004000 {
119 				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
120 				reg = <0x10004000 0x1000>;
121 				interrupts = <25>;
122 				clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
123 					 <&clks IMX27_CLK_PER1_GATE>;
124 				clock-names = "ipg", "per";
125 			};
126 
127 			gpt3: timer@10005000 {
128 				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
129 				reg = <0x10005000 0x1000>;
130 				interrupts = <24>;
131 				clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
132 					 <&clks IMX27_CLK_PER1_GATE>;
133 				clock-names = "ipg", "per";
134 			};
135 
136 			pwm: pwm@10006000 {
137 				#pwm-cells = <3>;
138 				compatible = "fsl,imx27-pwm";
139 				reg = <0x10006000 0x1000>;
140 				interrupts = <23>;
141 				clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
142 					 <&clks IMX27_CLK_PER1_GATE>;
143 				clock-names = "ipg", "per";
144 			};
145 
146 			rtc: rtc@10007000 {
147 				compatible = "fsl,imx21-rtc";
148 				reg = <0x10007000 0x1000>;
149 				interrupts = <22>;
150 				clocks = <&clks IMX27_CLK_CKIL>,
151 					 <&clks IMX27_CLK_RTC_IPG_GATE>;
152 				clock-names = "ref", "ipg";
153 			};
154 
155 			kpp: kpp@10008000 {
156 				compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
157 				reg = <0x10008000 0x1000>;
158 				interrupts = <21>;
159 				clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
160 				status = "disabled";
161 			};
162 
163 			owire: owire@10009000 {
164 				compatible = "fsl,imx27-owire", "fsl,imx21-owire";
165 				reg = <0x10009000 0x1000>;
166 				clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
167 				status = "disabled";
168 			};
169 
170 			uart1: serial@1000a000 {
171 				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
172 				reg = <0x1000a000 0x1000>;
173 				interrupts = <20>;
174 				clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
175 					 <&clks IMX27_CLK_PER1_GATE>;
176 				clock-names = "ipg", "per";
177 				status = "disabled";
178 			};
179 
180 			uart2: serial@1000b000 {
181 				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
182 				reg = <0x1000b000 0x1000>;
183 				interrupts = <19>;
184 				clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
185 					 <&clks IMX27_CLK_PER1_GATE>;
186 				clock-names = "ipg", "per";
187 				status = "disabled";
188 			};
189 
190 			uart3: serial@1000c000 {
191 				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
192 				reg = <0x1000c000 0x1000>;
193 				interrupts = <18>;
194 				clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
195 					 <&clks IMX27_CLK_PER1_GATE>;
196 				clock-names = "ipg", "per";
197 				status = "disabled";
198 			};
199 
200 			uart4: serial@1000d000 {
201 				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
202 				reg = <0x1000d000 0x1000>;
203 				interrupts = <17>;
204 				clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
205 					 <&clks IMX27_CLK_PER1_GATE>;
206 				clock-names = "ipg", "per";
207 				status = "disabled";
208 			};
209 
210 			cspi1: spi@1000e000 {
211 				#address-cells = <1>;
212 				#size-cells = <0>;
213 				compatible = "fsl,imx27-cspi";
214 				reg = <0x1000e000 0x1000>;
215 				interrupts = <16>;
216 				clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
217 					 <&clks IMX27_CLK_PER2_GATE>;
218 				clock-names = "ipg", "per";
219 				status = "disabled";
220 			};
221 
222 			cspi2: spi@1000f000 {
223 				#address-cells = <1>;
224 				#size-cells = <0>;
225 				compatible = "fsl,imx27-cspi";
226 				reg = <0x1000f000 0x1000>;
227 				interrupts = <15>;
228 				clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
229 					 <&clks IMX27_CLK_PER2_GATE>;
230 				clock-names = "ipg", "per";
231 				status = "disabled";
232 			};
233 
234 			ssi1: ssi@10010000 {
235 				#sound-dai-cells = <0>;
236 				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
237 				reg = <0x10010000 0x1000>;
238 				interrupts = <14>;
239 				clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
240 				dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
241 				dma-names = "rx0", "tx0", "rx1", "tx1";
242 				fsl,fifo-depth = <8>;
243 				status = "disabled";
244 			};
245 
246 			ssi2: ssi@10011000 {
247 				#sound-dai-cells = <0>;
248 				compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
249 				reg = <0x10011000 0x1000>;
250 				interrupts = <13>;
251 				clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
252 				dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
253 				dma-names = "rx0", "tx0", "rx1", "tx1";
254 				fsl,fifo-depth = <8>;
255 				status = "disabled";
256 			};
257 
258 			i2c1: i2c@10012000 {
259 				#address-cells = <1>;
260 				#size-cells = <0>;
261 				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
262 				reg = <0x10012000 0x1000>;
263 				interrupts = <12>;
264 				clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
265 				status = "disabled";
266 			};
267 
268 			sdhci1: mmc@10013000 {
269 				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
270 				reg = <0x10013000 0x1000>;
271 				interrupts = <11>;
272 				clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
273 					 <&clks IMX27_CLK_PER2_GATE>;
274 				clock-names = "ipg", "per";
275 				dmas = <&dma 7>;
276 				dma-names = "rx-tx";
277 				status = "disabled";
278 			};
279 
280 			sdhci2: mmc@10014000 {
281 				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
282 				reg = <0x10014000 0x1000>;
283 				interrupts = <10>;
284 				clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
285 					 <&clks IMX27_CLK_PER2_GATE>;
286 				clock-names = "ipg", "per";
287 				dmas = <&dma 6>;
288 				dma-names = "rx-tx";
289 				status = "disabled";
290 			};
291 
292 			iomuxc: iomuxc@10015000 {
293 				compatible = "fsl,imx27-iomuxc";
294 				reg = <0x10015000 0x600>;
295 				#address-cells = <1>;
296 				#size-cells = <1>;
297 				ranges;
298 
299 				gpio1: gpio@10015000 {
300 					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
301 					reg = <0x10015000 0x100>;
302 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
303 					interrupts = <8>;
304 					gpio-controller;
305 					#gpio-cells = <2>;
306 					interrupt-controller;
307 					#interrupt-cells = <2>;
308 				};
309 
310 				gpio2: gpio@10015100 {
311 					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
312 					reg = <0x10015100 0x100>;
313 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
314 					interrupts = <8>;
315 					gpio-controller;
316 					#gpio-cells = <2>;
317 					interrupt-controller;
318 					#interrupt-cells = <2>;
319 				};
320 
321 				gpio3: gpio@10015200 {
322 					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
323 					reg = <0x10015200 0x100>;
324 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
325 					interrupts = <8>;
326 					gpio-controller;
327 					#gpio-cells = <2>;
328 					interrupt-controller;
329 					#interrupt-cells = <2>;
330 				};
331 
332 				gpio4: gpio@10015300 {
333 					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
334 					reg = <0x10015300 0x100>;
335 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
336 					interrupts = <8>;
337 					gpio-controller;
338 					#gpio-cells = <2>;
339 					interrupt-controller;
340 					#interrupt-cells = <2>;
341 				};
342 
343 				gpio5: gpio@10015400 {
344 					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
345 					reg = <0x10015400 0x100>;
346 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
347 					interrupts = <8>;
348 					gpio-controller;
349 					#gpio-cells = <2>;
350 					interrupt-controller;
351 					#interrupt-cells = <2>;
352 				};
353 
354 				gpio6: gpio@10015500 {
355 					compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
356 					reg = <0x10015500 0x100>;
357 					clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
358 					interrupts = <8>;
359 					gpio-controller;
360 					#gpio-cells = <2>;
361 					interrupt-controller;
362 					#interrupt-cells = <2>;
363 				};
364 			};
365 
366 			audmux: audmux@10016000 {
367 				compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
368 				reg = <0x10016000 0x1000>;
369 				clocks = <&clks IMX27_CLK_DUMMY>;
370 				clock-names = "audmux";
371 				status = "disabled";
372 			};
373 
374 			cspi3: spi@10017000 {
375 				#address-cells = <1>;
376 				#size-cells = <0>;
377 				compatible = "fsl,imx27-cspi";
378 				reg = <0x10017000 0x1000>;
379 				interrupts = <6>;
380 				clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
381 					 <&clks IMX27_CLK_PER2_GATE>;
382 				clock-names = "ipg", "per";
383 				status = "disabled";
384 			};
385 
386 			gpt4: timer@10019000 {
387 				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
388 				reg = <0x10019000 0x1000>;
389 				interrupts = <4>;
390 				clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
391 					 <&clks IMX27_CLK_PER1_GATE>;
392 				clock-names = "ipg", "per";
393 			};
394 
395 			gpt5: timer@1001a000 {
396 				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
397 				reg = <0x1001a000 0x1000>;
398 				interrupts = <3>;
399 				clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
400 					 <&clks IMX27_CLK_PER1_GATE>;
401 				clock-names = "ipg", "per";
402 			};
403 
404 			uart5: serial@1001b000 {
405 				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
406 				reg = <0x1001b000 0x1000>;
407 				interrupts = <49>;
408 				clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
409 					 <&clks IMX27_CLK_PER1_GATE>;
410 				clock-names = "ipg", "per";
411 				status = "disabled";
412 			};
413 
414 			uart6: serial@1001c000 {
415 				compatible = "fsl,imx27-uart", "fsl,imx21-uart";
416 				reg = <0x1001c000 0x1000>;
417 				interrupts = <48>;
418 				clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
419 					 <&clks IMX27_CLK_PER1_GATE>;
420 				clock-names = "ipg", "per";
421 				status = "disabled";
422 			};
423 
424 			i2c2: i2c@1001d000 {
425 				#address-cells = <1>;
426 				#size-cells = <0>;
427 				compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
428 				reg = <0x1001d000 0x1000>;
429 				interrupts = <1>;
430 				clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
431 				status = "disabled";
432 			};
433 
434 			sdhci3: mmc@1001e000 {
435 				compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
436 				reg = <0x1001e000 0x1000>;
437 				interrupts = <9>;
438 				clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
439 					 <&clks IMX27_CLK_PER2_GATE>;
440 				clock-names = "ipg", "per";
441 				dmas = <&dma 36>;
442 				dma-names = "rx-tx";
443 				status = "disabled";
444 			};
445 
446 			gpt6: timer@1001f000 {
447 				compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
448 				reg = <0x1001f000 0x1000>;
449 				interrupts = <2>;
450 				clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
451 					 <&clks IMX27_CLK_PER1_GATE>;
452 				clock-names = "ipg", "per";
453 			};
454 		};
455 
456 		aipi2: bus@10020000 { /* AIPI2 */
457 			compatible = "fsl,aipi-bus", "simple-bus";
458 			#address-cells = <1>;
459 			#size-cells = <1>;
460 			reg = <0x10020000 0x20000>;
461 			ranges;
462 
463 			fb: fb@10021000 {
464 				compatible = "fsl,imx27-fb", "fsl,imx21-fb";
465 				interrupts = <61>;
466 				reg = <0x10021000 0x1000>;
467 				clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
468 					 <&clks IMX27_CLK_LCDC_AHB_GATE>,
469 					 <&clks IMX27_CLK_PER3_GATE>;
470 				clock-names = "ipg", "ahb", "per";
471 				status = "disabled";
472 			};
473 
474 			coda: coda@10023000 {
475 				compatible = "fsl,imx27-vpu", "cnm,codadx6";
476 				reg = <0x10023000 0x0200>;
477 				interrupts = <53>;
478 				clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
479 					 <&clks IMX27_CLK_VPU_AHB_GATE>;
480 				clock-names = "per", "ahb";
481 				iram = <&iram>;
482 			};
483 
484 			usbotg: usb@10024000 {
485 				compatible = "fsl,imx27-usb";
486 				reg = <0x10024000 0x200>;
487 				interrupts = <56>;
488 				clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
489 					<&clks IMX27_CLK_USB_AHB_GATE>,
490 					<&clks IMX27_CLK_USB_DIV>;
491 				clock-names = "ipg", "ahb", "per";
492 				fsl,usbmisc = <&usbmisc 0>;
493 				status = "disabled";
494 			};
495 
496 			usbh1: usb@10024200 {
497 				compatible = "fsl,imx27-usb";
498 				reg = <0x10024200 0x200>;
499 				interrupts = <54>;
500 				clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
501 					<&clks IMX27_CLK_USB_AHB_GATE>,
502 					<&clks IMX27_CLK_USB_DIV>;
503 				clock-names = "ipg", "ahb", "per";
504 				fsl,usbmisc = <&usbmisc 1>;
505 				dr_mode = "host";
506 				status = "disabled";
507 			};
508 
509 			usbh2: usb@10024400 {
510 				compatible = "fsl,imx27-usb";
511 				reg = <0x10024400 0x200>;
512 				interrupts = <55>;
513 				clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
514 					<&clks IMX27_CLK_USB_AHB_GATE>,
515 					<&clks IMX27_CLK_USB_DIV>;
516 				clock-names = "ipg", "ahb", "per";
517 				fsl,usbmisc = <&usbmisc 2>;
518 				dr_mode = "host";
519 				status = "disabled";
520 			};
521 
522 			usbmisc: usbmisc@10024600 {
523 				#index-cells = <1>;
524 				compatible = "fsl,imx27-usbmisc";
525 				reg = <0x10024600 0x200>;
526 			};
527 
528 			sahara2: crypto@10025000 {
529 				compatible = "fsl,imx27-sahara";
530 				reg = <0x10025000 0x1000>;
531 				interrupts = <59>;
532 				clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
533 					 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
534 				clock-names = "ipg", "ahb";
535 			};
536 
537 			clks: ccm@10027000 {
538 				compatible = "fsl,imx27-ccm";
539 				reg = <0x10027000 0x1000>;
540 				#clock-cells = <1>;
541 			};
542 
543 			iim: efuse@10028000 {
544 				compatible = "fsl,imx27-iim";
545 				reg = <0x10028000 0x1000>;
546 				interrupts = <62>;
547 				clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
548 			};
549 
550 			fec: ethernet@1002b000 {
551 				compatible = "fsl,imx27-fec";
552 				reg = <0x1002b000 0x1000>;
553 				interrupts = <50>;
554 				clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
555 					 <&clks IMX27_CLK_FEC_AHB_GATE>;
556 				clock-names = "ipg", "ahb";
557 				status = "disabled";
558 			};
559 		};
560 
561 		nfc: nand-controller@d8000000 {
562 			#address-cells = <1>;
563 			#size-cells = <1>;
564 			compatible = "fsl,imx27-nand";
565 			reg = <0xd8000000 0x1000>;
566 			interrupts = <29>;
567 			clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
568 			status = "disabled";
569 		};
570 
571 		weim: memory-controller@d8002000 {
572 			#address-cells = <2>;
573 			#size-cells = <1>;
574 			compatible = "fsl,imx27-weim";
575 			reg = <0xd8002000 0x1000>;
576 			clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
577 			ranges = <
578 				0 0 0xc0000000 0x08000000
579 				1 0 0xc8000000 0x08000000
580 				2 0 0xd0000000 0x02000000
581 				3 0 0xd2000000 0x02000000
582 				4 0 0xd4000000 0x02000000
583 				5 0 0xd6000000 0x02000000
584 			>;
585 			status = "disabled";
586 		};
587 
588 		iram: sram@ffff4c00 {
589 			compatible = "mmio-sram";
590 			reg = <0xffff4c00 0xb400>;
591 			ranges = <0 0xffff4c00 0xb400>;
592 			#address-cells = <1>;
593 			#size-cells = <1>;
594 		};
595 	};
596 };
597