1 // SPDX-License-Identifier: ISC
2 /*
3  * Device Tree file for Intel XScale Network Processors
4  * in the IXP 4xx series.
5  */
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/gpio/gpio.h>
8 
9 / {
10 	soc {
11 		#address-cells = <1>;
12 		#size-cells = <1>;
13 		ranges;
14 		compatible = "simple-bus";
15 		interrupt-parent = <&intcon>;
16 
17 		/*
18 		 * The IXP4xx expansion bus is a set of up to 7 each up to 16MB
19 		 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
20 		 */
21 		bus@c4000000 {
22 			/* compatible and reg filled in by per-soc device tree */
23 			native-endian;
24 			#address-cells = <2>;
25 			#size-cells = <1>;
26 			ranges = <0 0x0 0x50000000 0x01000000>,
27 				 <1 0x0 0x51000000 0x01000000>,
28 				 <2 0x0 0x52000000 0x01000000>,
29 				 <3 0x0 0x53000000 0x01000000>,
30 				 <4 0x0 0x54000000 0x01000000>,
31 				 <5 0x0 0x55000000 0x01000000>,
32 				 <6 0x0 0x56000000 0x01000000>,
33 				 <7 0x0 0x57000000 0x01000000>;
34 			dma-ranges = <0 0x0 0x50000000 0x01000000>,
35 				 <1 0x0 0x51000000 0x01000000>,
36 				 <2 0x0 0x52000000 0x01000000>,
37 				 <3 0x0 0x53000000 0x01000000>,
38 				 <4 0x0 0x54000000 0x01000000>,
39 				 <5 0x0 0x55000000 0x01000000>,
40 				 <6 0x0 0x56000000 0x01000000>,
41 				 <7 0x0 0x57000000 0x01000000>;
42 		};
43 
44 		qmgr: queue-manager@60000000 {
45 			compatible = "intel,ixp4xx-ahb-queue-manager";
46 			reg = <0x60000000 0x4000>;
47 			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
48 		};
49 
50 		pci@c0000000 {
51 			/* compatible filled in by per-soc device tree */
52 			reg = <0xc0000000 0x1000>;
53 			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
54 				     <9 IRQ_TYPE_LEVEL_HIGH>,
55 				     <10 IRQ_TYPE_LEVEL_HIGH>;
56 			#address-cells = <3>;
57 			#size-cells = <2>;
58 			device_type = "pci";
59 			bus-range = <0x00 0xff>;
60 			status = "disabled";
61 
62 			ranges =
63 			/*
64 			 * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
65 			 * done in 4 chunks of 16MB each.
66 			 */
67 			<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
68 			/* 64KB I/O space at 0x4c000000 */
69 			<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
70 
71 			/*
72 			 * This needs to map to the start of physical memory so
73 			 * PCI devices can see all (hopefully) memory. This is done
74 			 * using 4 1:1 16MB windows, so the RAM should not be more than
75 			 * 64 MB for this to work. If your memory is anywhere else
76 			 * than at 0x0 you need to alter this.
77 			 */
78 			dma-ranges =
79 			<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
80 
81 			/* Each unique DTS using PCI must specify the swizzling */
82 		};
83 
84 		uart0: serial@c8000000 {
85 			compatible = "intel,xscale-uart";
86 			reg = <0xc8000000 0x1000>;
87 			/*
88 			 * The reg-offset and reg-shift is a side effect
89 			 * of running the platform in big endian mode.
90 			 */
91 			reg-offset = <3>;
92 			reg-shift = <2>;
93 			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
94 			clock-frequency = <14745600>;
95 			no-loopback-test;
96 		};
97 
98 		uart1: serial@c8001000 {
99 			compatible = "intel,xscale-uart";
100 			reg = <0xc8001000 0x1000>;
101 			/*
102 			 * The reg-offset and reg-shift is a side effect
103 			 * of running the platform in big endian mode.
104 			 */
105 			reg-offset = <3>;
106 			reg-shift = <2>;
107 			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
108 			clock-frequency = <14745600>;
109 			no-loopback-test;
110 		};
111 
112 		gpio0: gpio@c8004000 {
113 			compatible = "intel,ixp4xx-gpio";
114 			reg = <0xc8004000 0x1000>;
115 			gpio-controller;
116 			#gpio-cells = <2>;
117 			interrupt-controller;
118 			#interrupt-cells = <2>;
119 		};
120 
121 		intcon: interrupt-controller@c8003000 {
122 			/*
123 			 * Note: no compatible string. The subvariant of the
124 			 * chip needs to define what version it is. The
125 			 * location of the interrupt controller is fixed in
126 			 * memory across all variants.
127 			 */
128 			reg = <0xc8003000 0x100>;
129 			interrupt-controller;
130 			#interrupt-cells = <2>;
131 		};
132 
133 		timer@c8005000 {
134 			compatible = "intel,ixp4xx-timer";
135 			reg = <0xc8005000 0x100>;
136 			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
137 		};
138 
139 		npe: npe@c8006000 {
140 			compatible = "intel,ixp4xx-network-processing-engine";
141 			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
142 			#address-cells = <1>;
143 			#size-cells = <0>;
144 
145 			/* NPE-A contains two high-speed serial links */
146 			hss@0 {
147 				compatible = "intel,ixp4xx-hss";
148 				reg = <0>;
149 				intel,npe-handle = <&npe 0>;
150 				status = "disabled";
151 			};
152 
153 			hss@1 {
154 				compatible = "intel,ixp4xx-hss";
155 				reg = <1>;
156 				intel,npe-handle = <&npe 0>;
157 				status = "disabled";
158 			};
159 
160 			/* NPE-C contains a crypto accelerator */
161 			crypto {
162 				compatible = "intel,ixp4xx-crypto";
163 				intel,npe-handle = <&npe 2>;
164 				queue-rx = <&qmgr 30>;
165 				queue-txready = <&qmgr 29>;
166 			};
167 		};
168 
169 		/* This is known as EthB */
170 		ethernet@c8009000 {
171 			compatible = "intel,ixp4xx-ethernet";
172 			reg = <0xc8009000 0x1000>;
173 			status = "disabled";
174 			/* Dummy values that depend on firmware */
175 			queue-rx = <&qmgr 3>;
176 			queue-txready = <&qmgr 20>;
177 			intel,npe-handle = <&npe 1>;
178 		};
179 
180 		/* This is known as EthC */
181 		ethernet@c800a000 {
182 			compatible = "intel,ixp4xx-ethernet";
183 			reg = <0xc800a000 0x1000>;
184 			status = "disabled";
185 			/* Dummy values that depend on firmware */
186 			queue-rx = <&qmgr 0>;
187 			queue-txready = <&qmgr 0>;
188 			intel,npe-handle = <&npe 2>;
189 		};
190 
191 		/* This is known as EthA */
192 		ethernet@c800c000 {
193 			compatible = "intel,ixp4xx-ethernet";
194 			reg = <0xc800c000 0x1000>;
195 			status = "disabled";
196 			intel,npe = <0>;
197 			/* Dummy values that depend on firmware */
198 			queue-rx = <&qmgr 0>;
199 			queue-txready = <&qmgr 0>;
200 		};
201 	};
202 };
203